SU1249594A1 - Storage - Google Patents

Abstract

The invention relates to computing and can be used in the construction of storage devices of increased reliability. The purpose of the invention is to increase the speed of the device. The device contains memory blocks for storing data and initial page addresses, a control unit, an adder for address translation, a counter that generates regeneration addresses, a decoder, registers, multiplexers, a coding unit, a control unit. The device corrects a single error and detects a double error. Synchronous control mode provides high speed, because this eliminates the time needed to cover the variation of the parameters inherent in asynchronous circuits. , 4 silt, 2 tab.

Description

I 1

The invention relates to computing technology and can be usedN.

Called in storage devices.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of a memory device; in fig. 2 - diagram of the mode selector; in fig. 3 - scheme of the decoder operations; in fig. 4 shows a register decoder circuit.

The device (Fig. 1) contains the first memory block 1, the control block 2, the second memory block 3 used to store the initial page addresses, the adder 4, the counter 5, the decoder 6, the first 7, the second 8, the third 9, the fourth 10 and fifth 11 registers, first 12, second 13, third 14, fourth 15, fifth 16 and sixth 17 multiplexers, coding block 18, control block 19, first 20 and second 21 signal conditioners.

The control unit 2 consists of a mode selector, an operation decoder and a register decoder.

The mode selector is designed to select one of the modes: reversal, regeneration.

The mode selector (Fig. 2) contains a crystal oscillator 22 pulses, triggers 23 and 24, counter 25, AND-NO element 26, And 27-29 elements, register 30, one-shot 31, AND-NE element 32, HE element 33, register 34, elements AND 35, the element NOT 36, the element AND 37, the element NOT 38 and the element OR 39.

The decoder operations (Fig. 3) contains the element AND-NOT 40, the element OR 41, the element AND 42, the element OR-NOT 43, the element AND-NOT 44, the elements NOT 45-47, the elements AND 48 and 49, the elements AND-NOT 50 and 51, the element And 52 and the element INR-NOT 53.

The decoder registers (Fig. 4) contains the element OR 54, the element AND-NOT 55, the decoder 56, the element NOT 57, the elements OR 58 and 59, the element AND-NOT 60 and the element NOT 61.

The storage device operates as follows.

The device inputs the control signals Request, Write, Operation, Byte and 17 bits of the address. At the outputs of block 2, one of the modes is selected: access to memory, access to registers, regeneration.

ten

f5

249594 2

Appointment of managers

and executable operations are described in

tab. one ,

An example of the use of logical addresses is described in Table. 2

The seventeen-bit logical address received at the input of the device is converted to a 21-bit physical address as follows.

In block 3, the starting addresses of the memory pages are pre-recorded.

When accessing the memory, the five most significant bits of the logical address are transmitted through multiplexer L 7 and are used to select one of the registers of block 3. From this register, the starting address of the memory page is read. The lower 12 bits of the logical address are used to determine the offset within the page.

The physical address is formed on the adder 4 by adding the initial 25 address and offset and is stored in register 11. The upper 5 bits of the physical address and the control signals are stored in register 8. The upper bits of the address are used to select the memory module of block 1 on the decoder 6 and to select the chip family inside the module.

The lower seventeen bits are multiplexed on block 15, which forms two dressings: the row address and the column address.

In the Write to Memory operation, the data is stored in register 9 and transmitted through multiplexer 14.

Block 18 generates check bits for the Hamming code.

Block 2 generates a row address strobe, a column address strobe, write resolution, a Response signal that is output to the device.

35

40

45

50

va.

During the Read Memory operation, the address and control signals for the memory block are generated in the same way as when writing.

The information is read from memory block 1 and fixed to register 7 and in block 19.

The control unit I9 checks the correctness of the read code. In the absence of an error, the data from register 7 through the switch 12 arrive at the outputs of the device.

Block 2 generates a row address strobe, a column address strobe, write resolution, a Response signal that is output to the device.

va.

During the Read Memory operation, the address and control signals for the memory block are generated in the same way as when writing.

The information is read from memory block 1 and fixed to register 7 and in block 19.

The control unit I9 checks the correctness of the read code. In the absence of an error, the data from register 7 through the switch 12 arrive at the outputs of the device.

3

In the case of a single error, a single error signal is output to control unit 2 on element 60, which generates a correction enable signal, which includes the output of block 19. The NOT element of 61 block 2 turns off the outputs of register 7. Scattered data from the output of block 19 through switch 12 arrive at the outputs of the device.

When a double error occurs in block 19, a double error signal is generated and output to the device.

During the operation Write byte, the word is read at the specified address, then from register 9 one data byte is received to switch 14, register 7 is used by another

Block 18 generates check bits. Thus, the data and check bits come into memory block 1. This completes the recording of one byte and the regeneration of another. The request for regeneration is generated in block 2 by means of a counter 25, a trigger 24, and an AND element 26.

The sign of the regeneration mode in block 2 is formed with the help of element 27 on the third trigger of register 30, after which the first trigger of register 30 is cocked and a single vibrator 31 is started, which forms the gate of the regeneration address. The current regeneration address is generated on the counter 5 and transmitted through the multiplexer 15 to the memory unit 1.

The regeneration address increment is raised along the falling edge of the regeneration address strobe. Register 10 provides for the execution of diagnostic operations. Zero bit of register 10 cancels the correction of single errors in order to ensure the test control of the data bits of block 1.

The first bit of register 10 cancels the formation of correct check bits and allows the writing of arbitrarily specified check bits from register 10 to block 1 for the purpose of

five

ten

15

20

495944

providing test control check bits of block 1, as well as simulating errors and checking block 19.

Bit 2-7 register 10 serves to receive the check bits read from the memory, or the upper bits of the address in case of double error, in order to localize the detected fault, as well as to receive arbitrary check bits from the information input of the device.

The multiplexer 13 transmits the address or data to the register 10 (depending on the code of the first bit of the register 10). The shaper 21 performs the transfer of arbitrary test bits from register 10 to block 1. During the operation of accessing registers, the sixth trigger of register 30 of block 2 forms a sign of the mode of addressing registers. Address decoder 56 enables the selection of a register.

When reading from register 11, its data arrive at the output of the device. Register 11 is used to test control the formation of a physical address. When reading from register 10, its data is sent to the output of the device through multiplexer 12. When accessing memory block 3, multiplexer 17 transmits the lower five bits of the address to the inputs of block 3. During an operation, the write signals are received from the OR 58 and 59 elements of block 2 respectively, in the low or high word of block 3, the ac shaper 20 receives data.

During a read operation, data from the output of block 3 is fed through multiplexer 16 to the output of the device. The multiplexer 16 performs a lower or higher (depending on the lower bit of the address) word read from block 3 to the output of the device.

25

0

five

0

five

When reading registers, one of blocks 11, 16 and 12 (depending on the selected register) is derived from the third state.

Table 1

Addresses

0-367777 370000-370077

370100, 370101 370102

Claims (1)

Invention Formula A memory device containing the first memory unit, the first and second registers, the first and second multiplexers, the decoder, the coding unit, the control unit and the control unit, the output of the first memory unit connected to the first input of the first register, the second input of which and the first input of the first the multiplexer is connected to one of the outputs of the control unit; the first output of the first register is connected to the second input of the first multiplexer, the output of which is the first code of the device, characterized in that, in order to increase quickly in action, the registers from the third to the last, multiplexers from the third to the sixth second memory block, the adder, the counter, the first and second signal conditioners, and the other outputs of the control unit are connected to the first to third multiplexers of the third to sixth registers, c. second by fifth, memory blocks, control and counter blocks and are - Continuation of table 1 Write About Byte Write 1 Byte Table 2 Purpose Memory Block 3 registers Register 1I Register 10 With the second output of the device, the first inputs of the coding unit, the second signal conditioner and the second multiplexer are connected to the first output of the fourth register, the first input of the control unit and the second input of the second register are the control input of the device, the information inputs of which are the third and fourth inputs registers, address input - the second inputs of the control unit and the sixth multiplexer and the first input of the accumulator, the third input of the control unit is connected to the first output of the second register, the second the output of the fourth register and the first output of the control unit, the output of the sixth multiplexer is connected to the address input of the second memory block, whose information input is connected to the output of the first signal conditioner whose input is connected to the output of the third multiplexer, the second inputs of the coding block and the first memory block, the third input of which is connected to the output of the decoder, the input of which is connected to the second output of the second register, the third input of which The first is connected to the output of the adder, the second inputs of the fifth register, the second and fourth multiplexers, the third input of the fourth multiplexer is connected to the top of the counter, and the output is connected to the fourth input of the first memory block, the fifth input is connected to the outputs of the coding block and the second signal conditioner, the second input of which is connected to the third output of the fourth register and the second input of the first multiplexer, the output of the first register is connected to the second; the input of the third multiplexer and the second input and output of the terminal block The troll, the outputs of the fifth register and the multiplexer are connected to the first output of the device, the third output of which is the first output of the control unit, the output of the second memory block is connected to the second inputs of the szmmmator and the fifth multiplexer, the output of the third register is connected to the third input of the third multiplier (IP The output of the second multiplexer is connected to the third input of the fourth register, the third output of the second register is connected to the sixth input of the memory unit, the second output of the first register is connected to the third one, the third input of the second multiplexer. 1 FIG. 2