SU1339654A1 - Device for checking magnetic memory integrated circuits - Google Patents

Abstract

The invention relates to computing and can be used in the development of storage devices on cylindrical magnetic domains. The object of the invention is to simplify the device; The device for monitoring magnetic integrated circuits of the memory contains counter 1, control unit 2, memory block 3, multiplexer 4. The counting input of counter 1 is informational input 5 of the device. The reset input of counter 1 is connected to the first input of control unit 2 and is the reset input 6 of the device. The second input of the control unit 2 is the first control input 7 of the device, the third input of the control unit 2 is the second control input 8 of the device, the fourth input of the control unit 2 is the third control input 9 of the device. The information input of the multiplexer 4 is connected to the data output of unit 3. The first output of the multiplexer 4 is connected to the information input of the counter 1, and the second output of the multiplexer 4 is the output 10 of the device. The output of counter 1 is connected to the data input of unit 3. The first output 11 of control unit 2 is connected to the reception enable input to the counting input of counter 1, the second output 12 of control unit 2 nd input of write enable on information input of counter 1, the third output 13 of control unit The 2nd input of the read mode setting of the block 3, the fourth output 14 of the control unit 2 with the sample input of the block 3, the fifth output 5 of the control unit 2 with the address input of the block 3, the sixth output 16 of the control unit 2 with the control input of the multiplexer 4 , 2 Il. e (L with so with O5 SP 4

Description

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The invention relates to computing and can be used in the development of storage devices on cylindrical magnetic domains (IC),

The aim of the invention is to simplify the device.

Fig. I shows a block diagram of the proposed device; 2 is a block diagram of a control unit;

A device for monitoring magnetic integrated circuits of a memory contains a counter 1, a control block 2, a RAM block 3, a multiplexer 4, the counter input of the counter 1 is information input 5 of the device, a reset input of the counter: a. connected to the first input of control unit 2 and is a device reset input 6, the second input of control unit 2 is the first, control input 7 of the device, the third input of control unit 2

20 of the first input element And 25 and with the input of the delay element 19, the output of which is connected to the first input of the element 24, the R input of the trigger 27 and the input of the delay element 20, the output

NIN is the second control input 8 of the device, the fourth input of the block 25 of which is connected to the first control input 2 is the third unit of the WL-HE 26 and the input of the element is the input input 9 of the device. The information input of the multiplexer 4 is connected to the data output unit 3 ,. the first output of multiplexer 4 is connected to the information input of counter 1, and the second output of multiplexer 4 is the output 10 of the device. The output of counter 1 is connected to the data input of unit 3, the first output II of control unit 2 is connected to the input enable input to the counting input of counter 1; the second output 12 of the control unit 2 - with the write enable input on the information input of the counter 1, the third output 13 of the control unit 2 - with the input of the setting of the read-write mode of the unit 3; the fourth output 14 of control unit 2 is with the sample input of unit 3; Fifth output 15 of control unit 2 - with address block input

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This 21 delays, the output of which is connected to the counting input of the counter. 29. Element output AND 24 is the first.

30, the output 11 of the control unit 2, the output of the OR-ME element 26 is the fourth output 14 of the control unit 2, the output of the trigger 27 is the third output 13 of the control unit 2,

The RAM unit 3 is intended to store the current values of the number of failures outputted by the cumulative registers of the tested magnetic integrated circuit. Each cumulative register corresponds to a separate word in block 3, On the digging registers from to K, there corresponds an area of address space from O to K-1.

The proposed device works in the following way.

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3; The sixth output 16 of the control unit 2 with the control input of the multiplexer 4.

The control unit 2 (FIG. 2) includes five delay elements 17-21, two elements OR 22 and 23, two elements AND 24 and 25, element OR-NOT 26, two RS flip-flops 27 and 28, and an address counter 29. The first and second inputs 6 and 7 of control unit 2 are the first and second inputs of the element OR 22, the output of which is connected to the reset input of the counter 29, the output of which is

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It is controlled by the fifth output 15 of the control unit 2. The third input 8 of the control unit 2 is the first input of the j element 23 and the S input of the trigger 28, the output of which is the sixth output 16 of the control unit 2. The fourth input 9 of control unit 2 is the second input of the element OR 23,

10 the R-input of the trigger 28, the second input of the AND 24 element, and the second input of the AND 25 element, the output of which is the second output 12 of the control unit 2. The output of the element OR 23 is connected

15 with the S-input of the trigger 27 and with the input of the delay element 17, the output of which is connected to the second input of the OR-NOT element 26 and to the input of the delay element 18, the output of which is connected to

20 of the first input element And 25 and with the input of the delay element 19, the output of which is connected to the first input of the element 24, the R input of the trigger 27 and the input of the delay element 20, the output

25 of which is connected to the first input of the element ШШ-НЕ 26 and to the input of the element

which is connected to the first input of the element ШШ-НЕ 26 and to the input of the elements

that 21 delays, the output of which is connected to the counter input of the counter. 29. Element output AND 24 is the first.

the output 11 of the control unit 2, the output of the OR-ME element 26 is the fourth output 14 of the control unit 2, the output of the trigger 27 is the third output 13 of the control unit 2,

The RAM unit 3 is designed to store the current values of the number of failures outputted by the cumulative registers of the tested magnetic integrated circuit. Each cumulative register corresponds to a separate word in block 3, Cumulative registers from to K-th corresponds to the area of the address space from O to K-1.

The proposed device works in the following way.

The main control signals in this mode are external signals. Data is ready (at input 9 of the device) and Nova page (at input 7 of the device). Signal Data is ready indicating that a new bit has been read from the checked magnetic integral, and Nova

page - that begins reading the new data block from the magnetic integrated circuit. On signal The data is ready the control unit 2 produces five auxiliary

sync pulses generated by delay elements 17-21.

The first data signal is ready. The B state determines the output of control block 2 connected to the control input of multiplexer 4, which leads to switching the output of block 3 to the information input of the error counter 1,

The sequence of actions on the signal The data is ready as follows: the output 13 of control unit 2 sets the reading mode of unit 3, the output 14 of control unit 2 outputs the sampling signal of unit 3, the output from unit 12 of control unit 2 outputs the output data of unit 3 to error counter 1, the signal from the output 11 of the control unit 2 allows reception to the counting input of counter 1; in case of an external signal Error (on input 5 of the device) the contents of the counter are increased by 1, the output 13 of the control unit 2 sets the recording mode of the unit 3, the output 14 of the control unit 2 enhances the signal sample and block 3, - according to which the modified or unchanged information from the error counter 1 is entered into the addressable cell of block 3, the contents of the address counter 29 are increased by 1.

When the signal arrives, the new page resets the counter 29 of the address, which allows restoring the correspondence between the address space of block 3 and the polled registers of the magnetic integrated memory circuit that are polled.

The mode of data output to the system is organized by an external signal transfer (via input 8 of the device). To output from the block, K layers are sent to K signals. Transfer, each word is followed by cleaning the selected cell of block 3.

The first signal Overflow switches multiplexer 4 to supply data from the data output of block 3 to output 1C of the device.

The sequence of signal operations. Forwarding is as follows: the output 13 of control unit 2 sets the reading mode of unit 3, the output 14 of control unit 2 outputs the sample signal of unit 3, and the read data is output to the device, the output 13 of control unit 2 sets the recording mode of unit 3, output 14 control unit 2 generates a sampling signal of unit 3; by which zero information from the output of the error counter 1 is entered into the addressable memory cell, the contents of the address counter 29 are incremented by I.

Claims (1)

Invention Formula 0 five 0 AT 0 five 0 A device for monitoring magnetic integrated circuits of a memory, comprising a counter and a control unit, characterized in that, in order to simplify the device, it contains a memory unit and a multiplexer, the counter input of which is an information input of the device, the counter reset input is connected to the first input of the control unit and is the reset input of the device; the second, third and fourth inputs of the control unit are respectively the first, second and third control inputs of the device; the first output of the control unit It is connected to the reception enable input on the counter counting input, the second output is connected to the write enable input on the information input of the counter, the third output is to the installation input of the read-write mode of the random access memory, the fourth output is with the sample input of the random access memory, the fifth output — with the address input of the operating memory unit; the sixth output — with the control input of the multiplexer, whose information input is connected to the data output of the operating memory unit, the data input of which is connected to the output of the counter; second input of which is connected to first output multiplexer, a second output of which is a data output device. Editor N.Lazarenko Compiled by Y.Rosenthal Tehred M.Didyk Order 4232/44 Circulation 589 Subscription BNISH the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader M. Pojo