KR0158249B1 - Series acess memory apparatus - Google Patents

Abstract

The serial access memory device of the present invention includes a memory cell array having a first data terminal and a plurality of address storage locations. This device consists of a shift register and an address decode circuit. The shift register stores a first address value of a serial access memory operation in response to an address clock signal. And an input terminal connected to the first data terminal. The address decode circuit sequentially accesses a plurality of address storage locations of the memory cell array, and responds to an access control signal, the first address value, an address clock signal, and a clock signal.

Description

Serial Access Memory Device

1 is a conventional voice recorder system.

2 is a voice recorder system according to the present invention.

3 is a timing diagram of transmission of a first address value according to the present invention;

4 is a diagram illustrating a specific function of a serial access memory device according to the present invention.

5 is a timing diagram of a memory write operation according to the present invention.

6 is a configuration diagram of the edge detector function shown in FIG.

7 is a flowchart showing that a write signal and a read signal are generated from a clock signal and an access control signal.

8 is another embodiment of the present invention.

9 is a concrete development diagram of the reset function shown in FIG.

10 is a correlation timing diagram of signals according to FIG. 9;

11 is a circuit diagram for performing an edge detector function and a reset function according to the present invention.

The present invention relates to a memory device, and more particularly, to a serial access integrated circuit memory device.

In order to meet the needs of today's multimedia computer systems, integrated circuit memory devices are being used in recent years to store enormous amounts of information, such as audio and video information. Information such as audio or video is characterized by a continuous flow of data. That is, such information is often stored and retrieved in sequential or serial fashion.

The prior art has two approaches to address the problem of digital voice storage. The first is to use a single chip that integrates the controller function as well as the voice storage memory function. This kind of system method has the drawback of system stiffness. For example, the minimum required capacity of an integrated circuit memory device for a 12 inch voice recording system is different from that of 6 inches. In such a situation, even if the controller embedded in the chip meets the needs of the user, it is only necessary to change the entire chip due to the limitation of the memory function itself.

The second is to employ two chips as shown in FIG. The first chip 13 performs a voice controller function and the second chip 11 performs a voice storage function. This method clearly has the flexibility of the system rather than the method described above.

However, this method has many drawbacks. The first drawback is that many pins are needed. Taking 256K SRAM as an example, required interface pins include at least A0-A14 address lines, D0-D7 data lines, memory read (RD) and memory write (WR) lines, chip select (CS) control lines, Vdd. You need things for the and Vss lines. The second drawback is the ease of expansion of memory capacity. When the need for expansion from 256K to 1 megabit is required, new address lines A15 and A16 are needed for the second chip 11. A third drawback is the need for a pin on the first chip 13. Since the controller 13 needs to know whether the memory chip 11 is empty for a predetermined memory operation, a plurality of selection signals M1 and M2 indicating the memory type being used are required for this controller 13. In FIG. 1, device 15 is an indicator light, 17 is a speaker and 19 is a microphone.

The first object of the present invention to solve the disadvantages inherent in the prior art as described above is to provide a serial access memory device having fewer pins than the conventional one. It is a second object of the present invention to provide a serial access memory device requiring only one data line, one address clock line, one clock line and one access control signal for access. It is a third object of the present invention to provide a serial access memory device whose pin configuration is not affected by its memory capacity. A fourth object of the present invention is to provide a serial access memory device in which a plurality of memory locations are accessed by receiving a first address value of the memory operation from the controller.

The serial access memory device according to the present invention includes one memory cell array having one first data terminal and a plurality of address storage locations. The serial access memory device is composed of one shift register and one address decode circuit.

The shift register stores a first address value of a serial access memory operation in response to an address clock signal. The shift register has a first input terminal connected to the first data terminal. The address decode circuit sequentially accesses a plurality of address storage locations of the memory cell array, and responds to an inhibit control signal, the first address value, the address clock signal, and a clock signal.

The spirit and specific configuration of the present invention will be described below in conjunction with the accompanying drawings.

As shown in FIG. 2, the serial access memory device 21 according to the present invention is connected to the voice recorder controller 23. FIG. Information lines include one clock line (CLK) 230, address clock (ADD CLK) line 210, bidirectional data (DATA) line 220, memory read / write (WR / RD) line 240, and chip select (CS) line 250. End of memory (EOM) line 260. The memory read / write line 240 is a memory access control line.

Data of the memory device 21 having a plurality of address memory locations is sequentially accessed via the data line 220. The first address value of the data input terminal DATA serial access memory operation of the memory device 21 is sequentially input for a predetermined time, and the data is sequentially transmitted for the remaining time. The transmission timing relationship of the first address value through the data line 220 is shown in FIG.

As shown in FIG. 4, the serial access memory device 21 includes a shift register 42, which resists the first address value of the serial access memory operation in response to the address clock signal 210. FIG.

The shift register 42 includes a first input terminal connected to a data input terminal DATA of the memory device 21. The serial access memory device 21 includes an address decode circuit 44. The circuit 44 includes a plurality of memory cell arrays 46 in response to a write signal 241, a read signal 242, the first address value 421, and the address clock signal 210. The address storage locations of S are sequentially accessed. Both the write signal 241 and the read signal 242 are related to the clock signal 230 and the memory write / read signal 240, which will be described below.

The shift register 42 has N data registers 420, each register connected in series with each other. Each of the N data registers includes a data output terminal Q, a clock input terminal CLK, and a data input terminal D. The data input terminal of the first data register of the N data registers is the first input terminal of the shift register 42 and is also connected to the data input terminal DATA. The clock input terminal of each data register receives the address clock signal 210.

The address decode circuit 44 includes one address latch / counter 442, each having N input terminals connected to the data output terminal of a corresponding data register 420, and in response to a load signal 448. The first address value is latched, and the value of the address storage location accessed by the increment signal 446 is incremented.

The address decode circuit 44 has an EOM terminal for outputting an end of memory signal 260 when the last memory location of the memory cell array 46 is accessed.

The address decoder Hiro 44 further includes an edge detector 444, which generates the load signal 448 and the incremental signal 446 in response to the memory read / write 240, the clock signal 230 and the address clock signal 210. .

The serial access memory device 21 is connected to the data input terminal DATA and the memory cell array 46, respectively, and transmits data corresponding to an address memory location accessed in response to the memory read / write signal 240 and the clock signal 230. One data buffer 48 is provided.

The timing of the memory write operation according to the present invention is shown in FIG. 5, where the end of memory (EOM) signal 260 goes high when the last memory location is accessed.

In the preferred embodiment of FIG. 5, the memory write operation is recognized when the memory write / read signal 240 is 'high' by the controller 23, and the memory read operation is performed by the memory write / read signal 240 to the controller 23. Is recognized as low.

One embodiment of the above edge detector 444 has one NAND gate 60, a first NOR gate 62, a second NOR gate 64, an inverter 66, a delay line 67 and an AND gate 68, as in FIG. The NAND gate 60 has two input terminals for receiving a read signal 242 and a write signal 241, and an output terminal for generating the incremental signal 446.

The first NOR gate 62 includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal receives the incremental signal 446. The second NOR gate 64 has a third input terminal, a fourth input terminal and a second output terminal. The third input terminal receives the address clock signal 210, the fourth input terminal is connected to a first output terminal of the first NOR gate 62, and the second output terminal is connected to a second input terminal of the first NOR gate 62. In addition, a second output signal 641 is generated. The inverter 66 has a fifth input terminal and a third output terminal. The fifth input terminal is connected to a second output terminal of the second NOR gate 64 and the third output terminal generates a third output signal 661. The AND gate 68 generates the load signal 448 in response to the second output signal 641 and the third output signal 661.

Referring to FIG. 7, the write signal 241 is generated by NANDING the clock signal 230 and the memory read / write signal WR / RD 240, and the read signal 242 is generated by the clock signal 230. The inversion signal of the memory read / write signal 240 is generated by a negative logic.

As in the preferred embodiment described above, the present invention provides advantages as described below over the prior art.

First, only one data line 220 and one address clock line 210 are needed to serially access the memory cell array 21 at a competitive access speed. Second, the interface pins between the controller 23 and the memory device 21 are constant regardless of the capacity of the memory device, i.e. 256K, 1M, and so on. Third, the address latch / counter 442 embedded in the memory device 21 accesses the last address memory location and outputs an end of memory signal 260 to the controller 23. Therefore, it is not necessary to supply the selection signals M1 and M2 for the type (capacity) of the memory used, thereby reducing the number of pins. Fourth, other shapes or different lengths of the memory device 21 may be connected to the same controller without changing the same memory device 21 or the controller 23. There may be one drawback in the configuration of the present invention as described above.

Since the number of the data registers 420 is fixed, for example, in the case of 20 data registers 420 in 1M SRAM, the address clock signal 210 needs 20 clocks to accurately access the memory cell array 46. If the controller 23 sends more than 20 clocks on the address clock line 210, the shift register 420 receives only the last 20 data sent on the data line 220, eventually resulting in that type of memory access operation. It is limited by the size of the memory device 21. However, if the controller 23 sends the number of clocks less than 20 on the address clock line 210, an error will occur due to the residual bit value in any upper bit position of the shift register 42.

The arrangement disclosed in FIG. 8 is another embodiment according to the present invention for solving the above-described drawbacks of the first embodiment. The illustrated serial access memory device has a shift register 42, an address latch / counter 442, a memory cell array 46, an edge detector 444, and a data buffer 48 as in the configuration of the first embodiment.

Since the functions and operations of most of the devices shown in FIG. 8 are the same as the corresponding portions of the first embodiment of FIG. 4 in the corresponding input signals, repeated descriptions will be omitted below.

The reset function 450 of FIG. 8 responds to the address clock signal 210, the read signal 242, and the write signal 241, and generates a reset signal 452 to reset the shift register 42. A preferred configuration embodiment of the reset function 450 is the same as in FIG.

As shown, the reset function 450 includes one NAND gate 90, one NOR gate 92, a second NOR gate 94, an inverter 96, a delay line 96, and a NOR gate 98. The NAND gate 90 has two input terminals and one output terminal for receiving the read signal 242 and the write signal 241, respectively.

The first NOR gate 92 has first and second input terminals and a first output terminal. The first input terminal is connected to an output terminal of the NAND gate 90. The second NOR gate 94 has third and fourth input terminals and a second output terminal.

The third input terminal receives the address clock signal 210, the fourth input terminal is connected to a first output terminal of the first NOR gate 92, and the second output terminal is connected to the first output terminal of the first NOR gate 92. It is connected to the second input and also generates a second output signal 941. The inverter 96 has a fifth input terminal and a third output terminal. The fifth input terminal is connected to the second output terminal of the second NOR gate 94 and the third output terminal generates a third output signal 961. The NOR gate 98 generates the above-described reset signal 452 in response to the second output signal 941 and the third output signal 961.

In FIG. 9, timing diagrams of signals of respective parts are shown in FIG. The write signal 241 and the read signal 242 are generated by the circuit shown in FIG.

Since the reset signal 452 is asserted at the first active address clock 210 after the previous read signal 242 or the write signal 241 is de-asserted, the shift register 42 is accordingly. The next first address value, which is reset and synchronized with the address clock signal 210, is correctly stored, and the number of bits is smaller than the number of the data registers 420. In some higher bit positions, the error according to the above-described current value does not occur accordingly. The specific configurations of the embodiments according to the present invention mentioned above are not limited thereto but merely exemplary.

Any equivalent alterations, substitutions, alterations or modifications that may be made to the above-described embodiments without departing from the spirit of the present invention are possible to those skilled in the art and the following claims It still remains within the protection scope of the present invention. For example, the edge detector 444 shown in FIG. 6 and the reset circuit of FIG. 9 can be easily combined into the circuit shown in FIG. 11 to generate the reset signal 452, the incremental signal 446 and the load signal 448. As can be, it is obvious to those skilled in the art.

Claims (20)

One single data terminal for serially receiving a first address value during a first period and for serially transmitting or receiving a plurality of sets of data signals during a second period; One memory cell array having a plurality of address storages respectively storing one set of a plurality of sets of data signals; One shift register for storing one first address value of one serial access memory operation, received from the single data terminal during the first period, in response to one address clock signal; One address for serially accessing a plurality of address storages of the memory cell array in response to one read access or one write access control signal, the first address value, the address clock signal, and one clock signal Decode circuits; It is configured to include; A plurality of sets of data signals serially received from the single data terminal are stored in the plurality of address storages by the write access control signal applied during the second period, and the read access control applied during the second period. And a plurality of sets of data signals from the plurality of address storages are serially transmitted through the single data terminal in response to the read access control signal and the clock signal by means of a signal. . 2. The shift register of claim 1, wherein the shift register comprises N data registers connected in series with each other, and the N data registers each include one data output terminal Q, one clock input terminal CKL, and one data input terminal. (D), wherein the data input terminal of the first data register is connected to the single data terminal, and the clock input terminal of each data register is for receiving the address clock signal. 3. The address decoding circuit as set forth in claim 2, wherein said address decode circuit comprises one address latch / counter having N input terminals, each connected to said data output terminal Q of one corresponding data register, and in response to a load signal; And latching the first address value of and incrementing the value of the address latch / counter in response to the incremental signal. 2. The serial access memory of claim 1 wherein the address decode circuit comprises one end of memory (EOM) terminal for sending an end of memory signal when the last memory location of the memory cell array is accessed. Device. The method of claim 2, wherein the address decode circuit further comprises an edge detector for generating the load signal and the increment signal in response to the read or write access control signal, the address clock signal and the clock signal. Serial access memory device. The method of claim 5, wherein the edge detector; A NAND gate having two input terminals for receiving a read access control signal and a write access control signal, respectively, and one output terminal for generating an incremental signal; A first NOR gate having a first input terminal, a second input terminal and a first output terminal, the first input terminal receiving the incremental signal; And a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal receives the address clock signal, the fourth input terminal is connected to a first output terminal of the first NOR gate, and the second output terminal is connected to the first output terminal. A second NOR gate connected to a second input terminal of the first NOR gate and generating a second output signal; An inverter having a fifth input terminal and a third output, the fifth input terminal being connected to a second output terminal of the second NOR gate, the third output terminal generating a third output signal; An AND gate for outputting the load signal in response to the second and third output signals; Serial access memory device, characterized in that consisting of. One single data terminal for serially receiving one address signal during a first period and for transmitting or receiving a plurality of sets of data signals during a second period; One memory cell array having a plurality of address storages; A plurality of sets of data signals serially received from the single data terminal connected to the single data terminal and the memory cell array, respectively, during the second period and by the write access control signal applied to the plurality of address storages. And a plurality of sets of data signals from the plurality of address storages are serially transmitted through the single data terminal in response to the read access control signal and a clock signal during the second period and by the applied read access control signal. One data buffer to be transmitted to; And a serial access memory device. 8. The method of claim 7, wherein in response to one address clock signal, one shift register for storing one first address value of one serial access memory operation received from the single data terminal during the first period. And, further comprising a serial access memory device. The shift register of claim 8, wherein the shift register comprises N data registers connected in series with each other, wherein the N data registers each include one data output terminal (Q), one clock input terminal (CKL), and one data input terminal. (D), wherein the data input terminal of the first data register is connected to the single data terminal, and the clock input terminal of each data register is for receiving the address clock signal. 10. The apparatus of claim 9, wherein the address decode circuit comprises one address latch / counter having N input terminals, each connected to the data output terminal Q of one corresponding data register, and in response to a load signal. And latching the first address value of and incrementing the value of the address latch / counter in response to the incremental signal. 8. The serial access memory of claim 7, wherein the address decode circuit comprises one end of memory (EOM) terminal for sending an end of memory signal when the last memory location of the memory cell array is accessed. Device. 11. The apparatus of claim 10, wherein the address decode circuit further comprises an edge detector for generating the load signal and the increment signal in response to the read or write access control signal, the address clock signal, and the clock signal. Serial access memory device. The method of claim 12, wherein the edge detector; A NAND gate having two input terminals for receiving a read access control signal and a write access control signal, respectively, and one output terminal for generating an incremental signal; A first NOR gate having a first input terminal, a second input terminal and a first output terminal, the first input terminal receiving the incremental signal; A third input, a fourth input, and a second output, wherein the third input receives the address clock signal, the fourth input is connected to a first output of the first NOR gate, and the second output is A second NOR gate connected to a second input terminal of the first NOR gate and generating a second output signal; An inverter having a fifth input terminal and a third output terminal, wherein the fifth input terminal is connected to a second output terminal of the second NOR gate, and the third output terminal generates a third output signal; An AND gate for outputting the load signal in response to the second and third output signals; Serial access memory device, characterized in that consisting of. The method of claim 1, further comprising a reset circuit responsive to a read access or write access control signal, a clock signal, and an address clock signal to generate a reset signal for resetting the shift register. Serial Access Memory Device. 15. The shift register of claim 14, wherein the shift register comprises N data registers connected in series with each other, wherein the N data registers each include one data output terminal (Q), one clock input terminal (CKL), and one data input terminal. (D), wherein the data input terminal of the first data register is connected to the single data terminal, and the clock input terminal of each data register is for receiving the address clock signal. 16. The apparatus of claim 15, wherein the address decode circuit comprises one address latch / counter having N input terminals, each connected to the data output terminal of one corresponding data register, the first decoding latch in response to a load signal. And latching an address value and for incrementing the value of said address latch / counter in response to an incremental signal. 15. The apparatus of claim 14, wherein the address decode circuit has an output stage for sending an end of memory signal when the address decode circuit is accessed to the last memory location of the memory cell array. 17. The apparatus of claim 16, wherein the address decode circuit further comprises an edge detector for generating the load signal and the increment signal in response to the read or write access control signal, the address clock signal, and a clock signal. Serial access memory device. 19. The device of claim 18, wherein the edge detector; A NAND gate having two input terminals for receiving a read access control signal and a write access control signal, respectively, and one output terminal for generating an incremental signal; A first NOR gate having a first input terminal, a second input terminal, and a first output terminal, the first input terminal receiving the incremental signal; A third input, a fourth input, and a second output, wherein the third input receives the address clock signal, the fourth input is connected to a first output of the first NOR gate, and the second output is A second NOR gate connected to a second input terminal of the first NOR gate and generating a second output signal; An inverter having a fifth input terminal and a third output terminal, wherein the fifth input terminal is connected to a second output terminal of the second NOR gate, and the third output terminal generates a third output signal; An AND gate for outputting the load signal in response to the second and third output signals; Serial access memory device, characterized in that consisting of. 15. The apparatus of claim 14, wherein the reset circuit comprises: a reset circuit; A NAND gate having two input terminals and one output terminal for receiving a read access control signal and a write access control signal, respectively; A first NOR gate having a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal is connected to an output terminal of the NAND gate; And a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal receives the address clock signal, the fourth input terminal is connected to a first output terminal of the first NOR gate, and the second output terminal. A second NOR gate connected to a second input terminal of the first NOR gate and generating a second output signal; An inverter configured to have a fifth input terminal and a third output terminal, the fifth input terminal being connected to a second output terminal of the second NOR gate, and the third output terminal generating a third output signal; And one NOR gate generating the reset signal in response to the second and third output signals; Serial access memory device, characterized in that consisting of.