SU1081669A1 - Storage with self-check - Google Patents

Abstract

STORAGE DEVICE WITH AUTONOMOUS CONTROL, containing a drive, number register, modulo convolution block two, unit number analysis block and reversible counter block whose outputs are connected to the unit number analysis block inputs, the information input of the device is the first input of the number register, the first output of which Connected to the input of the accumulator, characterized in that, in order to increase the speed of the device, an additional number register, a modulo-two adder unit, the element And, the first and second are entered into it. Cements OR, the first and second blocks of the OR elements, the block of elements AND, the accumulator outputs connected to one input of an additional number register, the other inputs of which are connected to one output of the unit number analysis unit, the other output of which is the first output of the device, the second output register the numbers are connected to the first input of the block of adders modulo two, the second input of which is connected to the first output of the additional register of the number and the first input of the block of elements I, the outputs of the block of adders modulo two connect are not connected to the inputs of the second OR element, the output of which is connected to the first input of the AND element, the second input of which is connected to the second input of the AND element block and is one control input of the device, the output of the AND element is connected to the second input of the number register and the first input of the first OR element , the second input of which is connected to the second output of the additional number register and is the second output of the device, the second output of the number register is connected to the first input of the second block of OR elements, the second input of which is i another equal output of the device, the output of the block of adders modulo two (L is connected to the first input of the first block of elements OR, the second input of which is connected to the output of the block of elements AND, the outputs of the first, second blocks of elements OR and the first element OR are connected respectively to the first, second and the third inputs of the reversible counter block, the third output of the additional register of the number of CX) is connected modulo two to the input of the convolution block, the output of which is the third O5 output of the device, the fourth output is up to O5 additional register and the number is the fourth output device and connected to the third input of the register.

Description

The invention relates to memory devices and can be used to create a highly reliable memory in which data is monitored over arrays. A memory device with autonomous control is known, which contains a drive, a number register, a modulo two convolution block, an adder, a control word register and a unit number analysis block. In such a device, when a data is written in the adder, a control word is formed which is then sent to the control word register. In the modulo two modulus of the convolution block HELP reading mode, all the words from the accumulator data array are alternately read and added to the control word B of the adder. In this case, a word is formed in the adder, containing zeros in the bits corresponding to the bits of the memory device in which there is no error or error of even multiplicity, and units in bits where there are errors of odd multiplicity. A single error is corrected by reading the word with the error from the drive, adding it with the contents of the adder and writing it to the same address in drive 1. The disadvantages of the known device are the limited control possibilities, which consist in the fact that only odd multiplicity errors are detected and single errors are corrected, as well as additional operations associated with sending the control word from the adder to the control word register and vice versa, which reduces reliability and device speed. The closest in technical essence to the invention is a memory device with autonomous control, comprising a drive, a number register, a modulo two convolution unit, a unit number analysis unit and reversible counters by the number of device bits, one of the inputs of which is connected to one output of the number register , the other inputs are control, and the outputs are connected to the inputs of the unit analysis unit, the outputs of which are connected to one number register input, the other number register inputs are connected to the drive outputs, and days of the outputs are connected to the inputs of the convolution unit modulo two to the inputs and drive. In a known device, when writing a data array using reversible counters, a control word is formed, the i-th bit of which is the sum of the number of units in the i-x bits of all the words in the array, modulo K, where n is the number of bits of the reversible counters. When writing to the j-th cell of an individual word array, the number stored there is previously read into the word register and subtracted from the control word stored in reversible counters. Then the recorded number is taken on the number register, added to the Control word and written to the drive. When reading a single word from the accumulator using a convolution block modulo. two checks for a fault in it. If there is no error, the word is output to the device. If the word is found with errors, then the entire data set is read. The addresses of the cells from which the data is read with errors are recorded. Reversible counters in this work as subtractive. If the number of failures received from the convolution block modulo two corresponds to the number of empty or missing units detected by the unit number analysis block, errors are corrected by inverting the corresponding bits 2. The disadvantages of the known device are its low reliability and low speed. The reliability of the device is low due to the fact that if there are failing bits in the storage drive where data is written that distorts the words to be written, the device’s performance is impaired. The low speed of the device is determined by the fact that when a single word is written in the memory cell, the previously written word is read beforehand, the word read is entered into the number register, and then it is subtracted from the control word stored in reversible counters. The written word is then taken to the number register and added to the control word in the reversible counters, and also written to the drive. The purpose of the invention is to increase the speed of the device. This goal is achieved by the fact that in a self-monitoring memory device containing a drive, a number register, a modulo two convolution unit, a unit analysis unit and a reversible counter unit, whose outputs are connected to the unit number analysis unit inputs, the information input device is the input of the register of the number, the first output of which is connected to the input of the accumulator, the additional register of the number, the modulo two adders block, the AND element, the first and second OR elements, the first and second blocks of this ementov OR, the AND unit, wherein the accumulator outputs are connected to one input of additional register, the other inputs of which are connected with one output of the analysis block number units, the other output of which is the first output

device, the second output of the number register is connected to the first input of the modulo two adders, the second input of which is connected to the first output of the additional number register and the first input of the AND block, the outputs of the modulo adders block two are connected to the inputs of the second OR element, the output of which is connected to the first input of the element And, the second input of which is connected to the second input of the block of elements AND, and is one control input of the device, the output of the element AND is connected to the second input of the number register and the first input of the first element nta OR, the second input of which is connected to the second output of the additional number register and is the second B.OUT of the device, the second output of the number register is connected to the first input of the second block of OR elements, the second input of which is another control input of the device, the output of the block of adders module two is connected to the first input of the first block of OR elements, the second input of which is connected to the output of the block of AND elements, the outputs of the first, second block of OR elements and the first OR element are connected respectively to; the first, second and third inputs of the reversible counter block, the third output of the additional number register is connected to the input of a convolution block modulo two, the output of which is the device output, the fourth output of the additional number register is the fourth output of the device and connected to the third input of the number register.

FIG. 1 shows a block diagram of a memory device with autonomous control; in fig. 2 - functional block diagram of the analysis of the number of units.

The device contains a register of 1 number, drive 2. additional register 3 numbers, blots 4 convolutions modulo two, block 5 modulo-two adders, block 6 AND elements, AND 7 element, first 8 and second 9 OR elements, first 10 and second AND blocks of elements OR, n - ($ reversible counter counters, combined into block 12 (the number of word digits,) and block 13 for analyzing the number of units. Register 1 has input 14, and register 3 has 15 output numbers. Additional register 3 has the output 16c of which is given the value of the marker bit of the word, block 4 CBiepTKH modulo two a - output circuit 17, and block 13. analysis of the number of units — output bus 18. The device also contains one control input 19 and another control input 20, unit 22 of the unit, command generation block 23 and output key 24. Block 13 contains multiplexer 21.

The device works as follows.

The mode of writing an array of words. In this mode, the recorded word is fed from input 14 to register I and entered into drive 2. Then the recorded word is read (recovered in drive 2) to additional register 3 - The contents of register 1 and 3 enter block 5 of the modulo two. If the word is written and read without error, the contents of these registers coincide and at the outputs of block 5

0, modulators modulo two and the element OR 9 will be the code “O. A code "1" is applied to the control input 20, which is allowed by the word from the additional register 3 through block 6 of the elements AND and the first block of 10 e.elements OR to the input of block 12.

At the same time, the code "1" is applied to all control inputs 19, in which the reversible counters of unit 12 operate as summations. The recorded word in block 13 is added to the control word.

0 If the word is written and read due to failures of the bits of the cells with errors, then at the corresponding outputs of block 5, modulo-two adders and the output of the element OR 9 there will be the code “1. The signal "1 received at input 20, at the output of the element And 7 forms a unit level, which is recorded in the marker bit of the register of the number" 1 and, acting through the element OR 8 at the input of unit 12, prohibits its operation. Marker bit

"From register 1 is written to the appropriate cell of accumulator 2, and because of this, it is excluded from operation." Then, the marker bit of register 1 is cleared in "O (the chain of magnification in Fig. 1 is not shown) and the same word is written into the next person whose operability is also checked. Other words of the array are written in the same way. Thus, after recording the array of words, all the accumulator cells are 2, the refusals in which distort the recorded words are excluded from the work, and in

 block 12, a control word is formed for

recorded array.

Record single word mode. This mode is used when it is necessary instead of a single word array.

5 write another. In this case, the previously recorded word is read from accumulator 2 to the additional register 3. From the input 14, the written word is fed to register 1. At the same time, the input "O" is input to input .20 and inputs 19. Element And 7 is closed.

0 From the output 16 of the additional register 3, the zero value of the marker bit is fed to the input of the element OR 8. Since both the inputs of the element OR 8 receive the code "O, then the output will also have a zero signal permitting the operation of the reversible counters of block 12. The contents of registers 1 and 3 are fed to the input of block 5 modulo-two adders, where the sum is formed module two. This generated word through the elements OR 10, to the other inputs of which the code "O" is transmitted, is transmitted to the information inputs of the reversible counters of block 12. At the same time, from the output of register 1, the recorded word goes to the inputs of the second block of elements OR 11 and is transmitted to the control inputs of the reversible counters of the block 12. The correction of the control word in the block 12 reversible counters is performed as follows. If in the irM bit of the written word the code is “1, then in the i-th reverse counter of the block 12, the addition of“ 1 for the code “0” is made in the i-M bit of the previously recorded word and the addition of “O for the code” 1. If the code “O” in the i-th digit of the register 1 registers, then the i-M reversible counter of block 12 subtracts “1 for code” 1 in i-M bits of the previously recorded word and subtracts “O for code“ O.

Single word reading mode. The read word from accumulator 2 is transferred to additional register 3, after which block 4 checks for the absence of errors in it. If the word is read with errors, then block 4 generates an error signal, which, in connection with input 17, is outputted from a memory device to a device that generates write and read addresses for storing the failure address (not shown). The control inputs 19 and 20 receive the code "O. In this case, the register of the number 1 is zero and the reversible counters of block 12 work as subtractive. Each word of the array from accumulator 2 is alternately read into additional register 3. Each read word when "O in the marker bit from register 3 is transmitted to the inputs of the block of adders 5 modulo two and through the first block of elements OR 10 enters the inputs of block 12, where it is subtracted from the control word. If the word "1" is read in marker position, then a single signal is output to output 16 and this cell is passed. In this case, the code “U comes from the additional register 3 to the input of the element OR 8 and also to the input of the block 12, prohibiting its operation. In the event of failures when reading words by the watchdog 4, an error signal is generated to control the memorization of the addresses of the failures. After reading the entire data array in

Block 12 generates a code containing groups of zeros in the counters corresponding to the bits of the memory device in which there are no errors or there are so many of them that are not detected by the type of control used. The number of failures is determined in block 13 of the analysis of the number of units to which the control word is transmitted from block 12.

If the number of failures received from

 modulo two convolution blocks 4, corresponds to the number of extra units detected by the unit 13 analysis of the number of units, units disappear in a given word, if the number of failures corresponds to the number of missing units, it means an accumulation of false units. In two cases, the errors are corrected by the addresses coming into the memory from the device where the addresses are memorized.

0 failures. At the same time, words with olibks are read out from accumulator 2 into additional register 3. Then, using signals from unit 13 of unit analysis, additional register 3 is corrected by inverting information in those bits where errors are detected. The corrected words from the additional register 3 are output to the output 15 of the device and, through register 1, are again recorded in the drive 2.

0 After the correction of errors, the entire array is read, and the read words go to block 12, which is preliminarily set on bus 19 to direct counting mode, where they are summed up. Thus, a control word is formed. At the same time, the reading of words is monitored using modulo two convolution block 4. If, when reading the entire array of words, no failures were detected, it means that the errors were corrected correctly and the further operation of the storage device is possible.

Thus, the proposed device, in comparison with the well-known one, allows 5 to bypass an unhealthy drive cells, in which discharge failures distort the recorded words, when recording an array of data.

figure 1

2

Claims (1)

A MEMORY DEVICE WITH AUTONOMOUS CONTROL, which contains a drive, a number register, a module of convolution modulo two, a unit for analyzing the number of units and a unit for reversible counters, the outputs of which are connected to the inputs of the unit for analyzing the number of units, the information input of the device is the first input of the number register, the first output of which is connected to the drive input, characterized in that, in order to improve the performance of the device, an additional number register, an adder block modulo two, an AND element, a first and a second element are introduced into it ORs, the first and second blocks of OR elements, the block of AND elements, the drive outputs being connected to one input of the additional number register, the other inputs of which are connected to one output of the unit number analysis unit, the other output of which is the first output of the device, the second output of the number register is connected to the first input of the adder block modulo two, the second input of which is connected to the first output of the additional number register and the first input of the block of elements And, the outputs of the adder block modulo two are connected to the inputs and the second OR element, the output of which is connected to the first input of the AND element, the second input of which is connected to the second input of the block of AND elements and is one control input of the device, the output of the AND element is connected to the second input of the number register and the first input of the first OR element, the second input of which connected to a second output of additional register and a second output device, the second number of output register connected to the first input of the second OR block elements, the second input of which is _{on the} other control input yc three, the output of the adder block modulo two is connected to the first input of the first block of OR elements, the second input of which is connected to the output of the block of AND elements, the outputs of the first, second blocks of OR elements and the first OR element are connected respectively to the first, second and third inputs of the block of reversible counters , the third output of the additional number register is connected to the input of the convolution unit modulo two, the output of which is the third output of the device, the fourth output of the additional number register is the fourth output of triplets and connected to the third input of the register numbers. ί