SU1089628A1 - Primary storage with error detection - Google Patents

Abstract

1. OPERATIONAL STORAGE, ERROR DETECTION DEVICE, containing a memory block and modulo adders two from the first to the sixth, with the first entries of the first and. The second adders in module two are connected respectively to the outputs of the third and fourth adders modulo two, the inputs of which are connected respectively to the information outputs and to the address inputs of the memory block, characterized in that, in order to expand the field of application of the device by providing the ability to transfer information in two directions, increasing the reliability of monitoring and simplifying the device; keys, logical block and element NOT are entered into it, with the first output of the logic block connected to the second inputs Two first and second adders modulo two, the third input of the first and the output of the fourth modulo adders two are connected respectively to the code and to the input of the element NOT, the first, second and third inputs of the logic unit are connected respectively to the control output and the co-managing inputs of the memory block, the fourth input of the logic unit and the control input of the memory unit are connected to the output of the second modulo adder two, fifth and sixth inputs of the logic unit are connected respectively to the output of the first modulo two adder and to the output The third and third inputs of the second modulo-two adders, the second output of the logic unit are connected to the control inputs of the keys whose inputs are connected to the information inputs of the memory unit, and the outputs are connected to the information outputs of the memory unit and are the information outputs of the device, the control inputs the memory block and the seventh input of the logic block are the control inputs of the device-, and the third and fourth outputs of the logic block are the control outputs of the device, the inputs from the eighth to the eleventh logical skip block, the fourth inputs of the first and second modulators two, the first and second inputs of the fifth and sixth modulo adders are the switching inputs of the device, the switching outputs of which are the fifth output of the logic block and the outputs of the fifth and sixth modulators two. 2. A device according to claim 1, characterized in that the logical block contains AND elements and AND-NAND elements, the first input of the first element AND being the first input of the block, the first inputs of the second and third elements AND and the first element. -NO are combined and are the second input of the block, the second inputs of the first and second elements are AND combined and are the third input of the block,

Description

the second and second inputs of the second element AND-NOT, the second input of the first element AND-NOT and the second input of the third element AND are respectively the inputs from the fourth to the seventh block, the inputs of which from the eighth to the eleventh are respectively the inputs from the first to the fourth fourth element AND , the outputs of the first, third and second elements AND, the first element AND-NOT and the fourth element AND are respectively the outputs from the first to the fifth block, the third input of the second element AND is connected to the output of the second element AND-NOT.

3. A device according to claim 2, characterized in that the logic unit comprises a third element whose Iv-code is connected to the second input of the third element And, the first input is connected to the second input of the first element And, and the second input is the seventh input of the block.

The invention relates to computing and can be used in the construction of random access memory (RAM) with control. An operational, memory with error detection containing a drive, AND or OR elements, input and output groups of AND elements, containing two AND elements per bit of a storage device, as well as blocks for the formation of write and read addresses and a comparison block. The disadvantages of the known device are the difficulties that arise due to the large number of elements I., and the absence of the possibility of detecting errors both in the address and in the information path. The closest technical solution to the invention is a random access memory with error detection, containing a accumulator, an input, an output and address registers, four blocks of rollovers modulo two and adders modulo two, counters and a subtractor, a synchronization unit whose outputs are connected to controllers. meter inputs connected to the outputs of adders modulo two, and the inputs of the first and second modulators two are connected respectively to the information outputs and to the address inputs of drive 2 . The disadvantages of the known device are the impossibility of transferring information in forward and backward control of information when transferring it from the output to the input of the formation of a check bit necessary to control information in subsequent processing stages and building additional blocks, which is necessary for modular expansion of information capacity. the number of layers and bits, which limits the scope of application of the device, the reliability of the control is low, since the control signal is generated only after tyvani all information from the storage and provided additional equipment control - required when building information capacity and complexity of the device. The purpose of the invention is to expand the field of application of the device due to the possibility of transmitting information in two directions, because of the reliability of the control and simplifying the device. The goal is achieved by the fact that the random access memory containing the memory block and the first two sixth, with the first inputs of the first and second adders modulo two connected respectively to the inputs of the third and fourth modulators two, the inputs of which are connected to respectively, to the information outputs and to the address inputs of the memory block, the keys, the logic block and the NOT element are entered, the first output of the logic block is connected to the second inputs of the first and second modulo-two adders, the third input of the first and the output of the fourth modulators-two are connected respectively to the output and to the input of the element NOT, the first second and third inputs of the logic block are connected respectively to the control output and to the control inputs of the memory block the fourth input of the logic block and the control input of the block PA They are connected to the output of the second modulo two, fifth and sixth inputs of the logic unit are connected respectively to the output of the first modulo-two adder and to the output of the third and third inputs of the second modulo-two adders; the second output of the logic unit is connected to the control inputs of the keys which are connected to the information inputs of the memory block, and the outputs are connected to the information outputs of the memory block and are the information outputs of the device that control the inputs of the memory block and the seventh input of the logic block These are the control inputs of the device, and the third and fourth outputs of the logic block are the control outputs of the device, the inputs from the eighth to the eleventh logical block, the fourth inputs of the first and second modulo two, the first and second inputs of the fifth and sixth adders by Module two are the switching inputs of the device, the switching outputs of which are the fifth output of the logic block and the outputs of the fifth and sixth modulo-two adders. The logical block contains the AND elements and the NAND elements, with the first input of the first AND element being the first input of the block, the first inputs of the second and third AND elements and the first AND AND element are combined and are the second input of the block, the second inputs of the first and The second AND elements are combined and are the third input of the block, the first and second inputs are the second IS-NOT element, the second input of the first IS-NOT element and the second input of the third AND element are respectively inputs from the fourth to the seventh block, whose inputs are from the eighth to the next the eleventh are respectively, the inputs from the first to the fourth fourth And elements, the outputs of the first, third and second And elements, the first NAND element and the fourth And element are respectively the outputs from the first to fifth block, the third input of the second And element is connected to the output of the second element INE The logical block contains the third NAND element, the output of which is connected to the second input of the third And element, the first input is connected to the second input of the first And element, and the second input is the seventh input of the block. FIG. 1 shows a functional diagram of the proposed device / in FIG. 2 is a functional diagram of the WTO embodiment of the logic unit. The device contains (FIG. 1) a memory block 1 with information outputs 2t) (where P is an integer) and a control input 3, a logic block 4. FIG. 1 designates control inputs 5-7 from first to third, control outputs 8, 9 of the device, element NE 10, switching inputs 11-20, outputs 21-23 of the switching device, control output 24 of the memory block, information 25 and address 26 inputs and information outputs 27 devices. The device also contains adders 28-33 modulo two from the first to the sixth. The logical block contains (see Fig. 1) nepBbDi 34 and the second 35 elements AND, the first element AND-NOT 36, the third 37 and fourth 38 elements And the second element AND-NOT 39. The device also contains the keys 40 (-40g). In the second embodiment, the logic unit also contains (see Fig. 2) the third element IS-NE 41. The device operates as follows. In the case when there is no need to increase the information capacity of the device, adders 32 and 33 (see Fig. 1) are used to invert and form a key management signal together with element 38, and to provide the necessary polarity of the signals at the outputs of adders 28 and 29 in the modes of recording and combining, an adder 33 is used. Accordingly, inputs 5 and 7 must be connected respectively to outputs 21 and 22, inputs 19 and 20 to outputs 21 and 22, output 23 to input 13, to inputs 17 and 18 send a signal o, to the inputs 11, 15 - signal recording / reading, the inputs 14 and 16 - a level 1 (corresponding to the communication are attached while in Figure 1 in phantom.). In the mode of direct reception and output of information (inputs 25 serve as inputs, outputs 27 as outputs, when writing to block 1, inputs 17, 18 and 11, 15 give the signals Premo / back and Write / read respectively in the form of levels 1. Pass through adder 3 level 1 will set input 5 to a low level that allows the information code to be written to block 1, and, through the adder 33, AND 38 and adder 32 will set a high level on the second input of the NAND element 3 Address code bits, coming from the inputs 26 to the inputs of block 1 and the inputs of the adder 31, are summed modulo two. This sum is fed to the first input of the adder 2 at the second input which is signal level O determined by a low signal at input 5, creating a low level at the output of the AND 34 element. When a high level is applied to input 6, the module at the control inputs of keys 40 (- 40 |, a level 1 determined by the signal from the output of element 37 and allowing the information code from inputs 25 to outputs 2 and the inputs of adder 30 to pass through the keys 40, -40c, the outputs of the block do not affect the levels of the signals at outputs 27 since the write mode is off condition. The adder 30 sums modulo two bits of the information code that have passed through the keys and the result of the sum goes to the third input of the adder 29, at the fourth input of which is the level 1 of the signal from the input 11. Thus, the output of the adder 29 produces the signal of the inverted sum modulo two information and address bits supplied to the control input of block 1 and memorized together with the information code in block 1. At output 8 in recording mode, the level O, corresponding to the sign of proper operation of the device and determine the level It is at the second input of the element I 35. When reading information, the signal Write / read has the level O and closes the keys 40u-40, will form the level O at its control input through the circuit: adder 33 - element 38 and adder 32 - element I 37. At the input 5 level 1, allowing reading from block 1 and passing the signal through the element And 34 to the second inputs of adders 28 and 29. Information code. counted from block 2 of block 1 when applying level 1 to input 6 and an address code to inputs 26, arrives at outputs 27 and inputs of the adder 30, adder 30 generates a modulo-sum signal of two bits of the information code, coming from the output of the adder 30 to the second input element AND-NOT 36, passing through which is allowed by a high level at input 6. Thus, at output 9, the sum of the modulo two bits of the information code is formed, i.e. the check bit of information contained in block 1. From the output of the adder 30, the signal also goes to the first input of the adder 28 and the third input of the adder 29, the second inputs of which receive the signal of the inverted amount modulo two bits of the address and information codes generated and stored in recording mode. The first input of the adder 29 comes from the output of the adder 31, the signal modulo two bits of the address code, to the third input of the adder 28 through the element NOT 10 - the inverse of the sum. At the fourth inputs of adders 28 and 29, levels 1 and O, respectively, coming from inputs 12 and 11. Thus, at the inputs of adder 28 there are signals: sums modulo two bits of the information code; inverse sum modulo two bits of address codes and information; inverse sum of address code bits; Level 1. At the inputs of the adder 29 there are signals: the sum modulo two bits of the address code, the inverse sum modulo two bits of the address code and information, the sum modulo two bits of the information code j level O. Consequently, when the read information matches and the address code to the sum of the address and information bits formed in the recording mode, the outputs of the adders 28 and 29 and the inputs of the AND-NOT element 39 are set to level 1, the third input of the element 35 and the control during the 8 is level O. no match (the presence of an error Odd multiplicity in the information code or address) On one or both of the outputs of the adders 28 and 29, the level O will be formed, and the output 8 will set the level 1 sign of malfunction. The presence of adders 28 and 29 in the control circuit makes it possible to increase the reliability of the control, since if there is an error in the address or information path and a malfunction of one of the adders 28, 29 leading to the masking of this error, the error will be the output of the second of the adders 28 and 29 In the mode of reverse reception and transmission of information (outputs 27 serve as inputs, and inputs 25 as outputs) the Forward / Back signal sent to input 17 and 18 has an O level, which sets a high level on the second the input element And 37 (through the element And 38 and mmator 32). In the recording mode (the Record / match signal at inputs 4 11 and 15 is level 1), when high-level ur is applied to input 6 at the control inputs of keys 40, -40, a high ypoBeHb is set, which opens the keys through which from outputs 27 to inputs 25 of block 1, information code bits are received. At the same time, the adder 29 forms, using the summers 30 and 31, the signal of the inverse sum modulo two bits of the address and information codes sent to input 3 and remembered in block 1 (the sum modulo two bits of the code addresses, at the second level O, determined by the presence of O at the second input of the element I 34, at the third input - the sum modulo two information bits, at the fourth input - level 1 from input 11, therefore, at the output of the matrix 29 - inversion amounts modulo two bits of address codes and information ation). In the read mode (the Write / read signal at inputs 11, 15 has a level O) when the address code is fed to inputs 26 and the sample enable signal to input 6, the information code counted from outputs 2 of block 1 is supplied through public keys 40-40fj to inputs 25 and the inputs of the adder 30. The adders 30 and 31 form the sums modulo two information and address bits arriving at the first and third inputs of the adders 28 and 29, and the sum of the address bits arrives with inversion at the third input of the adder 28. At the second inputs of the adders 28 and 29, the output of the output 24 through the element 34 is the signal of the inverse sum of the bits of the address codes and information generated in the recording mode. The fourth inputs of adders 29 and 28 receive levels O and 1, respectively, from inputs 11 and 12. Thus, the outputs of adders 29 and 28 and the inputs of the IS-NOT element 39 correspond to the read information and its address code to the sum modulo two signal in recording mode, levels 1 are set, and level O is set at the third input of element 35 and output 8 - a sign of proper operation. In case of error, odd multiplicity, in the address code or information at the outputs of one or both of adders 28 and 29, level O occurs, at the third input of the element And 35 level 1 and, since the first and second inputs of the element 35 also contain levels 1 , determined by the presence of a high level at inputs 5 and 6, then at the output of the element 35 and output 8 there will be a level 1 sign of malfunctioning. When increasing the information capacity of the device according to the element AND 38 and adders 32 and 33 are used to build and control the decoder additional address bits, therefore, to generate a key management signal in block 4, an IS-NE element 41 is added that performs the same function as implemented with the above described: e device operation element 38 and adder 32. Thus, the expansion of the scope, simplification, increase

efficiency and reliability of control is achieved due to the fact that the formation and storage of the check bits of the address codes and information is performed using the disabled state of the outputs, block 1 in the recording mode on the same I equipment on which the output of the device is generated and bidirectional transfer and storage of information, and with an increase in the information capacity, the control equipment is expanded without additional hardware costs.

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Claims (3)

1. OPERATIONAL MEMORIAL. ERROR DETECTING DEVICE, containing a memory block and adders modulo two from the first to the sixth, and the first inputs of the first and. the second adders modulo two are connected respectively to the outputs of the third and fourth adders modulo two, the inputs of which are connected respectively to the information outputs and address inputs of the memory unit, characterized in that, in order to expand the scope of the device by providing the possibility of transmitting information to in two directions, increasing the reliability of control and simplifying the device, keys, a logic block and an element NOT are entered into it, the first output of the logical block being connected to the second inputs of the second and second adders modulo two, the third input of the first and second fourth adders modulo two are connected respectively to the input and input of the element NOT, the first, second and third inputs of the logic unit are connected respectively to the control input and co-control inputs of the memory unit, the fourth input of the logical of the block and the control input of the memory block are connected to the second adder modulo two, the fifth and sixth inputs of the logic block are connected respectively to the first adder modulo two and to the third ad the third input of the second adders is modulo two, the second input of the logic unit is connected to the control inputs of the keys, the inputs of which are connected to the information inputs of the memory unit, and the outputs are connected to the information inputs of the memory unit and are information inputs of the device, the control inputs of the memory unit and * seventh input the logical block are the control inputs of the device ·, and the third and fourth outputs of the logical block are the control inputs of the device, the inputs from the eighth to eleventh logical blocks, four The grounded inputs of the first and second adders modulo two, the first and second inputs of the fifth and sixth adders modulo two are the switching inputs of the device, the switching codes of which are the fifth logic module and the outputs of the fifth and sixth adders modulo two. 2. The device according to claim 1, characterized in that the logical unit contains AND elements and AND elements, and the first input of the first element AND is the first input of the block, the first inputs of the second and third elements AND and the first element, which are NOT combined and are the second input of the block, the second inputs of the first and second elements AND are combined and are the third input of the block, 30 ζβ The southern and second inputs of the second AND-NOT element, the second input of the first AND-NOT element and the second input of the third AND element are respectively the inputs from the fourth to seventh block, whose inputs from the eighth to eleventh are respectively the inputs from the first to fourth fourth elements of AND, the outputs of the first, third and second AND elements, the first AND element and the fourth AND element are respectively the outputs from the first to fifth block, the third input of the second AND element is connected to the output of the second AND element. 3. The device according to claim 2, characterized in that the logic unit contains a third AND-NOT element whose output is connected to the second input of the third AND element, the first input is connected to the second input of the first AND element, and the second input is the seventh input of the block.