SU1372363A1 - Redundant read-only memory - Google Patents

Abstract

The invention of othiosigs to the hygienic technique, in part to the semiconductor lapomi) 1a1o: yc i juM iCT- you. The purpose of the invention is half a year; reliability of zapomzgayuidego ycTpoiicTita. Iostappstil Dal achieves by the fact that it is set to 1, 1, and the gio contains the source of the coytr of the LYPPs) a.ijieca 24, the control of the 2 i, Olok pam. ty kontro. g 25, blok ppch ti aripera 3ahtcine-ip 26, caneivTop, dash.k 14,15, scheme sraviiii 1). co-play; Istr Dunshlkh 17, Fortptt Opatol T Remeno International 19, Tpitrrep Control 20,; v c; Meirr il. j ipcTnii O.ioic sum1- (ator no mod. by juia 1 1 with the corresponding chassis. Listed number of characters has increased the likelihood oeirapVA QinD of the code of the failed YAH.SYKEY memory 1, 2 failed. on the cell from the backup drive 3. As a result, the reliability of the entire storage device operation is 2 silt, 1 tab.

Description

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The invention relates to a computing technique, in particular, to semiconductor memory devices.

The purpose of the invention is to increase the reliability of the memory.

Pa figs. 1 shows the scheme of memory with redundancy; in fig. 2 shows an example of the execution of the control control unit.

The memory contains 1, 2 and 3 backup drives, the first 4, second 5 and third 6 address switches, first 7, second 8 and third 9 data registers, first 10, second 11, third 12 modulo adders two, switch 13, nepBbDi 14 and 15 second data selectors, control block 16, control register 17, comparison circuit 18, time interval generator 19, trigger 20 control, AND 21 element, address register 22, reservation control block 23, control address register 24 block 25 control memory, substitution address memory block 26 and counter 2 7 control address.

The device has an address input 28, 30 steps from the storage unit 25 and from

information outputs 29 and 30, synchronization input 31 and control output 32

The redundancy control unit 23 has an input 33 and 34 and an output 32, 35-37 and contains a comparison circuit 38, an element HJIli-HE 39, a decoder 40 for control signals, a switch 41 for control signals, elements And 42 and 43, a time generator 44. and element I-UIH 45.

The switches 4-6 addresses, data selectors 14 and 15, the switch 13 data switchboard 41 of the control signals can be made on the basis of controlled multiplexers of the K155 series.

The control unit 16 can be implemented as a set of control circuits, implemented 1x: one of the known methods for detecting failures and output registers into which the result of monitoring all drives is entered in each call cycle.

The decoder 40 control signals can be performed, for example, on

the base of the usual decoder 3 - 8 and two track elements AND-NOT.

The output of the decoder 3-8, corresponding to code combination III at its input, is the third you

the course of the decoder 40 signal failure and is connected to one of the inputs of the element OR 45.

The device operates in three modes: the read mode in the absence of drive failures, the self-check mode of the failed drive, and the replacement mode of the failed drive cells.

The initial state of all the cells of the RAM 25 and 26 and the control trigger 20 corresponds to a zero logic level and is set by a signal (not shown) of the initial setup.

The operation modes of the device are controlled by the backup control unit 23 depending on the ratio of the code combinations received at its inputs 33 and 34, respectively, from the control memory unit 25 and the control unit 16. Possible code combinations for the inputs 33 and 34 of block 23 and the modes of operation of the device implemented in this case are shown in the table.

In the absence of failures in the accumulators to the inputs 33 and 34 of block 23 to 5

0

five

0

five

block 16 controls the initial zero combinations of a three-bit code. The zero code combination, coming from the input 33 to the input of the element OR NOT 39, sets at its output a signal of a single logic level. This signal switches the control switch 41 to receive signals from input 34 from control unit 16, and also permits the passage of signals from the decoder 40 of the failure signals through elements 42 and 43. The zero code combination from the output of control switch 4l is fed to the sampling inputs of switches 4- 6 addresses, switching them to receive signals from the address register 22. Null code combination at the output of the circuit

38 comparisons, indicating that the code combinations at the inputs 33 and 34 of the redundancy control unit 23 coincide, are input to the sample of the data switch 13, setting it to receive and receive information on the information outputs 29 and 30 of the device, information of the first 1 and second 2 working drives from the outputs of the first 7 and second 8 data registers.

The zero logic signal from the output of the control trigger 20 allows writing the current address to the control address register 24, writing the control signals to the output registers of the control unit 16, keeps the control address counter 27 (locks), and prevents the input of the device sync input 31 from passing through element and 21.

When a failure occurs in one of the drives from the output of the control unit 16 to the input 34 of the redundancy control unit, a code combination arrives that carries information about the failed drive (item 2, table 1).

The code combination, coming through the control switch 41 to the sampling inputs of the address switches 4-6, switches the one that corresponds to the failed drive to receive signals from the check address counter 27.

The code combination from the output of the comparison circuit 38, obtained as a result of a bitwise comparison of the code combinations at the inputs 33 and 34 (in this case, it repeats the code at the input 34), is fed to the input of the data switch sample 13, setting it to receive and issue the outputs 29 and 30 of the device calculated using blocks adders 10 and 11 of the true information of the failed drive.

The code combination of the control unit 16 from the input 34 of the reservation control unit 23 is supplied to the input of the failure signal decider 40. The signal of a single logic level from the first output of the decoder 40 through the allowed element And 43 is fed to the input of the imaging unit 44 of the time interval.

If two or three drives fail at the same time, the signal of a single logic level comes from the second output of the decoder 40 through the permitted element AND 42 to the first input of the OR 45 element and the third output of the decoder 40 to the second input of the OR element 45. The signal from the output of the OR 45 element goes to the monitored output 32 of the device, certificate of device failure.

The output signal from the imager 44 time interval trigger 20

0

five

0

five

0

five

0

five

the control is set to one and the true register of the failed drive is recorded in the control register 17, which is fed through the control signals of the control unit 16, the first data selector 14 from the outputs of the data switch 13 when the working drives 1 and 2 fail or from the third modulo block two 12 in case of failure of the backup drive 3.

The signal of a single logic level from the output of the trigger 20 control blocks the recording of the current address in the control address register 24 and the recording of the control signals of the failed drive in the output register of the control unit 16, and also allows the control address counter 27 to work and the signals to the input from the device synchronization input 31 through the element and 21.

The device goes into self-monitoring mode of the failed drive, while the delivery of true information to the consumer upon a command to access the device is not suspended.

The self-monitoring mode of the failed accumulator consists in successively traversing the array of the address of this accumulator in search of information identical to the true information of the failed cell.

The true information of the failed cell is stored in the control register 17 and comes from its output to one of the inputs of the comparison circuit 18, to the second input of which the second data selector 15 provides information of the failed storage drive through the signals controlled by the control unit 16. - l.

Upon reaching the address of the cell, the information of which is identical to the true information of the failed cell, the comparison circuit 18 generates a signal arriving at the input of the time interval 19.

A signal from the output of the time interval imager 19 records in blocks 25 and 26 at the address of the failed cell, respectively, the code combination of signals of the control unit 16 and the replacement cell address from the output of the control address counter 27, and the trigger 20 is also set to the initial zero state.

The device enters the replacement mode of the failed drive cell.

In the substitution mode, code combinations are received at the inputs 33 and 34 of the reservation control unit 23 in accordance with p. 3 of the table. 1. At the same time, the output of the OR-NOT 39 element is set to a signal of zero logic level, which forbid the AND 42 and 43 elements, and the control switch 41 switches to receive

signals from input 33 from block 25 by the input of the first block of adders on

mt control

The code combination of the monitoring memory unit 25 from the output of the control switch 41 is fed to the inputs of a selection of the address switches 4-6, switching the one that corresponds to the failed drive to receive signals from the replacement address memory block 26.

The zero combination at the output of comparison circuit 38 configures the output number switch in a manner similar to the read mode in the absence of drive failures.

In the event of a failure at the address in two accumulators (item 4, tab. 1), the device performs the replacement of the failed cell in the first accumulator in accordance with the described operation logic and parry the malfunction in the second accumulator. Parrying is performed on the signals of control circuit 38, the code combination at the output of which carries information about the second failed drive. This code combination is fed to the input of a sample of NryTaTopa 13 data, tuning it to the information inputs 29 and 30 of the true information device computed by the first 10 and second 11 blocks of modulo-two adders.

Claims (1)

Invention Formula Permanent redundant storage device containing three accumulators, three data registers, three address switches, two modulo adders, a data switch, a control block, a control address counter, an address register whose input is an input input 13723636 House device, and the output is connected to the first address inputs of the address switches, the control address inputs of which are connected to the output of the control address counter, and the outputs to the inputs of the first, second and third accumulators, respectively, the outputs of which are connected respectively to the inputs of the first, second and third data registers, the output of the first data register is connected to the first information inputs of the data switch and control unit and with the first 0 0 five five 0 five 0 five module two, the output of which is connected to the second information inputs of the data switch and control unit, the third information;:; the input input of which is connected to the output of the third data register, the second input of the first block of modulo-two adders and the first input of the second block of the modulo-two, second the input of which is connected to the output of the second data register, the third information input of the data switch, the fourth information input of the control unit, the five information input of which is connected to the output of the second block of summation modulo two and the fourth information input of the data switch, the first and second outputs of which are information outputs of the device, characterized in that, in order to increase the reliability of the device, it contains a control address register, a redundancy control block, a control memory block , substitute address memory block, two data selectors, comparison circuit, control data register, time interval generator, control trigger, AND element, third unit of modulators two, ne the left and second inputs of which are connected to the first and second outputs of the data switch, respectively, and the first and second information inputs of the first data selector respectively, the third information input of which is connected to the output of the third unit of the modulo two, the output is connected to the information input of the control data register, and the sample input of the first data selector is connected to the output of the control unit, the first information input of the redundancy control unit, with the information input of the operating memory block and the control and the sample input of the second data selector, three information inputs of which are connected to the outputs of the first, second and third data registers, respectively, and the output is connected to the first information input of the comparison circuit, the output of which is connected to the input of the time interval generator, and the second information input - with the output of the control data register, the sampling input of which is connected to the installation output of the redundancy control unit, the installation input of the control trigger, the reset input of which is connected to the output ormirovatel time interval and sampling the inputs of the operational blocks of memory control and address substitution, the control trigger output connected to a first input of AND gate, to the inputs of a counter control sample address control unit and the pin 000 001 010 100 001 010 100 No failures Failure of the 1st main drive Failure of the 2nd main drive Backup drive failure Failure of the 1st primary storage device Failure of the 2nd primary storage device Failure of the backup storage device 001 101 011 Replacement failed. checks and parry Failure of the 1st main and backup drives Failure of the 1st and 2nd main drives at the same address 110 Failure of the 2nd main and backup drives 0 five 0 five the address register, the information input of which is connected to the address register input, and the output is connected to the information input of the RAM memory block of the replacement address and the address input of the RAM memory control block, the output of which is connected to the second information input of the redundancy control block; is the control output of the device, the comparison output is connected to the sample input of the data switch, and the information output is connected to the input switches of the address switches, the second address the inputs of which are connected to the outputs of the memory block of the replacement address, the address input of which is connected to the output of the control address counter, the counting input of which is connected to the output of the And element, the second input of which goes to the synchronization input of the device. Reading in the absence of drive failures Failed self control accumulator Substitution refused cells Replacement failed. checks and parry  matching at failure of two drives 00 011 101 110 Failure of the 1st and 2nd main drives Failure of the 1st soft and backup drives Failure of the 2nd main and backup drives FIG. 2 Table continuation