SU1129658A1 - Redundant storage - Google Patents

Abstract

1. A BACK-UP STORAGE DEVICE containing an address register, one of the outputs of which is connected to the inputs of the first and second working and backup memory blocks, the first and second switches, whose information inputs are connected to the outputs of the corresponding working memory blocks, and the control inputs from another output of the address register, the first adder, one of the inputs of which is connected to the outputs of the backup memory block, characterized in that, in order to increase the reliability of the device. A second backup block of memory, the first and second code converters, the third switch, the second and third adders, and the information selection block, the outputs of which are outputs of the device, are entered into it, and the inputs are connected respectively to the outputs of the first switch, the first, second and third adders, The other inputs of the first adder are connected to the outputs of the first code converter, the inputs of which are connected to the outputs of the second switch and one of the inputs of the second adder, the other inputs of which are connected to the outputs of the third the switch and one of the inputs of the third adder, the other inputs of which are connected to the outputs of the first backup memory block, the inputs of which are connected to the inputs of the second backup memory block, the outputs of which (L are connected to one of the inputs of the third switch and the inputs of the second converter code, the outputs of which connected to other inputs of the third switch, the control input of which is connected to another output of the address register.

Description

2. The device according to claim 1, characterized in that the information sampling unit comprises first to third comparison blocks, an OR element and a fourth switch, the outputs of which are outputs of the block, one of the information inputs connected to the first inputs of the comparison blocks, the second inputs

which are one of the inputs of the block, and the outputs are connected to the inputs of the OR element, the output of which is connected to the control input of the fourth switch, the other information inputs of which and the second input of the first comparison unit are the other input of the block.

The invention relates to computing and can be used in the construction of storage devices of highly reliable computing systems.

A reserved self-monitoring memory device is known, containing duplicate memory blocks, address and number registers, hardware modular control units, switches, and a control unit. In the device, the accuracy of the output information is ensured by using modular instrumentation blocks and switching to a backup memory unit when fault 1 is detected.

A disadvantage of the known device is the low reliability of the output information due to the low efficiency of malfunction detection by hardware control modulo.

The closest technical solution to the invention is a redundant storage device containing an address register, one of the bits of which serves to enter a sign of access to the first or second working memory blocks, the backup memory block, which contains a modulo two information with the same addresses from working memory blocks, the first and second switches, whose information inputs are connected to the outputs of working memory blocks, and the control inputs to the output of one of the address register bits, modulo ntrol, one-by-one adder, third switch, clock generator, comparison circuit, group of I 2 elements.

The disadvantage of this device should include the delivery of unreliable information to the consumer in the event of a malfunction of one of the working memory blocks (in case of failure of the module control unit hardware), which reduces the reliability of the device.

The purpose of the invention is to increase the reliability of the device by increasing the reliability of the information output.

The goal is achieved by the fact that in a backup memory device containing an address register, one of the outputs of which is connected to the inputs of the first and second working and backup memory blocks, the first and second switches, 5 information inputs of which are connected to the outputs of the corresponding working memory blocks, and the control inputs with another output of the address register, the first adder, one of the inputs of which is connected to the outputs of the backup memory block, the second backup memory block, the first and second converters are entered whether the codes, the third switch, the second and third adders, and the information sampling unit whose outputs are the device outputs and the inputs are connected respectively to the outputs of the first switch, the first, second and third adders, the other inputs of the first adder are connected to the outputs of the first code converter, the inputs of which are connected to the outputs of the second switch and one of the inputs of the second adder, the other inputs of which are connected to the outputs of the third switch and one of the inputs of the third adder, the other inputs of which are soy dinene with the outputs of the first backup

a memory unit whose inputs are connected to the inputs of the second backup memory unit, the outputs of which are connected to one of the inputs of the third switch and the inputs of the second code converter, the outputs of which are connected to other inputs of the third switch, the control input of which is connected to another output of the address register.

The information sample block contains the first to third comparison blocks, the OR element and the fourth switch, the outputs of which are the outputs of the block, one of the information inputs connected to the first inputs of the comparison blocks, the second inputs of which are one of the inputs of the block, and the outputs connected to the inputs the OR element, the output of which is connected to the control input of the fourth switch, the other information inputs of which and the second input of the first comparison unit are the other input of the unit.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 is the same block selection of information. The device (Fig. 1) contains the address register 1, one of bits 2 of which serves to enter a sign of access to the first 3 or second 4 working memory blocks, the first backup memory block 5, which contains information, is equal to the sum of the codes containing in the same cells of the first 3 and second 4 working memory blocks, the second backup memory block 6, which contains information, is equal to the difference of codes contained in the same cells of the first 3 and second 4 working memory blocks, first switch 7, first converter 8 codes, the second the switch 9, the third switch 10, the second converter 11 codes, the first 12, the second 13 and the third 14 adders, block 15 sample information, having inputs 16-19.

Information block 15 (Fig. 2) contains the first 20, second 21 and third 22 comparison blocks, fourth switch 23, element OR 24.

The operation of the device is as follows.

The address of the cell to which it is necessary to address is written into register 1, in one of bits 2 of which the indication of access to the first 3 or second 4 working memory blocks is entered.

If a call is made to the first working memory block 3, the information read from it (for example, a) through the first switch 7 is fed to the input 16 of the information sampling unit 15.

At the same time, one input of the first adder 12 through the second switch 9 and the first converter of 8 codes will receive the return information code (e.g., c) contained in the second work unit 4 of the memory, and the input of this adder will receive information from the first backup unit 5 is equal to the sum of the information codes of the first and second working memory blocks (ACh). The second input of the second adder 13 through the second switch 9 will receive information from the second working memory block 4, and another input of the second adder 13 through the third switch 10 will receive information from the second backup memory block 6, equal to the difference of the codes of the same cells of the first 3 and second 4 working memory blocks (a-in). Information from the outputs of the first backup memory block 5 (a + b) will be sent to one input of the third adder 14, and information from the outputs of the second backup memory block 6 (a-b) will go to another input of the third adder 14 via the third switch 10. In this case, the input 17 of the block 15 sample information from the outputs of the first adder 12 will receive information equal to: (a + b) -in. At the entrance

18 block 15 of the sample information from the outputs of the second adder 13 will receive information equal to: 8 + (a-b) a. At the outputs of the third adder 14, 5 information will be generated, equal to: (o + b) + (a-b) 2a. To the input 19 of the information sampling unit 15 from the outputs of the third adder 14, information of the second and subsequent bits is supplied, i.e. the result of the summation divided by 2 and equal to a.

So, for example, if: a 0101; , then a-t-8,01101 (most significant sign); a-8 00101 + 1000 11100 (term in and result of addition in the reverse code). In this case, the outputs of the first adder

5 12 a code will be formed (a + b) -v 01101 + 10111 00101 (taking into account the transfer from the sign bit); at the outputs of the second adder 13 - the code in + (ab) 01000 + 11100 00101 (including the transfer from the sign bit); at the outputs of the third adder 140 code: (a + 8) + (ae) 0jl01 + 11100 01010 (taking into account the transfer from the sign bit). The input 16 of the information sampling unit 15 from the outputs of the first switch 7 receives the code 0101. All the bits of the result are added to the input 17 and 18 of the unit 15 with the outputs of the corresponding adders 12 and 13, with the exception of the most significant (digit) bit, i.e. code 0101. To input 19 of block 15, from the outputs of the third adder 14, all bits of information are supplied, for

0 with the exception of the youngest bit, i.e. code 0101.

Thus, the inputs of the comparison units 20, 21 and 22 and the inputs of the switch 23, in the absence of faults in the working 3, 4 to the reserve 5, 6 memory blocks, receive the same information, equal to the information of the selected (in this case, the first 3) working memory block ti. In the case of comparing the information arriving at block 15 via input 16 with information arriving via any of the other inputs (17, 18, and 19), it is considered reliable and is outputted through the switch 23 via the control signal from the output of the OR element 24 to the output devices.

In the case of incomparability of information, coming on the input 16 of the block 15, with information arriving on other inputs, from the output of the OR element 24, the control input of the switch 23 receives a signal that switches the switch 23.

0 In this case, instead of the faulty information from the inputs 16, information from the inputs 17 of the information retrieval unit 15, i.e., the recovered information, will be sent to the device outputs.

five . If a call is made to the second working memory block 4, the switches 7, 9, 10 are switched and through the switch 7 to the input 16 of the sample block 15

information will be received information, the second working unit 4 of memory (equal to 1000, by analogy with the considered example).

At the input 17 of the block 15 sample information through the first adder 12 will receive information equal to (a-fe). The inputs 18 and 19 of block 15, respectively, come from the outputs of the second 13 and third 14 adders information is equal to a- (a-b) 1000 and (a + b) - (a-b) -1/2 1000. Otherwise, the device does not differ from that described.

Thus, the application of the invention ensures the issuance of highly reliable information in the event of a fault, one of the memory blocks (or if all

memory blocks, if the addresses of the failed cells do not match). High accuracy of the information is provided by monitoring information from the working memory blocks and switching to the reserve

the result of a one-by-one comparison of the read information, and not the result of an inefficient instrumental control modulo (as in the prototype).

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Claims (2)

1. A RESERVED MEMORY DEVICE containing an address register, one of the outputs of which is connected to the inputs of the first and second working and backup memory blocks, the first and second switches, the information inputs of which are connected to the outputs of the corresponding working memory blocks, and the control inputs are connected to the other output of the register addresses, the first adder, one of the inputs of which are connected to the outputs of the backup memory unit, characterized in that, in order to increase the reliability of the device, a second backup memory unit, first the first and second code converters, the third switch, the second and third adders and the information sampling unit, the outputs of which are the outputs of the device, and the inputs are connected respectively to the outputs of the first switch, the first, second and third adders, the other inputs of the first adder are connected to the outputs of the first code converter the inputs of which are connected to the outputs of the second switch and one of the inputs of the second adder, the other inputs of which are connected to the outputs of the third switch and one of the inputs of the third adder, its inputs are connected to the outputs of the first backup memory block, the inputs of which are connected to the inputs of the second S backup memory block, the outputs of which are connected to one of the inputs of the third switch C and the inputs of the second code converter, the outputs of which are connected to the other V inputs of the third a switch whose control input is connected to the other output of the address register. 2. The device according to π. 1, characterized in that the information sampling unit contains first to third comparison blocks, an OR element and a fourth switch, the outputs of which are the block outputs, one of the information inputs is connected to the first inputs of the comparison blocks, the second inputs of which are one of the block inputs, and the outputs are connected to the inputs of the OR element, the output of which is connected to the control input of the fourth switch, the other information inputs of which and the second input of the first comparison block are another input of the block.