SU1462424A1 - Device with self-check for delaying digital information - Google Patents

Abstract

The invention relates to computing and can be used in digital information delay devices. The aim of the invention is to improve the reliability of the device. Increased reliability is achieved by storing information in each cell of a storage device with the maximum possible accuracy for it, regardless of the state of the remaining storage cells. At the same time, the higher bits of the information word for each address are stored in the cell 6 or 7, which is determined by the efficiency of the cell of the corresponding accumulator. A sign indicating the position of the highest part of the word for each cell of the accumulators 6 and 7 is stored in the accumulator 8. 1 Il. G S

Description

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The invention relates to computing and can be used in digital information delay devices.

The aim of the invention is to increase the reliability of the device, which consists in the fact that each cell on the colitiser stores its information with the maximum possible accuracy for the cell, independent of the state of the remaining cells in the storage device.

The drawing shows a block diagram of the device.

The device contains pefvy 1 and second 2 convolution blocks, input switch 3, element OR 4 counter 5 addresses 5 first - third 6-8 drives, output register 9, D-flip-flop 10 / third convolution block 11, first comparison block 12, the fourth convolution block 13, the second block. 14 comparisons, output switch 15, synchronization input 16, information inputs of higher 17 and lower 18 bits, information outputs 19 and outputs 20 of the high bit error signal, information outputs 21 and output 22 of the low bit error signal.

The device works as follows.

The information inputs 17 and 18 of the device receive a sequence of information layers E1, followed by sync pulses at the input 16 of the device synchronization, during which the first half of the clock reads information from the storage cell recorded to the clock back, and during the second half writes information to the same cell, which , in turn, will be read through K cycles. The magnitude of the delay K is determined by the conversion factor of the counter 5, which, under the influence of the clock pulses, sequentially iterates over the addresses of the accumulators 6–8.

The high and low bits are written to the accumulators 6 and 7 together with the corresponding control bits, which are calculated by the first 1 and second 2 convolution blocks as a sum modulo p. The information read from the accumulators together with the control bits is written to the output register 9.

The third 11 and fourth 13 convolution blocks, together with the first 12 and second, 14 comparison blocks, produce

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error signals in the senior and junior half-words.

In the absence of failures in accumulators x 6 and 7, input 3 and output 15 switches transfer information to their outputs without re-switching, i, e. the higher bits are pushed into accumulator 6, the lower ones - into accumulator 7. After a delay, the higher bits go to exit 19, the younger ones to exit 21.

In the event of a failure of a certain cell of the accumulator 6, in which the most significant bits are stored, the output of the first comparison unit 12 is a signal 1, indicating a failure. This signal will be recorded, in the next half-cycle of writing to the third, one-bit, drive 8. At the same time, the bits of the input information word will be written to the drives 6 and 7 at the same address. The appearance of the control input of the input switch 3 of signal 1 will cause switching of switch 3. As a result, the higher bits of the word will be written into the cell of the second accumulator 7, and the low bits - into the cell of the first accumulator 6, where a fault was detected at the same address in the previous half-cycle of reading.

Thus, each cell of the accumulator 6 is assigned to a single-bit storage unit 8 with the same address where the operability of the corresponding storage unit 6 is stored. If the storage location of the storage unit 8 is zero, then the corresponding storage location of the storage unit 6 is healthy and it will store the highest bits. If a unit is stored in cell 8 of the accumulator 8, then a malfunction exists in the corresponding cell of the accumulator 6 and the lower bits will be entered into it, while the higher bits will be recorded in the corresponding serviceable cell of the accumulator 7,

In this case, when reading into D-flip-flop 10 from accumulator 8, the unit that will control the switching of the output switch will be read to restore the correct location of the low and high bits. In addition, this signal, via the OR 4 element, will control the writing of the next word in this

the same cell of the drives 6 and 7 in the rewired form, i.e. instead of the higher bits, the lower bits will be re-recorded in drive 6. Switches 3 and 15 commute the information together with the corresponding test bits.

Thus, by introducing into the delay device digital information an additional accumulator of the OR element and a D-flip-flop, the device saves the higher bits of information in the event of a failure, which leads to an increase in the reliability of the device.

Claims (1)

Invention Formula N Device for delaying digital information with control, containing four convolution blocks, input and output switches, address counter, first and second drives, output register, two comparison blocks, with the count input of the address counter connected to the write / read control inputs of the first and second drives , the output enable input of the output register and is the device synchronization input, the output of the address counter is connected to the address inputs of the first and second drives, the information and control inputs of the first and the second accumulators are connected to the corresponding outputs of the input switch, the first and second information inputs of which are connected to the inputs of the first and second convolution blocks, respectively, and are the inputs of the device upper and lower bits, respectively, the outputs of the first and second convolution blocks 0 five 0 five 0 five 0 five The inputs of the input switch, the information and control outputs of the first and second drives are connected to the corresponding inputs of the output register, the first and second information outputs of which are connected to the corresponding inputs of the output switch and the inputs of the third and fourth convolution blocks, respectively, the control outputs of which are connected to the corresponding inputs of the first and the second comparison unit, whose inputs are connected to the control outputs of the output register, the first and second information outputs are output The switch are the outputs of the high and low bits of the device information, respectively, about the fact that, in order to increase reliability, a third accumulator, an OR element and a D-flip-flop are entered into the device, and the address input of the third accumulator is connected to the corresponding inputs the first and second drives, the information input of the third accumulator is connected to the control input of the input switch and the output of the OR element, the second input of which is connected to the control input of the output switch and the output of the D-trigger a, whose information input is connected to the output of the third accumulator, and the input of read / write controls is connected to the corresponding inputs of the first and second drives, the first input of the OR element is connected to the output of the first comparison unit and the first error input of the output switch, the second error input of which is connected to the output The second comparison unit, the first and second error outputs of the output switch, form respectively the outputs of the error signals of the lower and lower bits.