SU1193825A1 - Code translator - Google Patents

Description

The invention relates to computing and can be used to convert codes specified in binary form tables

mutual conformity.

The purpose of the invention is to expand the functionality by providing two-way and reciprocal transformation of tabular codes with simultaneous control.

Figure 1 shows the block diagram of the code converter; Fig.2 is a functional diagram of the control unit; on fig.Z - timing charts of the control unit.

The code converter contains the first 1 and second 2 registers, the first 3 and second 4 memory blocks, the control unit 5, the comparator 6 and the switch 7, the first 8 and second 9 inputs of which are the corresponding converter inputs, the first 10 and second 11 outputs are connected to information inputs 12 and 13 of the corresponding registers 1 and 2, the reset inputs of which are connected to the first control input 14. The outputs of the first register 1 are connected to the first outputs 15 of the converter, the address inputs 16 of the first memory block 3 and the information inputs 17 of the second block 4 memory. The outputs of the second register 2 are connected to the second outputs 18 of the converter, the address inputs 19 of the second memory block 4, and the information inputs 20 of the first memory block 3.

The outputs of the first 3 and second 4 memory blocks are connected to the third 21 and fourth 22 inputs of the switches 7, the third and fourth outputs of which are connected to the first and second inputs of the comparator 6, the output of which is connected to the first input 23 of the control unit 5. The first 24 and second 25 outputs of the control unit 5 are connected to the control inputs of the respective registers 1 and 2, the third 26 and the fourth 27 outputs of the control unit 5 are connected to the first control inputs of the first 3 and second 4 memory blocks. The second input of the control unit 5, combined with the second control inputs of the memory blocks 3 and 4, is connected to the second control input 28 of the converter. The third 29 and fourth 30 control inputs of the converter are connected to the corresponding inputs.

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control unit, with the third input

the latter is connected to the manager

input switch 7. Fifth output

control unit 5 is the third

5 output 31 of the converter.

The control unit 5 (FIG. 2) contains delay elements 32 and 33, AND elements 34-42 and OR elements 43-45. The delay of elements 32 and 33 10 is greater than the duration of the circulation cycle.

to block 5 of memory. The inputs of block 5 receive the following signals: "Input tables" (fig.Za) - to the second input 28; "Direction" (Fig.36) - on

15, the third input 29, “Code Maintenance” (fig.Zv) - to the fourth input 30.

At the first input 23 of block 5, a signal "equal to" comes from the comparator, 6 (Fig. Zg). The following signals are removed from the outputs of block 5: "" Memory strobe 1 "(fig. 3) to the third output 26; "Memory strobe 2" (fig.Ze) - on the fourth exit 27; "+1 register 1" (fig.Zh) - on the first exit 24;

"+1 register 2" (fig.Z3) to the second output 25; "End of the cycle" (fig.Zi) on the fifth exit 31.

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The output signals of block 5 are associated with its input signals by the following logical functions:

"Memory Strobe 1" = "Entering Tables"

Λ ("Direction" A "Support of the code" V "Direction" Λ "Maintenance of the code delayed by * £")

35 ’’ Entry of tables “A” Direction ”A“ Code maintenance ”.

"Memory Strobe 2" = "Entering Tables"

A. ("Direction" Λ "Accompanying code delayed by £" V "Direction" A "Accompanying code") V "Entering tables" A "Direction" Λ "Accompanying code",

"+1 register 1" = "Enter tables"

A "Direction" A. "Code maintenance delayed by T".

"+ Ϊ register 2" - "Enter tables"

A "Direction" A "Code maintenance delayed by £".

"End of cycle" = "Entering tables" A "Code maintenance, (delayed by?" V "Entering tables" A "Equal to" D "Maintenance code, delayed by 2 s."

To ensure the work transforms

55 code reader it is necessary to carry out the preparatory stage, which consists in writing conversion tables in a memory block.

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The external control signal "Input tables" comes from input 28 to the inputs of blocks 3 and 4 of memory, thereby transferring them to the information recording mode, and to the input of control unit 5, thereby allowing the generation of pulses at outputs 24 and 25 of control unit 5 and prohibits the analysis of the input 23 block - ¹ ka 5 controls. The external "Direction" signal from input 29, which enters the input of control unit 5, in the "Table entry" mode allows the generation of pulses at outputs 24 and 25 of block 5, and its absence in the "Table input" mode allows generation of pulses at outputs 25 and 27 control unit 5.

In the absence of a "Direction" signal at the control input of the switch 7, the first information inputs 18 are connected, through the switch 7 to the first register 1 and through the first inputs to the comparator 6. The outputs of the first memory block 3 through the third information inputs 21 are connected to the second register 2, and the outputs of the second memory block 4 through the fourth information inputs 22 are connected to the second inputs to the comparator 6. · Control signal. The “direction” from input 29 at the control input of switch 7 connects the outputs of the first memory block.3 to the first inputs of the comparator 6, and the outputs of the second memory block 4 to the first register 1, the second information inputs 9 to the second. th register 2 and the second inputs of the comparator 6.

Let tables of codes M and H be given. It is necessary to order the codes of table M in ascending order of the binary codes of table H and vice versa of table H in ascending order of codes in table M. For example, the letters A, B, C, and P in table M correspond to codes (0 .. . 010.0 ... 000.0 ... 011.0 ... 001), and in the table H codes (0 ... 001.0 ... 011.0 .., 010.0 ... 000), i.e. Table M should be ordered as follows: 0 (0 .. .001), A (0 ... S), C (0 .. .011), B (0 ... 000) correspond to codes (0 ... 000.0 ... 001.0.0.,. 10.0 ... 011) of the table H, and the codes of the table H are ordered as follows: B (0 ... 011), P (0 ... 000) , A (0 ... 001), 0 (0 ... 010) correspond to the codes (0 ... 000.0 ... 061.0 ... 010.0 ... 011) of table M.

To enter the tables M and H, a pulse is sent to the input 14 of the code converter, resetting registers 1 and 2 to the zero state, the second control inputs of the memory blocks 3 and 4 and the second input of the control unit 5 are fed with the control input of the tables. The inputs 8 of the device receive the binary code of table M, the corresponding code 0 ... 000 of table N. Through the first information outputs 10 of the switch 7, it enters the information inputs of the first register 1 and is written there. From the output of register 1, this code goes to the information inputs 17 of the second memory block 4, the outputs of the second register 2 are fed to the address inputs 18 of the second memory block 4.

The “Code Maintenance” impulse from input 30 enters the fourth control input of control unit 5, under its influence output 27 · unit 5 induces an impulse and the process of writing the code of table M at the zero address occurs.

After the end of the write cycle, a pulse appears at the output 25 of the control unit 5, which is fed to the counting input of the second register 2, increasing the value of the co-holding register 2 by one, and the output 31 from the control unit 5 is given a pulse signaling the end of the recording cycle. Then, the second code of table M, corresponding to code 0 ... 01 of table H, goes to inputs 8, and the process proceeds similarly, only the code is written at 0 ... 01 ..., etc. until table M. is completely entered. '

To enter the codes of the table H ne--. Go to the third "input of the control unit 5 and the control input of the switch 7 to send the" Direction "signal from the input 29 and the H table codes should go to the second information inputs 9 of the device. The process of writing the codes is carried out through the register 2 into the first memory block 3. The first register 1 works in the counter mode. The writing process is carried out in the same way as described above. Upon completion of entering the table H, the converter is transferred to the main mode.

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code conversion and works

in the following way.

From the second control inputs of the blocks 3 and 4 of the memory and from the second input of the control block 5, the signal ₅ "Entering tables" is removed, thus translating the code converter into the main mode of operation. Blocks 3 and 4 of memory go into read mode. Outputs 24, and 25 of block 5 are blocked and analysis of input 23 of control block 5 is allowed.

When converting the codes of the table M to the codes of the table H, the "Direction" control signal is removed from input 29. 15 The code through the first information inputs 8 is fed to the comparator 6, and from the output 10 of the switch 7 through the input 12 is fed into the register 1 and recorded in it. From the inputs of the register 1, the code 20 is supplied to the address inputs 16 of the memory block 3. Under the influence of a pulse tracking code from input 30, a pulse appears at the fourth input of control unit 5, which through ~ 25 cuts output 26 of unit 5 goes to the first control input of memory 3 and reads the information. The read information comes from the output of memory block 3 through a switch * 7 to input 13 of register 2. At the output of register 2, the code value converted from M to H appears.

This converted code is fed to the address input 19 of memory block 4. 35

From the output 27 of the control unit 5, a pulse is fed to the first control input of the memory unit 4, information is being read from the memory unit 4, i.e. the inverse conversion of 40 code from H to M. The code value from the outputs of memory block 4 through the inputs 22 of switch 7 is fed to the second inputs of comparator 6, the first inputs of which contain the code value that was transformed twice from M to H and from H to M, the value of the information at the inputs of the comparator 6 during normal operation of the converter will be the same.

The comparator makes a comparison · <codes on the inputs and, if they are equal, the signal from the output of the comparator 6, acting on the input 23 of the control unit 5, allows the generation of a pulse at the fifth output of the control unit 5 (output 31), which accompanies the output code taken from the register outputs 2. If the code values at the inputs of the comparator 6 do not match, it removes the signal from the input 23 of the control unit 5, prohibiting the generation of the tracking pulse of the transformed code at the device output 31, thereby fixing the conversion errors (FIG. 3d and). When a control signal appears

The “direction” at exit 29 is converted in the other direction — from the codes of table H to the codes of table M.

The conversion process is carried out similarly, except that now the codes go through inputs 9 to switch 7, the main conversion is performed by memory block 4, the inverse (controlling) memory block 3, and the output converted code is removed from the outputs of the first register 1. When changing the transformation laws, new compliance tables.

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Claims (1)

CODE CONVERTER * cell holding the first register, the first memory block and the control unit, which is due to the fact that, in order to expand the functionality by providing two-way reciprocal conversion of table codes with simultaneous control, the second memory block, the comparator tor. and the switch, the first and second inputs of which are the corresponding inputs of the converter, the first and second outputs are connected to the information inputs of the first and second registers, respectively, the input reset are connected to the first control input of the inverter and the outputs are connected to corresponding outputs of transducers A-T and to the address inputs of respective memory blocks combined with data inputs sootvetst-. first and second memory blocks, the outputs of which are connected respectively to the third and fourth. the switch inputs, the third and fourth outputs of which are connected to the first and second inputs of the comparator, the output of which is connected to the first input of the control unit, the first and second outputs of which are connected to the counting inputs of the respective registers, the third and fourth outputs of the control unit are connected to the first control inputs of the first one, respectively and the second memory blocks, the second control inputs of which are combined with the second input of the control unit and connected to the second control input of the converter, the third input of the block control is combined with the control input of the switch and connected to the third control input of the converter, the fourth control input of which is connected to the fourth input of the control unit, the fifth output of which is the third output of the converter. one I}