SU1499407A1 - Device for controlling domain storage - Google Patents

Abstract

The invention relates to computing and can be used in the construction of magnetic domain storage devices. The aim of the invention is to reduce power consumption by connecting only the currently required memory blocks. The device allows you to determine in which specific memory blocks the array is physically located, the starting and ending addresses of which are specified, and connect the power source only to these blocks. 2 Il.

Description

The invention relates to computing and can be used when building domain magnetic storage devices.

The purpose of the invention is to reduce energy consumption by sub-staking only the currently required power units.

FIG. 1 shows a functional diagram of the device; in fig. 2 shows an algorithm for operating the device.

The device (Fig. 1) contains a generator 1, a group of control inputs 2, a first element AND 3, a first trigger 4, a second element AND 5, a first comparison element 6, a third element OR 7, a group of 8 memory blocks, a group of 9 elements And, the fourth element OR 10, the first 11 and the second 12 elements OR, the first 13 and second 14 number registers, the third trigger 15, the auxiliary register 16 addresses, the first counter 17, the adder 18, the second element 19

comparison, registers of the initial 20 and final 21 addresses, rpjmny 22 address inputs of the device, block 23 of semi-permanent memory, second trigger 24, decoder 25, group of 26 elements OR, group 27 of trigger, second counter 28, quarter trigger 29, third 30, the fourth 31 and fifth 32 elements And, a group of 33 keys, the sixth element And 34, input 35 of the device number, inputs of clock 36, read 37, reset 38, control 39, following address 40, start of clock 41, write 42, sign of operation with the array 43, the sign of the address work 44, the first clock 45, start 46, the second tact 47 first, handling 48, destination address 49 start address 50, an address 51.

The device works as follows.

Before working with the input 38, the device is reset.

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The reset to the inputs of the element OR 10 and further to the inputs of a group of 26 elements OR, triggers 27, counter 28 and to the first inputs of register 20 of the starting address and register 21 of the final address, and also to the inputs of element SHSh 11 of the setting trigger 4, to its initial state input element OR 12, to the inputs of the first register

The 13th number and the second register 14th number, and N. And the input of the trigger 15, due to which the device is reset. Then, from the inputs 43 or 44 of the operation of the device, the trigger 24 receives a signal, determining if the domain memory works with arrays of information or loader write or read information.

If the entry or stitching of information is more addressable, then the registers of the start address 20 and the first end address 21 will have the same address code. Consequently, at the output of the decoder 25 there will be no control potential, and the control potential from the output of the comparison element 19 does not pass through the AND 30 element (this signal, when working with arrays, at the end of the work, turns off the pitches from the memory blocks). the impulse from the group of 2 inputs passes through the element I 31 and then through the group of 26 elements .l-ffl goes to the inputs of the group 27 of the triggers, due to which the keys 33 turn on they feed all the 8 memory blocks. At the same time, the first nag-pin unit is turned on by cooling the control potential on the trigger 15 through the element 32.

If arrays are to be sampled or recorded, then in the outgoing state, the group of 27 triggers is in zero, and the trigger is 15

set to one state by the control potential from the start-up input 46 of the device. Due to this, the first key of the group. 33 keys connects power only to the first memory block 8. At the same time on the register

20 initial address and register

21 end addresses are set to address codes received from the bus

22 addresses These addresses go to adder 18, where the starting address is extracted from the end address, and

on the element 19 comparison. The addresses are subtracted by the memory access signal coming to the third input of the adder-18, and the received code enters the torus 25, the output potential from which through the elements of OR of group 26 sets one or the other trigger of group 27 to a single state. Due to this, the control potential is supplied to one or the other key of group 33 and the power supply for the additional signal is supplied. a memory block containing some higher addresses of the required array with respect to the initial one,

In this case, during operation, a continuous comparison of the addresses on the additional comparison element 19 occurs (the initial address is increased by adding one) D If the addresses are matched, then the output potential of the comparison element 19 causes the potential to flow to the first input of the 30 And element at the other input of which the permitting potential is already present, with ™ coming from the trigger 24. Due to this, the trigger 29 is set to one state and the clock pulses from the second clock input 47 of the device are fed to the input counter 28, at a time equal to the counter overflow time, the output pulse from it is fed to the input of the element OR 10 and further to the reset of a group of 27 triggers that turn off the power from the additional memory blocks, while the control device is again in the initial state and consumes power is supplied only by the first, dekhsurny memory block, which, with large amounts of memory, significantly reduces the power consumption of the storage device as a whole.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A control device for domain memory comprising a group of a memory block, a generator of clots, a first and a second pin, a first trigger, a link, a first and. the second elements are And, the first counter, the group of elements is And, the block of semi-permanent memory, the first and second registers of the number, the registers of the initial and final addresses, the auxiliary address register, the clock inputs of the memory blocks of the group are connected to the output of the pulse generator, the clock the input of which is the input sync and my device, the first input of the first element I is the input of the device, the second input of the first element I is connected to the output of the first trigger and to the first input of the second element And the second input of which is connected to the third input of the first element And the first input of which is connected to the output of the starting address register, the second input of the first comparison element is connected to the output of the auxiliary address register, the reset input of which is connected to the first inputs of the first and second elements in OR, with inputs., resetting the first and second number registers and the auxiliary address register and with the device reset input, the information inputs of the end and start address registers are respectively the end and start addresses of the device, the address of the terminal memory block is the address input of the device; the control input of the semi-permanent memory block is connected to the control inputs of the memory blocks of the group and to the control input of the device; the input of the next address of the device is connected to the clock input ohm of the register of the start address, the start of the clock input of the device is connected to the second input of the first OR element, the output of which is connected to the reset input of the first trigger, the installation input of which is connected to the output of the semi-permanent memory block and the counting input of the first counter, the reset input of which is connected to the output The second OR element, the second input of which is connected to the overflow output of the first counter and to the input of the auxiliary address register, the output of the first AND element is connected to the input of the second number register, bit whose information input is connected to the outputs of the corresponding elec 99407 numbers ten 15 20 whose information input is the input of the device number, characterized in that, in order to reduce power consumption by connecting only the currently required memory blocks, the third and fourth elements OR, the third and sixth elements are entered into it, the second comparison element , second to fourth triggers, a group of elements OR, a group of triggers, a group of spurs, a second counter, a decoder and an adder, the first input of which is connected to the output of the register of the start address and to the first input of the second element 1 The second input of which is connected to the output of the end address register and the second input of the adder, the output of the second comparison element is connected to the first input of the third element AND, the second input of which is connected to the forward output of the second trigger, the reset inputs and settings are respectively the attributes working with the array and addressing the device, the inverse output of the second trigger is connected to the first input of the fourth element AND, the second input of which is the first clock input of the device, the output of the fourth element a AND is connected to the first input of the fifth element AND and to the nepBbiMii inputs of the elements of the OR group, the second input of the fifth element AND is the device start input, the output of the fifth element AND is connected to the installation input of the third trigger, the reset input of which is connected to the device reset input , the second inputs of the elements of the lash group are connected to the corresponding outputs of the decoder, the input of which is co-. dinen with an adder output, output The third element And is connected to the installation input of the fourth trigger, the reset input of which is connected to the reset inputs of the initial and final registers 25 thirty 35 40 And the group, the first inputs of which are full addresses, the second counter, are connected to the third input of the second element And to the device's recording input, the output of the second number register is connected to the fourth input of the second element, whose output is connected to the control input of the pulse generator, the second the inputs of the elements And the group is connected to the corresponding bits of the output of the first register 55 the second group OR, the first input of which is connected to the device reset input, the second input of the third element OR is connected to the output of the second counter, the counting input of which is connected to the output of the fifth element AND, the first and second inputs of which are connected respectively to the output of the fourth Trig5 the second group OR, the first input of which is connected to the device reset input, the second input of the third element OR is connected to the output of the second counter, the counting input of which is connected to the output of the fifth element AND, the first and second inputs of which are connected respectively to the output of the fourth trigger and with the second clock input of the device, the outputs of the elements of the group 21 of the group are connected to the installation inputs of the corresponding group triggers, the outputs of which through the group from the second through K (the number of keys in the group) are connected s with the inputs of the inversion of the memory blocks of the group from the second to the Kth, the input of the inversion of the first α The group's memory is connected via the first KEY group to the output of the third trigger, the outputs of the group's memory blocks are connected to the corresponding inputs of the fourth OR element, the output of which is connected to the fourth input of the first OR element, the third adder input is the device's access input. . J start j Ojpmeni peyffUMS with HaccugoH iai fgi / Record the starting address, 7 /, if ide). / / Record of the renal address, / names of its code t (Am) / 1 fafoma (, current aresonM Increase tnsKyuieto address by 1. i-i-n Power on at the th. o / tOK memory & feed power on memory f / ioK noS pfCHt U fiafffn f I Chkonets ) 2