SU1278978A1 - Read-only memory with overwriting information - Google Patents

Abstract

The invention relates to computing and can be used in permanent storage devices. Overwriting information. The aim of the invention is to reduce power consumption. This goal is achieved by introducing additional blocks 14 of keys and elements 17, 18, 19 OR NONE, which allows reducing the current consumed by decoders 3, 6. Reducing the capacitance of the discharge buses 5 connected to amplifiers 10 allows the circuit to be more interference resistant. 1 ill., 1 tab.

Description

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The invention relates to computing and can be used in permanent storage devices with overwriting information (PROM).

The purpose of the invention is to reduce the power consumption of the EPROM.

The drawing shows a functional diagram of the PROM.

The EPROM contains drives 1, blocks of 2 column keys, 3 column decoders and bit parameters; 4 and 5 decoders, 6 lines decoders, line buses 7, input lines 8 and 9 of row rows and descramblers, write / read amplifiers 10, output buses 11 devices, recording blocks 12, recording bus 13, additional blocks 14 of keys, outputs 15 of which are connected to the inputs of blocks 2, the first group of address buses 16, elements OR-Hb 17-19, control bus 20 of recording blocks 12.

the second group of address buses 21 (direct and inverse), control buses 22 and 23.

The device works as follows.

In the unselected mode (storage mode), the potential 16 of the logical unit enters the busses 16; the direct and additional address code 21 codes that form the first group of address buses are fed to the potential of the logical zero (or logical unit); 13 of the read and hold recording mode, a potential is supplied whose level is lower than the voltage required to record information and at least equal to the supply voltage of the device.

Tires 15, 20, 22 and 23 establish a low voltage level, as a result, blocks 12 are disconnected from bus 13. The states of the outputs of the decoder 6 are E, depending on the potential level on the control buses 22 and 23; the table.

0- The decoder is disabled.

One of the lower-case pics 7 is selected depending on the address code on the input buses 8

1- outputs in the third state

In read mode, a high and a low voltage level is applied to the address buses 16 in accordance with the address code. Block 14 is turned off if there is a low level potential on its input buses 16, and the decoder 3 columns discharges all 15, except for one, in accordance with addresses 8. Discharge 5 is connected via blocks 2 to discharge types 4 of the selected drive 1. Remaining blocks 14 keys maintain low potential on tires 15, and 2 key blocks are closed.

A logical unit is fed to one of the buses 21, and a logical zero to the other. From the outputs of the elements OR-NOT 17 and 18, which are ideally connected to the tires 16 with a low-level potential, an inverted signal arrives at a logical level on the tires 21.

Thus, the control bus lines 22 and 23 of the decoder of 6 lines belonging to the selected drive are supplied with a logical unit (for example, via bus 22) and a logical zero (23). Den-Shfrator 6 lines, in accordance with the code on the spikes 8, one selected row 7 is charged.

Since the inputs of the remaining OR-NOT elements 4 and 15 are connected at least with one of 1PIN 16, the level of the logical unit is low, at the outputs of these elements there are logical zeros, and on lower-case pnnah 7 there is a potential close to the potential of the lines in storage mode.

Thus, there is a readout of information stored by memory elements located on the intersection of the selected bus 7 of selected accumulator m 1 and bit 2, connected via blocks of 2 keys with bit spikes 5 and connected to amplifiers 10.

In recording mode, the device operates in the same way, the only difference is that a high 11th program voltage is applied to the recording bus 13. In this case, the output 20 of the third element OR NOT 19 of the selected storage device 1 from the recording bus 13 is supplied with a programming voltage, and through the recording blocks 12 to the selected bus 7 a recording voltage is applied. On tires 20 of all other elements OR NOT 19, the level of potential corresponds to a logical

zero and on bus 7 unselected decoders 6 and 3 rows and columns the write voltage does not pass.

Claims (1)

Invention Formula Permanent memory with data rewriting, containing drives, key blocks, the inputs of each of which are connected to the outputs of the corresponding column decoder, and the outputs - with the inputs of read amplifiers, row decoders, the outputs of each of which are connected to the lower-line tires of the corresponding drive and the outputs of the recording unit The inputs of which are the information input of the device and the outputs are connected to the outputs of the respective row decoder and column decoder, the outputs of the read amplifiers are outputs of the device, characterized in that reduce the power consumption of the device, add additional key blocks and OR NOT elements, the first and second inputs of which are combined with the inputs of additional key blocks and are the first group of address buses, the third inputs the first and second elements OR are NOT connected respectively and are the second group of address buses, and the outputs are connected to the control buses of the corresponding line decoder, the outputs of the third OR elements are NOT connected to the control bus of the recording blocks.