SU1603438A1 - Stack storage - Google Patents

Abstract

The invention relates to computing and can be used in information processing systems. The purpose of the invention is to expand the field of application of the device due to the possibility of simultaneous recording and reading. The device contains shift registers 1, 6, buffer registers 3, 5, a RAM 4, a control block 8, a counter 9, a pulse generator 10, a trigger 11 with corresponding connections. 1 hp f-ly, 2 ill.

Description

FIG, g

The invention relates to a calculator, my technique, and can be used in information processing systems.

The purpose of the invention is to expand the field of application by providing the possibility of simultaneous recording and reading.

Fig, 1 is a diagram of a stack storage device; ka of FIG. 2 is a diagram of a control unit.

The device contains (Figures 1 and 2) the first shift register 1, information input 2, the first buffer register 3, the operational drive 4, the second buffer register 5, the second shift register 6, the information output 7, the control unit 8, the counter 9, pulse generator 10, trigger 11, start input 12, stop input 13, first 14, second 15 and third 16 counters-dividers, first delay element 17, OR-NOT element 18, second delay element 19 and capacitor 20.

The shear size of the shift registers (p) 1 and 6 is defined as the quotient of the division of the operating frequency of the RAM and the frequency of arrival of the input information. The operating frequency of the RAM is determined from

f j.

P tan + tc4

where tc4 is the time required to read the information;

tan is the time required to record information.

The device works as follows.

In the initial state, generator 10 is turned off, dividers 14-16, counter 9, flip-flop 11, first shift register 1, first buffer register 3, RAM 4, second buffer register 5 and second shift register 6 are reset shown).

When a start pulse arrives at input 12, a single level appears at the output of trigger 11, triggering a generator of 10 pulses. When synchronization pulses arrive at the corresponding input of the first shift register 1, the information arriving at its input is shifted by one bit. When synchronization pulses arrive at the corresponding input of the second shift register 6, the information recorded in it is shifted by one bit and outputted at device 7. When a p / 2 impulse arrives at the input of control unit 8 (where n is the width of shift registers 1 and 6), the output of counter divider 14 is a signal that arrives at the reverse input of operative accumulator 4. At this moment, at the second output of block 8 A control O is present, which determines the reading mode from the RAM 4 at the zero address coming from the outputs of the counter 9. At the fifth output of the control unit there is a signal 1, i.e. information is rewritten from the operative accumulator 4 to the second buffer register 5.

When the input of the control unit 8 control unit p / 2 impulses at the synchronization input of the first counter-divider 14, and consequently, the signal O appears at the third output of the control unit 8, the output of the second counter separator 15 receives the signal 1, and The output of the control unit 8 is the signal O. When the control unit 8 control unit n / 4 + + l / 2 arrives at the synchronization input, a signal 1 appears at the third output of control unit 8, i.e. information is overwritten from the first buffer register 3 to the operative drive 4.

Upon arrival of the synchronization input of the control unit 8, n pulses, the signal O appears at the third output of the control unit 8, the fourth output of the control unit 8 is the signal 1, the first output of the control unit 8 is the signal 1, the second output of the control unit is the signal O, and at the fifth output of the control unit, signal 1.

Thus, during the second half of the period of the nth pulse, information is overwritten from the second buffer register 5 to the second shift register 6 and from the first shift register 1 to the first buffer register 3.

Claims (2)

1. A stack memory device containing a trigger, the direct output of which is connected to the input of a pulse generator mode setting, a counter, a random access memory, characterized in that, in order to expand the area of the device application by providing simultaneous recording and reading, a block is entered into it control, the first and second buffer registers, the first and second shift registers, the information input of the first shift register is the device of the same name, the outputs of the first shift register are connected to or- .matsionnymi inputs of the first buffer register whose pyhody connected to data inputs of the operational accumulator which outputs are connected with the the information inputs of the second buffer register, the outputs of which are connected to the information inputs of the second shift register, the output of which is the information output of the device, the output of the pulse generator is connected to the synchronization inputs of the first and second shift registers, the first output of the control unit and the second buffer registers and the second shift register, the second output of the control unit is connected to the synchronization input of the first buffer register and the input - reading the RAM, the third output of the control unit is connected to the circulation input of the RAM, the fourth output of the control unit is connected to the synchronization input of the counter, the fifth output of the control unit is connected to the synchronization input of the second buffer register, the output of the counter is connected to the corresponding address inputs RAM, the setup input in 1 trigger is the input to start the device, and the input installation in O - input stop the operation of the device, 2. Pop-1 device, characterized in that the control unit contains an OR-NOT element, the first and second delay elements, the first, second and third counters-dividers, the synchronization inputs of the counter, in-delmtels, are combined and are the synchronization input the control unit, the output of the first divider counter is the third output of the control unit, the output of the second divider counter is connected to the input of the first delay element, the output of which is the second output of the control unit, the output of the third divider counter is connected to the input of the second element This delay and the second input of the element ORI is not the fourth output of the control unit, the output of the second divider counter is connected to the first input of the element OR NOT, the output of which is the fifth output of the control unit, the output of the second delay element is connected to the installation input The third divider counter is the first output of the control unit. Vh. about- t4 15 20 -about 17