JPS62263560A - Data transfer system - Google Patents

Abstract

PURPOSE:To require no transfer of a redundant byte by providing a counter for displaying the effectiveness and the ineffectiveness of the last one byte of receiving data successively transferred to a memory and reading and recognizing this value by a central processing unit. CONSTITUTION:A DMA transfer request signal 2 is transmitted to a DMA control circuit 3 by a data receiving request 4 of even number times or a data receiving completion signal 8 from an input and output device 5. According to a DMA transfer permission signal 3 from the DMA control circuit 3, a data receiving permission signal 5 to the data receiving request signal 4 of the even number times from the input and output device 5 is transmitted to the input and output device 5. The output signal 7 of the counter for counting whether the data receiving request signal 4 is the even number times or odd number times is outputted to a host data bus and the CPU6, when the interruption of the DMA transfer completion is raised from the DMA control circuit 3, reads it from a data bus, thereby, recognizes whether the data on the last odd number address is effective or ineffective.

Description

[Detailed Description of the Invention] [Summary] In DMA transfer from an input/output device with an 8-pin data bus width to a 16-bit wide memory, the last byte of received data continuously transferred to the memory A counter is provided to display whether the data is valid or invalid, and this value is read and recognized by the central processing unit, eliminating the need for redundant byte transfers.

[Industrial Field of Application] The present invention relates to a data transfer method between an input/output device and a main memory in a digital computer, and particularly to a direct memory access (hereinafter abbreviated as DMA) transfer method.

DMA is a method in which an input/output device or a human output control device directly accesses the main memory to read and write without going through a central processing unit (hereinafter abbreviated as CPU), and is widely used in information processing devices. It is being said.

The input/output device data bus is typically 8 bits wide, and the main memory data width is typically 16 or 32 bits. Therefore, when a fractional byte occurs in the main memory in DMA, special processing is required, and the most efficient processing method is desired.

[Prior Art] Conventionally, data transfer using DMA is performed by byte transfer from an input/output device having an 8-bit wide port connected to a 16-bit bus to memory, as shown in Figure 4(a). It was common.

That is, the 8-bit data from the input/output device is distributed to the upper/lower part of the memory by the memory control signal from the DMA control circuit, and 16-bit data is stored at consecutive addresses in the 16-bit memory.
Store bytes sequentially.

There is also a method, as shown in FIG. 6(b), in which 8-bit data from an input/output device is latched in a flip-flop and transferred as a word to a memory.

That is, the upper data of the 8-bit data from the input/output device is latched by a flip-flop according to the device control signal from the DMA1%II'4B circuit, and the upper and lower data are simultaneously written to the memory.

The former performs DMA every time 1 byte of data is received or received.
Since a transfer request is issued to the i#J control circuit and only one byte of data can be transferred in an IDMA cycle, there is a drawback that the bus load increases and the throughput of the entire system decreases.

In the latter case, even if the data from the input/output device is an odd number of bytes, it is transferred to the memory in words, so it is necessary to write invalid data to the last odd address in the memory as shown in Figure 5. there were.

That is, as shown in FIG. 5(a), when storing in the memory in words, D M A i! The memory address from the II control circuit is increased by 2 with one transfer.

As shown in (b), when the data from the input/output device is an even number of bytes, valid data is written up to the memory address +1 at the end of the DMA transfer, but as shown in (c), when the data is an even number of bytes, valid data is written to the memory address +1 address at the end of the DMA transfer. When this occurs, the data directed to the memory address +1 address at the end of the DMA transfer is written.

Therefore, one byte of fixed pattern redundant data is required at the end of the received data in order to determine whether the data on the final odd address is invalid or valid.

[Problems to be Solved by the Invention] The present invention aims to provide a new data transfer method that solves the above-mentioned conventional problems.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the data transfer system of the present invention.

In the figure, 2 is a flip-flop that latches upper-order data.

Reference numeral 1 denotes a data reception control circuit, which includes a counter for counting whether data reception requests from an input/output device are an even number or an odd number, and a gate for controlling various signals.

3 is a normal DMA control circuit.

4 is a 16-bit memory, 5 is an input/output device, and 6 is a central processing unit (CPU).

A data reception control circuit 1 is a circuit provided for the present invention.

Although FIG. 1 has been described as a 16-bit memory for convenience of explanation, the present invention is not limited to 16-bit memory, and even in the case of a memory with a 32-bit configuration, etc., a flip-flop that latches data and a data reception control circuit are used. This can be applied by increasing the number of flip-flops that count data reception requests in one.

[Operation] (1) The data reception control circuit 1 counts whether the data reception request signal (2) from the input/output device 5 is an even number or an odd number.

(2) At the odd-numbered data request, the latch clock ■
At the same time, it outputs a data reception permission signal ■ to the input/output device 5 in response to the data reception request.

(3) Even-numbered data reception request from the input/output device 5■
Alternatively, in response to the data reception end signal ■, a DMA transfer request signal ■ is sent to the DMA control circuit 3.

(4) When the DMA transfer transfer permission signal goes up from the DMA control circuit 3, the data reception permission signal ■ is sent to the input/output device 5 in response to the even-numbered data reception request signal ■ from the input/output device 5.

(5) The output signal ■ of the counter that counts whether the data reception request signal ■ is an even number or an odd number is output to the upper data bus, and the CPU 6 receives a signal from the DMA control circuit 3 to indicate whether the DMA transfer has ended. When an interrupt occurs, it is recognized whether the data at the last odd address is valid or invalid by reading it from the data bus.

In the above way, it is possible to recognize whether the data on the final odd address is valid or invalid.
Redundant data indicating the end of data is not required.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 and 3.

FIG. 2 is a circuit diagram of a main part of an embodiment of the present invention, showing an internal circuit of a data reception control circuit.

In FIG. 2, reference numeral 11 denotes a JK-type rough flip-flop, which constitutes a 1-bit counter that receives the data reception request signal ■ from the input/output device as a clock input, and determines whether the data reception request signal ■ is even or odd. The number of times is counted cyclically.

The output of the counter 11 is “
1”, and becomes “0” at the even-numbered data reception request.

When an odd-numbered data reception request is made, that is, when the output of the counter 11 is 1'', the AND gate 13 opens, and the data reception permission signal ■ is sent to the data reception request signal ■, and the input/output device is sent to the flip-flop connected to the upper data bus. Outputs the data latch pulse ■.

When an even-numbered data reception request occurs, that is, when the output of the counter 11 is "0", the AND gate 12 opens and the OR gate 1
The signal is input to the S terminal of the R3 type flip-flop 15 via the input terminal 4, and is set.

When the flip-flop 15 is set, a DMA transfer request signal (2) is output to the DMA control circuit.

When the DMA transfer permission signal from the DMA control circuit goes up,
This is input to the R terminal of the flip-flop 15 to reset it, and the DMA transfer request signal ■ is dropped, and at the same time, the
A data reception permission signal (2) in response to an even-numbered data reception request is sent to the input/output device via the R gate 16.

The input/output device receives the data reception permission signal (2), sends the lower data to the lower data bus, and transfers the word to the memory together with the upper data latched in the flip-flop of the upper data bus.

When the input/output device completes the data transfer, it sends out a data reception completion signal (■).

The data reception end signal (2) is input to the S terminal of the flip-flop 15 via the OR gate 14.

If the data reception request is an even number, the flip-flop 15 is already set, but if it is an odd number, it is in the reset state, so this is set, and the DM
A transfer request ■ is sent.

This terminates the DMA transfer.

Upon completion of the DMA transfer, the DMA control circuit raises a DMA transfer interrupt to the CPU.

When the CPU receives this, it sends a continuous signal to the driver 17 and reads the output of the counter 11.
Determine whether the reception requests were received an odd number of times or an even number of times.

When the output of the counter 11 is "1", there is invalid data at address (memory address at the end of DMA transfer) +1, and when the output of the counter 11 is "0", (memory address)
It can be determined that there is valid data at address +1.

FIG. 3 shows a time chart of each signal in this embodiment.

From the top, data reception request ■, received data, counter output, latch clock ■, data reception permission ■, DMA transfer request ■, DMA transfer transfer permission stand and data reception end ■
Indicates the timing of

At point (2), a data reception request (2) is sent from the input/output device, the counter becomes "1", the latch clock (2) turns "on", and a data reception permission (2) is sent.

At point (2), when data reception request (2) is dropped, rough clock (2) and data reception permission (2) are dropped.

At point (2), when the next data reception request (2) is raised, the output of the counter is inverted and becomes "θ", and DMA!
A DMA transfer request ■ is sent to the J control circuit.

When the DMA transfer permission unit is issued from the DMA1#1t11 circuit at the time of ■, data reception is permitted to the input/output device■
is sent, and the DMA transfer request ■ is dropped.

As a result, words are transferred from the upper data bus and the lower data bus.

At point (2), when the data reception request (2) is dropped, the data reception permission (2) and the DMA permission (2) are dropped.

At point [F], when the data reception end ■ is sent from the input/output device, a DMA request ■ is sent to the DMA control device regardless of whether the data reception request ■ is an odd number or an even number. When you receive a DMA transfer permission in response,
Send data reception permission ■ to the input/output device and end the DMA transfer.

[Effects of the Invention] As explained above, according to the present invention, the load on the bus can be reduced by performing word transfer between the memory and the input/output device, and it is possible to determine whether the last odd address is valid or invalid without redundant data. This has an extremely large effect on improving system throughput.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a main circuit diagram of an embodiment of the present invention, Fig. 3 is a time chart of an embodiment of the present invention, and Fig. 4 is a block diagram of a conventional example. , FIG. 5 is a diagram showing the data structure on the memory. In the drawing, l is a data reception control circuit, 2 is a flip-flop, 3 is a DMA control circuit, 4 is a memory, 5 is an input/output device, 6 is a central processing unit (CPU), 11 and 15 are flip-flops, 12, 13 is an AND gate, 14 and 16 are OR gates, and 17 is a driver. Principle block diagram of the present invention jI1 Figure ■ ■ OD ■ [F] Time chart of one embodiment of the present invention (b) Block diagram of conventional example Figure 4 Diagram showing data structure on memory Figure 5

Claims (1)

[Claims] In a DMA transfer from a 1-byte wide input/output device (5) to a multi-byte wide storage device (4), the input/output device (5)
It has a flip-flop (2) that latches data per byte from and converts it into a multi-byte wide bus, and a counter that counts data reception requests from the input/output device (5). The data reception control means (1) generates a control signal to the DMA control means (3) and the input/output device (5), and a latch control signal to the flip-flop (2), and when the DMA transfer ends, the central processing A data transfer method characterized in that the device (6) is configured to recognize whether data at the final address is valid or invalid by reading the output of the counter.