SU1109751A1 - Parallel firmware control unit - Google Patents

Abstract

MICROPROGRAMME CONTROL DEVICE containing an address register, three IL elements, first and second counters, an address decoder, a microinstruction memory block, three AND elements, a clock generator, a microoperation register, the input group of the first element OR is a group of logic device inputs, the output of the first element OR is connected to the first input of the group of information inputs of the address register, the remaining inputs of the group of information inputs of which are connected to the outputs of the address code of the microcoma memory block d, the outputs of the micro-operation code of which are connected to the control outputs of the device through the register of micro-operations, the outputs of the code of the number of blocked clock pulses of the memory block are connected to the information inputs of the first counter, the subtracting input of which is connected to the outputs of the first element And the first input of which is connected to the output of the second element OR and through the element NOT with the first input of the second element AND, the group of inputs of the second element OR is connected with the group of information outputs of the first counter, the second input of the first element nta I is connected to the output of the clock generator and to the second input of the second element I, the output of which is connected to the gate of the address decoder, the group of inputs and the output group of which are respectively connected to the group of information outputs of the second counter and the group of address inputs of the microcommand memory block, summing up, the input of the second counter is connected to the output of the third element, And, characterized in that, in order to expand the scope of application due to the realization of the possibility of asynchronous control signals It also contains two delay elements, a multiplexer, a one-shot and a trigger, with the trigger output connected to the first input of the third element And to the third input of the second element And, the second input of the third element And through the first delay element connected to the output of the second element And, the input of the CO installation into the O flip-flop is connected to the output of controlling the formation of the microcommand address of the microcommand memory unit and to the input of the one-vibrator whose output is connected to the first control input of the multiplexer and through the second the delay element — with the installation input into the address register O, whose output group is connected to the first group of information inputs of the multiplexer, the second control input of which is an input to control the start of operation of the device, the second group of information inputs of the multiplexer is a group of code inputs

Description

the initial microcommand of the device, the counter and with the group of inputs, the third group of outputs of the multiplexer of the ISH1 connection, the output of which is connected with the group of information inputs is dinene with the installation input of 1 trigger.

1109751

The invention relates to computing and can be used as a control device with programmable logic in general and special purpose computers.

A firmware control device is known comprising a clock pulse generator, a group of counters, a group of triggers, an AND element, an address register, a delay element, a memory block, a microinstruction register, decoders that provide a variable micro-tact, transition to the next state after executing the longest microoperation in current microcommand 1.

The disadvantage of the device is a narrow field of application, due to the impossibility of performing micro-operations with arbitrary moments of onset and duration in a micro-tact.

A firmware control device containing a microinstructions memory block is also known — an address counter, an address decoder, a microinstruction register, a clock counter, a microoperations block, an microoperation decoder, an AND group of elements, an OR element 23.

The disadvantage of this device is a narrow field of application, due to the performance of microoperations in one micro-tact and the impossibility of micro-microchromia with arbitrary starting points and duration in the micro-tact.

Closest to the proposed technical essence and the achieved result is a firmware control device containing serially connected first address register. , the first decoder, the first memory block, the second register address and the first block of AND elements, the second input of which is the input of the logic conditions of the device, and the output is connected to the input of the first address register, clock generator, OR element, counter, output which is connected to the input of the decoder, the second, third and fourth memory blocks, the second, third and fourth decoders, the third and fourth address registers, a group of counters, the switching node of the beginning of micro-operations, a group of blocks of elements And, the first, second and third elements AND, group of elements OR, element NOT, and the first output of the clock generator is connected to the first input of the first element AND, the second input of which is connected through the element NOT to the output of the element OR, and to the first input of the second element And, the output of the first element AND is connected to input inputs of the first, second, third and fourth decoders, information inputs of the second, third, fourth decoders are connected respectively to the second, third, fourth outputs of the first address register, and outputs through the second, third , quarter-hpc memory blocks — with the first output of the device, the inputs of the third and fourth address registers, respectively, the outputs of the bits, except the last third address register, are connected to the first inputs of the switching node of the micro-operations start moments, the second inputs of which are connected to the outputs of the pulse decoder, and the outputs the switching node is connected to the first inputs of a group of blocks of elements I, the second inputs of which are connected to the outputs of the fourth address register, and the outputs to the information inputs of a group of scratches, cat outputs the first group of elements OR are connected to the second output of the device and to the inputs of the element OR, the second output of the pulse generator is connected to the first input tert | its element is And, the second input, which is connected to the output of the last bit of the third address register, and the output to the counting input of the counter and to the second input of the element I, the output of which is connected to the subtracting inputs of the group of counters 3.  A disadvantage of the known device is the narrow scope.  When forming micro-operations with pro.  By arbitrary moments of onset and length of time in a micro-tact, a known device does not allow issuing several micro-operations from one output to the time of issuing one long mic operation from another output.  It does not have to form micro-operations with a duration that exceeds the duration of the micro-tact.  Moreover, during the sampling of micro-operations prints from the memory blocks to the control object, no useful information is output, which significantly reduces the speed of the known device and limits its scope.  The task in the memory block of the codes for the duration of micro-operations entails a large amount of equipment for additional storage of the code at the output of the device and unfolding it in a time sequence.  This ultimately reduces the functional capabilities and speed due to the time delay of the signals on the elements and leads to an increase in the internal cycle of the device.  The purpose of the invention is the expansion of the field of application due to the realization of the possibility of asynchronous output of control signals.   The goal is achieved by the fact that the device containing the address register has three OR elements, the first and second sensors, an address decoder, a microcommand memory block, three AND elements, a clock generator, a microoperation register, and the input group of the first element OR is a group inputs of logical conditions of the device, the output of the first element OR Connected to the first input of the group of information inputs of the address register, the remaining inputs of the group of information inputs of which are connected to the outputs of the address code of the memory block. microinstructions, the outputs of the micro-operations code of which through the micro-operations register are connected to the control outputs of the device, the outputs of the code of the number of blocked clock pulses of the memory block are connected by the synformational inputs of the first counter, the subtracting input of which is connected to the outputs of the first element I, the first input of which is connected to the output the second element OR and through the element NOT with the first input of the second element AND, the group of inputs of the second element OR is connected to the group of information outputs of the first counter, the second input of the first element I is connected to the output of the clock pulse generator and to the second input of the second element I, the output of which is connected to the gate input of the address decoder, the group of inputs and the group of outputs of which are respectively connected to the group of information outputs of the micro-commands summing the input of the second counter is connected to the output of the third element And, additionally introduced two delay elements, a multiplexer, a one-shot and a trigger, and the trigger output is connected to the first in the third element And the third input of the second element And the second input of the third element And through the first delay element connected to the output of the second element And, the input setting in O of the trigger is connected to the control output of forming the microcommand address of the microinstructions memory block and the single-vibrator input, output which is connected to the first control input of the multiplexer and through the second delay element to the input of the installation in the address register O, whose output group is connected to the first group of information inputs of the multiplexer, Torah control input which is input to control the beginning of the device, a second group of information inputs of the multiplexer is a group of inputs the initial microinstruction code device groups. and the multiplexer outputs are connected to the information group.  the inputs of the second counter and with the group of inputs of the third OR element, the output of which is connected to the input of the installation in 1 trigger.  The essence of the invention is that the control signals provided by the microprogrammed control devices are characterized by the onset of S11, the duration and the end of the output.  Each of these features may be encoded in a memory unit.  In the proposed device, unlike the known ones, the beginning and end of the control pulse is encoded. The pulse itself is formed by the counting trigger of the register of microoperations during two samples from the memory block of the device.  On the first signal from the memory block, the counting trigger goes to the unit state and starts the control pulse, on the second signal the trigger returns to the initial state and the control pulse is interrupted.  Such encoding using counting triggers allows organizing asynchronous control signals not only during the execution of a single microcommand or micrototact, but also within the entire microprogram.  One microinstruction in the memory unit can store both the signs of the beginning and the signs of the end of the microoperations, as well as the sign of the absence of a change in the state of the counting trigger.  The microcommands are selected as necessary to change the control sig nals.  At the same moment, both the end of the performed micro-operations and the start of the next micro-operations can be set.  In this case, the control signals on the third group of outputs can remain unchanged due to the absence of an effect on the count input of the register of micro-operations.  Since the beginning and end of the control signal in different microcommands, it is his.  duration can be arbitrary to the limit :; firmware.  The smallest duration of the control signal is equal to the shortest micro-operation performed in the operating device.  of a radio transmitter and depends only on the speed of the selected element base of the microprogram control device. For locks, for example, prohibiting the interruption of the microprogram being executed, the duration of a certain control signal can be equal to the execution time of the entire microprogram.  During the execution of such long microoperations, a register of microoperations can be replaced by several microinstructions, each of which at one or several outputs can consistently begin and terminate short or medium duration control pulses of microoperations, due to which the asynchronous operation mode of the device is organized.  The sample of the next microcommand is combined with the execution time of the previous microcommand, which ensures the continuous issuance of microoperations and a significant increase in the speed of the device.  In addition, independent control signals from each output can optimize the execution of groups of linear sequences of microcommands over time and combine them into separate microprograms with the assignment of a single address, and execute the microprogram in natural addressing mode, and transitions between micro subprograms in forced addressing mode .  The drawing shows a functional diagram of the firmware control device.  The device contains the first element OR 1, register 2 addresses with inputs 2. 1 (troupe of informational inputs) to which the unmodifiable part of the address code arrives, 2. 2 The first group of information inputs, which receives the modified part of the address code, register 3 micro-operations, the second element 4 delay, one-shot 5, multiplexer 6 with inputs 6. 1 (first group of information inputs), 6. 2 (first manager), (second group of information inputs), 6. 4 (second control input), an address counter 7, an address decoder 8, a microcommand memory block 9 with outputs 9. 1 (address code outputs), 9. 2 (outputs of micro-operations code), 9. 3 (control output of the micro-command address formation), 9. 4 (outputs of the code of the number of blocked clock pulses), the third element OR 10, the trigger 11, the third element AND 12, the second element And 13, the first element 14 delay, the generator of 15-clock pulses, the first element And 16, the counter 17, the second element OR 18 , element 19, stroke 20, logical conditions of the device, input 21 of the initial microcode code of the device, input 22 of the control of the device operation, control outputs of the device 23.  7  1 The purpose of the main functional elements of the firmware control device is as follows.  Memory block 9 is designed to store codes of the signs of the beginning and end of micro-operations in the micro subprogram, the code of the number of blocked clock pulses preventing the control signals on the outputs 23 of the device, as well as the unmodified parts of the micro subprograms address codes.  The multiplexer 6 allows the transfer of the address to the counter 7 of the address from the register 2 of the address or from the input 21 of the device in accordance with the control signals received at the inputs 6. 2 and 6. 4 multiplexer.  The counter 7 of the address sequentially selects the microprogram addresses in the natural addressing mode, and the counter 17 is designed to store the code of the number of blocked micro-clock clocks.  A clock pulse generator 15 serves to generate pulses that synchronize the operation of the device.  Register 2 of the address serves to store the address of the next microsubroutine and its modification with forced addressing.  The second delay element 4 serves to reset the contents of the address register 2.  One vibrator 5 serves to control the operation of multiplexer 6.  The trigger 11 and the first delay element 14 control the sampling process from the memory block 9 and the generation of the address in the address counter 7.   In the initial state, the memory elements of the device are in the zero state.  The device works as follows.  From the input 21 devices to the information. Inputs 6. 3, multiplexer 6 receives an operation code representing the code of the initial microcommand of the micro subroutine.  At the same time, from the input 22 to the second control input 6. 4 multiplexer 6 receives a start-up signal.  On this signal, the operation code through multiplexer 6 enters the address meter 7 and parallel to Vlod. s of element OR 10.  At the output of the element OR 10, a high 1 potential is formed, which, entering the trigger input 11, sets it to 1, after which the Start Work signal is removed.  The unit from the output of the trigger 11 is supplied to the elements I-12 and 13 and allows the clock pulses to pass through them from the generator 15 (the counter 17 is in the zero state and the output of the element HE 19 has a signal that allows the pulse to pass through the element 13) .  The first clock pulse from the output of the generator 15 through the element And 13 enters the gate input of the decoder 8 addresses and selects from memory block 9.  From the memory block 9, the unmodifiable portion of the code of the address of the next Microsubprogram, which is from output 9, is read. 1 block 9 is fed to the inputs 2. 1 register 2 addresses.  The code of micro-operations of the first micro-command from outputs 9. 2 blocks 9 of the memory enters the register 3 of the micro-operations on the even-numbered inputs of the T-flip-flops, setting the corresponding ones in one state, which sets the beginning of the output of a certain set of control signals to the output 23 of the device.  The end of each of them, made by transferring the T of the trigger to the zero state, can be specified in any of the following microprogram microcommands.  The delay time of the element 14 is equal to the time duration of the clock pulse, therefore at the moment of stopping the impact of the clock pulse on the gate input of the address decoder 8 from the output of the delay element 14 through the And 12 element the summing input of the address counter 7 receives a signal, increasing its content by one.  After this, the second clock pulse resolves a sample from memory block 9 of the next micro-instruction containing only the code of micro-operations.  This microinstruction can simultaneously terminate part of the control signals, leaving the other part of the output signals unchanged, and by acting on the counting inputs of register 3 triggers, start the execution of new microoperations.  At the same time, the end of one and the start of issuing other micro-operations allows eliminating the overhead of changing micro-commands in the register of micro-operations, and the ability to not interrupt the control signal when changing micro-commands provides an arbitrary duration of this signal within microprogram рограм.  Such an organization of operation of the device implies the selection of block of memory of microinstructions from block 9 only at the necessary moments, the time when a change in output signals is required.  If within a few cycles of the generator 15, start; since (h + 1) -th clock cycle, it is not necessary not to interrupt or begin micro-operations, then in the microcommand executed in the nth clock cycle, sets the code for the number of blocked clock pulses.  After selecting a microcommand from block 9 of memory, the code of the number of blocked clock pulses from output 9. 4 of block 9 enters the information inputs of counter 17 and through the element OR 18, the element NOT 19 prohibits the passage of clock pulses through the element And 13.  At the same time the signal from the output of the element OR 18 is fed to the input of the element AND 16, allowing the passage of clock pulses through it from the generator 15 to read the input of the counter 17.  In (n + l) -th cycle of operation of the micro-sampling device from memory block 9 does not occur, and the pulse from generator 15, coming through AND 16 to the subtracting input of counter 17, reduces its content by one.  After zeroing the counter 17 at the output of the element OR 18, a low potential is established, which through the element NOT 19 allows the passage of the next so-called pulse through the element I 13.  At the same time, the low potential from the output of the element OR 18 prohibits the passage of clock pulses from the generator 15 to the subtraction of the input of the counter 17 through the element 16.  The clock blocking circuit eliminates the storage of empty microcommands in the memory block 9.  The linear sequence of micro commands is executed by the device in the natural addressing mode, t. e.  each subsequent sample from the memory is preceded by an increase in the contents of the address counter by one.  This makes it possible not to store in the memory block 9 the address parts of all micro-instructions, and, consequently, to reduce its volume. Transitions between micro-subprograms, e. e.  The transitions according to logical conditions are carried out in the following manner: From register 3 of micro-operations using a micro-command, a micro-interrogation of the device is set, the state of which determines branching in the microprogram.  The signal from the polled device is fed to the input 20 of the firmware of the control unit and through the element OR 1 sets the trigger (input 2. 2) register 2 addresses are one. If no signal was received from the device being polled, the state of the modified bit of register 2 address remains zero and thus the second possible transition address is formed.  The (n + 1) -th micro-command corresponding to the last micro-command of the micro-sub-program defines the end of the micro-operation of the polled device and the control signal for rewriting the generated address from register 2 of the address to counter 7 of the address.  After sampling from the 7p + 1) -m microcommand memory, the control signal from output 9. 3 blocks of memory 9 are fed to. the input of the installation a of the trigger 11, set it to the zero state, and to the input of the one-shot 5.  The zero potential from the output of the trigger 11 prohibits the passage of clock pulses from the generator 15 through the elements 12 and 13.  As a result, an increase in the content of the counter 7 addresses per unit will be blocked.  The one-vibration 5 under the influence of a control signal at its input generates a pulse whose duration is equal to the rewriting time of the address from the register 2 addresses to the counter 7 addresses.  This pulse from the output of the one-shot 5 is fed to the control input 6. 2 multiplexer 6, permitting the address to be rewritten by the next micro subgroup about 1, and through the delay element 4 enters the input of the setting in the O register 2 of the address, discarding its contents after rewriting the address.  In parallel with the rewriting of the address in the address counter 7, the address code through the element OR 10 sets the trigger 11 to 1.  The output signal of the trigger 11 is supplied to the elements And 12 and 13 and again allows the generator 15 clock pulses to produce a sequential sampling of micro-commands micro subprograms.  Note that the transition by logical conditions is caused not by the entire set of devices of the controlled object, but by its individual parts, for example

therefore, it is not necessary to stop issuing control signals to the rest of the object, which is implemented in the control device. At the same time that the firmware control device switches to another micro subprogram, control signals are not output to those devices on which this transition depends but they are not terminated for part of the controlled object. These features should be taken into account when programming the control memory of the firmware control device.

For programs with a large number of branches, the capabilities of the device make it possible to organize a purely forced addressing mode as follows. The group of micro-operations is implemented by two micro-commands, the first of which contains the address part and the operational part, which sets the beginning of micro-operations. The second microinstruction contains the operational part, which sets the end of the executed microoperations and the control signal of rewriting the address from the register 2 of the address to the counter 7 of the address. In this case, the operation of the device is organized in the same way and described. The use of natural addressing with a linear sequence of microinstructions significantly reduces the overall execution time of the micro subprogram by rational placement of the micro ops in time. This is provided by new features of the device, simultaneously starting one and ending other micro-operations, as well as the property of preserving the signal at the output of the device when changing micro-commands.

The end of the operation of the device after the execution of the firmware is set programmatically. The last microsubroutine proceeds to a microcommand with a zero address part and a single control sign in the operating part. After sampling the memory fault, the control signal from the output 9.3 of the memory block 9 sets the trigger 11 to the zero state, which blocks the subsequent memory access signals, and starts the one-shot 5. The single-shot 5 allows the address to be overwritten by the multiplex 6 from register 2 to the counter 7. But since the address code is zero, it, having passed the OR 10 element, cannot set trigger 11 into a single state, which saves the clock pulses of the generator 15. The device waits for the arrival of a new operation code and the Start operation signal.

Thus, the asynchronous issuance of control signals improves the technical characteristics of the proposed device and extends the scope of its application.

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Claims (1)

A MICROPROGRAM CONTROL DEVICE containing an address register, three OR elements, first and second counters, an address decoder, a micro memory instruction block, three AND elements, a clock generator, a microoperation register, the input group of the first OR element being the group of inputs of the device’s logical conditions, the output of the first of the OR element is connected to the first input of the group of information inputs of the address register, the remaining inputs of the group of information inputs of which are connected to the outputs of the address code of the micro-memory block, the microoperation code of which through the microoperation register is connected to the control outputs of the device, the code outputs of the number of blocked clock pulses of the memory block are connected to the information inputs of the first counter, the subtractive input of which is connected to the outputs of the first AND element, the first input of which is connected to the output of the second OR element and through the element NOT with the first input of the second AND element, the group of inputs of the second OR element is connected to the group of information outputs of the first counter, the second input of the first AND element is connected with the output of the clock pulse generator and with the second input of the second element And, the output of which is connected to the gate input of the address decoder, the group of inputs and the group of outputs of which are respectively connected to the group of information outputs of the second counter and to the group of address inputs of the memory block of microcommands, summing the input of the second counter connected to the output of the third AND element, characterized in that, in order to expand the scope of application by realizing the possibility of asynchronous operation of control signals, it is an additional but contains two delay elements, a multiplexer, a one-shot and a trigger, with the trigger output connected to the first input of the third element And and the third input of the second element And, the second input of the third element And through the first delay element connected to the output of the second element And, the installation input in O '· the trigger is connected to the control output by generating the micro-command address of the micro-command memory block and to the input of a single-shot, the output of which is connected to the first control input of the multiplexer and through the second delay element to the input of the mouth There are 0 entries in the address register, the group of outputs of which is connected to the first group of information inputs of the multiplexer, the second control input ^ of which is the control input of the device's operation, the second group of information inputs of the multiplexer is the group of input code of the initial microcommand of the device, the group of outputs of the multiplexer will connect the yen to the group of information inputs counter and with the group of inputs of the third element OR, the output of which is connected to the input of the installation in 1 trigger