SU1005049A1 - Microprogram control device - Google Patents

Description

The invention relates to automation and computer technology and can be used as a multi-cycle device for microprogramming control in the construction of computers and systems, as well as automated control systems for technological processes.

A firmware control device is known that contains an address register, a microprogram memory block, a microinstruction register, descramblers, a microprogram beat duration control block (I.

The disadvantage of this device is its low reliability, due to the formation of the end of the micro-tact on the sectional delay lines.

The closest to the proposed technical essence and the achieved positive effect is a device containing an address register, serially connected clock generator, clock signal block, serially connected first address decoder, first memory block, first microcommand register, divided into n operational fields and one address field, and each of the Shioni operas

field contains control and information parts connected in series to the second address decoder, the second storage unit, the second micro-command register containing the main field and n operating fields, the control decoder code, the first group of AND blocks, the first block of OR elements, and the second group of elec blocks cops And, the first group of blocks of elements OR, block of elements 2 AND - OR, n decoders of operation codes, trig, herm control 2. .

A disadvantage of this device is its low speed, which is due to the use of micro-tacts of constant length in multi-tact microcommands regardless of the strokes of issuing the last micro-operation.

20

The execution time of a microprogrammer consisting of NQ one-cycle micro-instructions and N multi-tact micro-instructions is equal to

T, NoTo M „T„. tto n ,,

25

where Tjj is the nanotact d)

m is the number of nanotacts in the mycrotact. So the prototype has

30 by a large time redundancy, which is due to the fact that no matter in which nanotact the last microoperation is performed in a multi-tact micro-command, its execution time is equal to T,

The purpose of the invention is to increase the speed of the device.

Claims (2)

The goal is achieved by the fact that the device containing the address register, clock pulse generator, meter, decoder, serially connected first address decoder, first memory block, first microcommand register, serially connected second address decoder, second memory block, second microprocessor control register the first group of blocks of elements AND, the first block of elements OR, the second the group of AND blocks, the first group of OR blocks, the 2I-OR block, the opcode decoder operation codes, the control trigger, the output of the address register is connected to the information decoders of the control decoders, respectively, whose outputs are connected to the first inputs of the first cell blocks, second entrances.  which are connected to the output of the decoder, the information input of which is connected to the output of the counter, the counting input of which is connected to the output of the clock generator and to the control input of the decoder, the outputs of the AND element blocks of the first group are connected to the synchronization inputs of the decoder of operation codes, respectively, the operating outputs of the second the register of micro-instructions are connected to the first inputs of the blocks of elements AND of the second group, the second inputs of which are connected to the zero output of the control trigger, the outputs of the blocks of elements AND of the second group are connected to the first inputs of the blocks of elements OR of the first group, the outputs of which are connected respectively to the information inputs of the decoder-operation codes, the outputs of which are connected to the output of the device’s microoperations, a third group of the blocks of elements I, first, second, third and fourth elements AND, first, second, third, fourth and fifth elements OR, first, second and third elements of delay, first, second, third, fourth, fifth, sixth and seventh one-shot, b the block of selection of the maximal nano-tact, micro-tact formation trigger, the first input of the first element I connected to the unit output of the control trigger, the first input of the second element I connected to the zero output of the control trigger, the second inputs of the first and second elements I connecting to the single input of the trigger forming the microactact and the first one-shot is connected to the zeroing input of the control bits of the first micro-command register whose address output is connected to the first input of the first group of inputs of the element ale ntov 2I-OR, the second input of the first group of inputs of which is connected to the unit output of the control trigger / zero output of which is connected to the first input of the second group of inputs of the block of elements 2I-OR, the second input of the second group of inputs of which is connected to the address output of the second micro-command register, output the block of elements 2И-OR is connected to the first information of the first lm input of the address register, the second information input of which is connected to the input of the initial address of the device, the third inputs of the first and second elements And are connected to the output of the - the outputs of the first and second elements I are connected to the synchronizing inputs of the first and second decoder addresses, respectively, and to the first and second inputs of the first OR element, the output of which is connected to the zero input of the microtakt trigger via the first element of the second, the single input of which is connected to the output of the second - an OR element, the first input of which is connected to the outputs of the blocks of elements AND of the second group, the second input - with the output of the maximum nanotact selection unit, the first input of which is connected to the output control decoders, the second input - with the output of the decoder, the third input of the second element OR is connected to the input of the device's initial address, the output of the microcommand type label of the second micro-command register is connected to the inputs of the second and third one-vibrators, the output of the second single-vibrator is connected to the first input of the third element OR, the output the third one-shot is connected to the first input of the fourth element OR, the output of the label of the type of micro-commands of the first register of micro-commands is connected to the inputs of the fourth and fifth one-vibration, the output is The fourth one-shot is connected to the second input of the fourth element OR, the output of the fifth one-shot is connected to the second input of the third element.  OR, the outputs of the branch label of the first and second micro-command registers are connected to the inputs of the fifth OR element, the output of which is connected to the first inputs of the third and fourth AND elements, the second input of the third AND element is connected to the inverse input of the fourth AND element, and the output of the third element And through the sixth one-shot is connected to the third input of the third element OR, the output of which through the second element of the end switch is connected to the single input of the control trigger, the zero input of which connected to the output of the third delay element ment whose input is connected to the output of a third OR gate, the outputs of the first registers of Information ra microinstructions are connected to first inputs. the blocks of elements AND of the third group, the second inputs of which are connected to the single output of the control trigger, and the outputs to the second inputs of the blocks of the elements of the OR group.  In addition, the maxiglonal nanotact selection unit contains the first one. and the second element OR, the group (ml) of elements AND-OR (t is the number of nanotacts in the microtact), the group (t-1) of elements NOT, the group m of elements AND, the inputs of the first element OR and the first inputs (ml) of elements The AND-OR units are connected to the first input of the unit, the second inputs (t-1) of the elements of the AND-OR group are connected to the outputs (t-1) of the elements of the NOT group / respectively, the output of the first. of the OR element and the outputs (ml) of the elements of the group are connected to the first inputs of the corresponding m AND elements of the group, the second inputs of which are connected to the second input of the block, the outputs of the first OR element and (w-1) elements of the AND-OR group, except the last, are connected to the inputs correspond to the hadh (t-1) elements of the NOT group, the outputs of the m elements AND the group are connected to the inputs of the second element OR, the output of which is connected to the output of the block.  FIG. 1 shows a diagram of the proposed firmware control device; in fig.  2 is a functional block diagram of the selection of the maximum nanotact.  The proposed device contains (FIG.  1) generator 1 clock pulses, counter 2, block 3 elements.  2I-OR, input 4 of the starting address, device, register 5 of the address, the first element AND b, the first decoder) 7 addresses, the first memory block 8, the first register 9.  microinstructions / decoder 10 control field -11 informational field 12, address-field 13, field 14 labels of type microcommand and field 15 of the branch label, the first one-shot 16 ,. control decoders 17, the first group of blocks 18 elements AND, the first block 19 elements OR, the third group of blocks 20 elements AND, the first group of blocks 21 elements OR, decoders 22 operation codes, the outputs 23 of the device micro-operations, the second element AND 24, the second decoder 25 wow,  the second memory block 26, the second register of 27 micro-instructions containing information field 28, address field 29, field 30 of the micro-command type label, field 31 of the branch label, first OR 32 element, first delay element 33, And second group 34 a maximum nanotact selection unit 35, a second element OR 36, a microactact trigger 37, a fifth element OR 38, a second one-shot 39, a third one-shot 40, a fourth one-shot.  4 G, fifth single vibrator 42 ,.  the input P3 of the logical conditions of the device, the third element AND 44, the fourth element AND 45, the sixth one-shot 46, the seventh one-shot 47, the fourth element OR 48, the third element OR 49, the second element 50 of the endgame, the third element 51 delay, control trigger 52.  A maximal nanotact selection unit 35 (Fig.  2) contains the first element OR 53, the group 54 (m-I) of the elements AND-OR (t is the number of nano-tacts in the micro-tact), the group of elements NOT 55, the group 56 of elements AND, the second element OR 57.  The firmware control device operates as follows.  Each device microtoact consists of nanotacts,.  In the initial state, all the elements of the memory are in the zero state, the address of the initial one-step microcommand of the microprogram is recorded in the address registrar 5 through the input 4 of the device.  Simultaneously with the recording of the address of the first microcommand, the signal from the input 4 of the device through the second element OR 36 sets the trigger for triggering the clock state to one and prepares the second element AND 24 for allowing the reading of the one-time microtactic address through the second decoder 25.  the mandala recorded in the second block 26, First Clock, a pulse coming from the output of the decoder 10 through the second element AND 24 to the synchronous input of the second decoder 25 of the address, allows the reading of the first one-cycle micro-command from the second block 26 to the second register 23 of the micro-instructions.  In the field x 28 recorded codes of single-ended microcoma. ndy, which through the second group of blocks 34 of the elements of AND, and through the second block of 21 elements OR arrive at the inputs of the corresponding decoders 22 opcodes.  The signal from the single output of the trigger 37 for generating the clock through the first single-oscillator 16 activating fields 11 of the first register of 9 micro-instructions is zeroed.  The zero codes of the control fields 11 arrive at the inputs of the control decoders 17, the first outputs of which are excited and through the first group of blocks 18 of the elements AND the first block of 19 elements OR arrive at the synchronization inputs of the decoders 22 operation codes, the inputs of which receive the micro-operation codes of the first micro-command.  At the outputs 23 of the decoders 22, signals of the corresponding microoperations appear.  After issuing a single-ended microcommand, the signals from the outputs of the block 34 of the elements are transferred to the inputs of the second element OR 36, the signal from the output of which sets the formation trigger 37 to a single state, thereby allowing the reading of the next microcommand.  In addition to the operating parts in the field 28 of the second register of 27 micro-commands, the address of the next micro-command (single-ended or multi-tact) is recorded in the field 29.  In field 30 of the micro-command type label, the sign M is recorded, and.  1, if the next microgoom is yes; O, if the following micro-codename is single-ended, In field 31 of the branch label, sign B is recorded, and fl, if the given microinstruction is in. It is a microcommand about branch otherwise.  Suppose that the next micro-coded microprogram is many steps per micro-command.  R.  In this case, a single signal from the output of the field 30 of a microcommand type label through the third one-shot 40, the fourth element OR 48, and the second delay element 50 arrive at the single input of the control trigger 52 and throws it into the one state.  The second delay element 50 is necessary for delaying the transfer of the control trigger 52 for the time required to rewrite the address of the next microcommand from the address, field 29 of the second microcommand register 27 through block 3 of the elements 2I-OR to address register 5.  The signal from the single output of the control trigger 52 through the first element B comes to the synchronization input of the first decoder 7, thereby allowing the reading of the I TOK command recorded in the first storage unit 8 at the register address 5. Simultaneously with the reading of the multi-tact micro-command, the signal from the synchronous input of the first decoder 7 the address through the first element OR 32 and the first delay element 33 arrives at the zero input of the trigger formation 37 and switches it to the zero state.  The first delay element 33 is necessary to realize the possibility of transferring information from blocks 8 and 26 to registers 9 and 27. Transferring the trigger 37 to forming the clock state to the zero state shows that the next micro tact has started and prohibits reading of the new micro command written to. register 5 ashres.  A read-only multi-instruction micro-instruction is recorded in the second register of 9 micro-instructions, on the information fields of which the control and operational parts of the micro-command are written.  At the same time, codes of numbers of nano-tacts in which the corresponding micro-operation should be performed, codes of which are written in operating fields 12, Tact code-in which operational information is to be read from field 12, are received from the field are written in the control fields x11. 11 of the first register of 9 microinstructions per control decoder 17.  One of the outputs of the control decoder 17, corresponding to the micro-operation code for the microprocessor in this one: the nanotact is excited.  The signal from the output of the decoder 17 through the element AND of the first group of blocks of elements AND and the element OR of the first block, 19 elements OR enters the synchronous input of the decoder 22.  The operation: on the part of the microoperations of the given nanotact enters through the block 20 of the elements AND and the block 21 of the elements OR to the input of the decoder 22 of the operation code.  At the output of the decoder 22, a signal of the corresponding micro-operation appears.  Similarly, in the corresponding nano-tact, information is read from each of the outputs of the operating fields 12 to the registers of 9 micro-instructions.  The address of the next microcommand from the output of the floor 13 through the block 3 of the elements 2И-OR enters the register 5 of the address.  If the next micro-command is multi-tact, the signal from the output of the M field of the micro-command type label is through the fourth one-shot 41, the fourth OR 48 and the second delay element 50 to the single input of control trigger 52. If the next micro-command is single-ended, the signal from the output of the M field of the micro-command type label is through the fifth one-shot 42, the third element OR 49 and the third delay element 51 arrive at the zero input of the trigger 52 and transfer it to the zero state, thus preparing the circuit for operation With a single-cycle micro-command. When the device is operated with a multi-micro micro-command, the signals from the outputs of the control decoder 17 arrive at the input of the maximum nano-cycle extraction unit 35.  At the same time, the first element OR 53 receives signals from the outputs of the decoder 17, corresponding to the codes of the maxima of the nanotacts in which the corresponding microoperations are performed.  If there is at least one microoperation in the multi-tact microcommand performed in the last nano-cycle, the corresponding output of the control decoder 17 Chiu is the signal.  This signal arrives at one of the inputs of the first element OR 53 and after the clock pulse from the decoder 10 is supplied, passes through the element AND 56, the second element OR 57 of the block 35 and through the second element OR 36 to the single input of the trigger 37 for generating the clock, throwing it in a single state.  The occurrence of a signal at the unit output of the trigger 37 for the formation of a clock indicates the end of the execution of this microtact and allows through the first AND 6 element or the second AND 24 element to read the next microcommand whose address is written in the address register 5.  If there are no control information in the n-th nano-shock, the signal from the output of the NOT element 55 prepares for the interrogation the first element (t-1) AND-OR 54 which receives signals from the outputs of the control decoders corresponding to the (t-1) -th nano-stroke .  (go-1} th clock pulse polls this nanotact.  If there is control information for this nanotact, a micro tact end signal is generated at that nanotact.  If there is no control information in the (t-1) -nm nano-tact, then all the remaining nano-tacts with control information are sequentially polled.  Thus, the micro-tact end signal is generated for the maximum nano-tact, which contains the control information recorded in the operating fields 12 of the first register 9 microcommands.  If the next micro-command (one tact or multi-tact) is a branch micro-command, by the corresponding. The exit of the branching field 15 Il 31, a signal appears, which through the fifth element OR. 38 enters the inputs of the third and fourth elements And 44 and 45.  Depending on the logic conditions input to the device input 43, the control trigger 52 is set to a particular state.  At the same time, the recognition of logical conditions is formed as follows: GI, if the next microman 1 yes is multi-tact; | 0 if the next microcoman; and is one-touch.  After that, with the arrival of the next signal of the first nanotact, the device functions similarly to that described.  The use of the proposed microprogram control unit will allow increasing the speed with respect to the prototype by 20%.  Claim 1.  A firmware control device containing the address register, clock generator, counter, decoder, serially connected first address decoder, first memory block and first microcommand register, serially connected second decoder, second block, memory and second microcommand register, OR element block, the first and second groups of blocks of elements.  And, a group of blocks of elements OR, a block of elements 2И-OR, p decoders of operation codes, a control trigger, with the output of the address register connected to the information inputs of the first and second decoders of the address, the control outputs of the first register of microinstructions connected to the information inputs of the control. decoders, respectively, the outputs of which are connected to the first inputs of blocks of elements And the first group, the second inputs of which are connected to the output of the decoder, information; the input of which is connected to the output of the counter, the counting input of which is connected to the output of the clock generator and controlled to the decoder input of the decoder, the outputs of the element blocks of the first group through the block of elements OR are connected to the synchronization inputs of the decoders of the operation codes, respectively, the operating outputs of the second microcommand register are connected to the first the inputs of the blocks of elements And the second group, the second inputs of which are connected to the zero output of the control trigger, the outputs of the blocks.  elements of the second group are connected to the first inputs of the blocks of the elements of the OR group, the outputs of which are connected respectively to the information inputs of the decoder operation codes, the outputs of which are connected to the output of the device microoperations, which are u. in order to increase speed, it additionally contains a third group of blocks of elements And, the first, second, third and fourth elements And, the first, second, third ,. the fourth and fifth elements OR, the first. , second and third delay elements, first, second, third, fourth, fifth, sixth and seventh one-shot, maximum nanotact selection unit, micro-tact formation trigger, with the first input of the first element I connected to the unit output 4 of the control trigger And the first input of the second element And connected to the zero output of the control trigger; the second inputs of the first and second elements I are connected to. single trigger output.  forming microtoacts and through the first one-shot one connected to the zeroing input of the control bits of the microinstruction register, whose address output is connected to the first input of the first group of inputs of the 2I-OR block, the second input of the first group of inputs is connected to the single output of the control trigger, the zero output of which connected to the first input of the second group of input blocks of the 2Y-OR elements, the second input of the second group of inputs of which is connected to the address output of the second register of microcommands, and the code to the first information input m of the address register, the second information input of which is connected to the input of the initial address of the device, the third inputs of the first and second And elements are connected with. the output of the decoder, the outputs of the first and second elements And are connected to the syncrunner inputs of the first and second address decoders and with the first and second inputs of the first. .  element OR, respectively, the output of the "first element OR" through the first delay element is connected to the zero input of the trigger for the formation of a micro-tact, one. The primary input of which is connected to the output of the second OR element, the first input of which is connected to the –outputs of the AND block of the second group, the second input to the output of the selection block of the maximum nanotact, the first input of which is connected to the outputs of the control decoders,.  the second input is with the output of the decoder.  the third input of the second element OR is connected to the input of the initial address of the device, -, the output of a micro-command tag of the second register of micro-instructions is connected to the inputs of the second and third one-vibrators, the output of the second one-vibrator is connected to the first input of the third element OR, the output of the third one-vibrator is connected to the first input the fourth element OR, the output of the label of the microcommand type of the first register of microcommands is connected to the inputs of the fourth and fifth vibrators; the output of the fourth one-shot is connected to the second input of the fourth store ementa OR, the output of the fifth monostable coupled to a second input of the third OR gate, the outputs of the first label and second branching microinstruction register connected to the first and second.  entrances. the fifth OR element whose output is connected to the first inputs of the third and fourth elements AND, the second input of the third element H is connected to the inverse of the fourth element AND and connected to the input of the logical conditions of the device, the output of the third element AND is connected to the third input of the third element OR , the output of the fourth element AND through the seventh one-shot is connected to the third input of the fourth element OR, the output of which through the second delay element is connected to the single input of the control trigger, zero second input coupled to an output of the third element zaderzh1 and having an input connected to the output of the third OR gate, in. the formation outputs of the first register of micro-commands are connected to the first inputs of the blocks of elements AND of the third group, the second inputs of which are connected to the unit output of the control trigger, and the outputs to the second inputs of blocks of the elements of the OR group, 2.  The device according to claim.  1, differs from the fact that the block of maximum nanotacta contains the first and second elements OR, the group (p-1) of the elements AND-OR (rrj is the number of nano-tacts in the micro-tact), the group (Gp-1) of the elements NOT / group fri elements AND, the inputs of the first element OR and the first inputs (in-l) of the elements AND-OR are connected to the first input of the block, the second inputs (n) of the elements AND-OR are connected to the outputs (t-1) of the elements NOT groups, respectively , the output of the first element OR and the outputs (t-1) of the elements AND-OR groups are connected respectively with the first input-.  m m elements AND groups, the second inputs of which are connected to the second input of the block, the outputs of the first element OR, and (tt1-1) elements of the AND-OR group, except the last, are connected to the inputs (t-1) of the elements NOT groups, respectively, the outputs of the AND elements Groups are connected to the inputs of the second element OR, the output of which is connected to the output of the block.  Sources of information taken into account during the examination 1. - USSR author's certificate number 467351, cl.  G 06 F 9/22, 1972.   2. USSR author's certificate according to the application No. 2765918 / 18-24, cl. G 06 F 9/22, 1970 (prototype). k