SU1128258A1 - Device for checking execution of sequence of commands of operator - Google Patents

Abstract

A DEVICE FOR THE CONTROL OF THE PERFORMANCE OF THE SEQUENCE OF OPERATOR'S ACTIONS, containing an indication unit, a group of elements NOT, two. groups of elements AND-NOT and the first corpse., PU triggers, and the inputs of the elements NOT groups are informational inputs of the device, the outputs of the elements NOT groups are connected to the first inputs of the corresponding elements AND-NOT the first group, the inputs of the display unit are connected to direct the outputs of the corresponding triggers of the first group, the zero inputs of which are combined and are the installation input of the device, are those that, in order to increase the reliability of the control, are entered into it, the memory block, the encoder, the group shapers single impulses 1.; ow, second trigger group, two OR elements, delay element and blocking node that contains an OR element, Pi-HE element and a group of AND elements, with the direct outputs of the first group of trigger elements connected to the corresponding inputs of the block OR element , the output of the OR element is connected to the first input of the NAND element, the output of which is connected to the first inputs of the elements and the group, the second inputs of which are combined with the inputs of the corresponding elements of the group, the outputs of the elements AND groups are the outputs of the blocking node and connected to the inputs of the corresponding shapers of single pulses of the group, the forward outputs of which are connected to the group of information inputs of the encoder and the corresponding inputs of the first OR element, the output of which is connected to the synchronization input of the encoder and the input of the delay element whose output is connected to the first inputs of all AND elements NOT the second from the group, the outputs of which are connected to the single and the inputs of the corresponding slots of the first group of triggers with single inputs of the corresponding triggers of the second group and inputs of the second OR element, the output of which is connected to the second inputs of all AND-NOT elements of the first group, the outputs of which are connected to the first-zero inputs of the corresponding trigger of the second group, the inverse outputs of which are connected With the second inputs of the corresponding elements AND-NOT of the second group, the third inputs of which are assembled with the corresponding information outputs of the block, the address input of which is connected to the output of the encoder, The second input of which is connected to the second zero inputs of all the triggers of the second group and the installation input of the device, the second input of the NAND element is the device start input,.

Description

The invention relates to automation and computing and can be used to create an operator control system at the control panels of automated control systems. A device is known to control the execution of the sequence of actions of the operator’s VIY, containing the group of the OR elements and the group of triggers ClD. . However, this device does not provide in full Quality Measurement and Control, as it records only the fact of the sequence violation at the current time, and not the place of its manifestation. It is possible to control only a strictly specified sequence. The closest to the invention to the technical essence is a device for monitoring the execution of a sequence of operator actions, comprising a data code block, an indication block, a group of elements, NOT two groups of NAND elements, and a group of flip-flops, with the first information. The online output of the data input unit is connected to the input of the first element of the NOT group, the nth output of the data input unit is connected to the first input of the nth element of the NAND of the first group, each i -and information output of the input block and data is connected to the input of the i -th the element of the group and the first input of the i-1 / -th element of the AND-NOT of the first group (h-1) /, the outputs of the elements of the NOT group are connected to the second inputs of the corresponding elements AND are NOT the first group whose outputs are combined with single inputs of the corresponding group triggers, the first inputs of the corresponding elements And - NOT the second group and the first group of inputs of the display unit, the second group of inputs of which are connected to the outputs of the IS-NOT elements of the second group whose second inputs are connected to the outputs ... of the corresponding group triggers, - the zero inputs of which are combined and - connected to the output of the initial The first settings of the C 2 data entry unit However, the known device does not allow controlling the execution. arbitrarily given sequence of operations. The purpose of the invention is to increase the reliability of the control. The goal is achieved by the fact that the device for monitoring the execution of the operator's sequence of actions, containing the display unit., A group of elements NOT, two groups of elements AND-NOT and the first group of triggers, the inputs of the elements of NOT groups are information inputs of the device, the outputs elements NOT groups are connected to the first input. The corresponding elements of the IS-NOT of the first group, the inputs of the display unit are connected to the direct outputs of the corresponding triggers of the first group, the zero inputs of which are combined and are the installation input of the device, a memory block, an encoder, a group of single pulse drivers, the second group of trigger points, two elements are entered OR, a delay element and a blocking node that contains an OR element, an AND-NOT element and a group of AND elements, the outputs of the first group triggers connected to the corresponding inputs of the OR element of the blocking node, the output of which is connected to the first input of the NAND element, the output of which is connected to the first inputs of all elements AND groups, the second inputs of which are combined with the inputs of the corresponding elements NOT groups of the outputs of elements AND of the group are output wells of the blocking and connected to the start inputs of the corresponding drivers of single pulses groups, direct outputs, which are connected to the group of information inputs of the encoder and the corresponding inputs of the first OR element, the output of which is connected to the synchronization input of the encoder and input the home of the delay element whose output is connected to the first inputs of all the NAND elements of the second group, the outputs of which are connected to the single inputs of the corresponding triggers of the first group, the inverse outputs of the shapers of the single group pulses are connected to the single inputs of the corresponding triggers of the second group and the inputs of the second OR element, the output of which is connected to the second inputs of all the elements of the IS-NOT of the first group, the outputs of which are soy: Dinenas with the first zero inputs of the corresponding triggers of the second group, inverse you the strokes of which are connected to the second inputs of the corresponding IS-NOT elements of the second group, the third inputs of which are connected to the corresponding information outputs of the memory block, whose address input is connected to the output of the encoder, the installation rotor of which is connected to the second zero inputs of all triggers of the second group and the installation input of the device The second input of the AND element is NOT a device start input. FIG. 1 shows a functional block diagram of a device for monitoring the execution of an operator’s sequence of actions; in fig. 2 - the same. node lock; in fig. 3 - the same Formed ate single pulses; in fig. 4 is an encoder; FIG. 5 is an embodiment of a memory block. The device for controlling the execution of the operator's sequence of actions (Fig, 1) contains a blocking unit 1, a delay element 2, a first group of triggers 3-8, an indication unit 9, a group of formers 10-15 single pulses, an encoder 16, a group 17 outputs of the device, the second group of flip-flops 18-23, the second group of elements AND-NOT 24-29, the first group of elements AND-NOT 30-35, the group of elements NOT 36-41, memory block 42, elements OR 43 and 44, Block 45 data entry is connected to the device. Interlock unit 1 (FIG. 2) contains a group of elements AND 46-51, element OR 52, element I-HE 53, Shaper of single pulses (FIG. 3) contains 3-K triggers 54 and 55 and element 56 of delay. The output of the trigger 54 is connected to the direct output of the driver, the output of the delay element 56 is with the inverse output. The encoder (FIG. 4) contains the encoder element 57, the elements 58-60 and the triggers 61-63, the operator control actions program in block 42 recorded in such a way that the address corresponding to a particular control of data entry block 45 causes, at the output of memory block 42, a information word defining those controls with which the operations immediately preceding the operation should be performed. RGANI, B cell memory unit 42 with the address 001 is recorded in the zero information layer ;, into- cell with address 010 in -.CH. The 1st bit (memory block 42 has six bits), in the cell with the saddle 011-1 in the 1st and 2nd bit, in the cell with the address 100 is written in the 3rd bit and d, d , (fig, 5),. The device operates as follows. By the signal from the control output of the data input unit 45, all the device triggers are set to zero (initial) state. There are no signals on the remaining outputs of the data entry unit 45, which corresponds to the logic level O. There are also logic levels on all outputs and inputs of block 1, Signals from the outputs of all drivers 10-15 single pulses correspond to the logic level O, I. . The correct sequence of operations is characterized by the arrival at the information inputs of the formers of 10–15 logical levels. positive pulses according to the presence of units in memory block 42. The indicated state of the memory block 42 corresponds to the following sequence of operations: 1; - the logic level H arrives at the input of the start of the spinner 10; 2 - a positive pulse (for example, from the push-button switch of the data entry unit 45) is fed to the input of the imaging unit 11; 3 - the logic level O arrives at the input of the imaging unit 10; Next, the following operations are successively performed: 4 - a positive pulse arrives at the input of the imaging technology 12; 5-positive pulse is fed to the input of the imaging unit 13; 6 - a positive impulse is fed to the input of the shaper 14; 7 - a positive impulse arrives at the input of the imaging unit 15. When the information input of the imaging unit 10 is received at the logical level H, a single impulse is generated at its forward output, which then enters the information input of the encoder 16, the output of which is. A pulse code 001 appears. It arrives at the address input of the memory block 42. Logic O levels corresponding to the zero state of the outputs of the memory block 42 close the AND-NOT elements 24-29, preventing the gating signal from arriving. from the output of delay element 2, change their state. The delayed single pulse from the inverter output of the driver 10 sets the trigger 18 to a single state, the logic level O from the inverse output of this trigger confirms the single state of the AND-24 element even with a strobe signal, the positive pulse corresponding to the second operation, from the input of the data input unit 45 to the input of the imaging unit 11 through the blocking node 1, as a result, the input unit 42tami receives the code 010, and the output generates the word 000001, the trigger 19 is set to one position e, the NE-NE element 25 is closed by a signal from the inverse output of this trigger. When performing the third operation, the signal level at the first output of the block 45 data entry. . reduced to the logical level O,,. . As a result of performing the fourth operation / (with the third by the number of the control unit of the data input unit 2) at the output of the memory unit 42. word 000011 is formed, with the elements AND-NO 24 and 25 remaining in one state and upon receipt of the gating signal, as well as being closed by logical levels from the outputs of the flip-flops 18 and 19; after the arrival of the delayed single pulse from the inverted output of the former 12, the trigger 20 is set to one state, and the triggers 18 and 19 are returned to the initial (zero) state by a signal received from the output of the second element OR 43 through the elements AND 30 and 31 , in the presence of a logic level H at the outputs of the HE elements 36 and 37, the zero input of the trigger 20 does not receive the logic zero level, since at the moment the second input of the AND-NE element 31 signal from the output of the second element OR 43 its first input arrives logic level th zero with NOT element 38, at whose input is present a logic level 1 (positive pulse) caused by the connection of the control unit of the third body 45 number of data input. When a pulse corresponding to the fifth operation arrives at the input of the imaging unit 13, the information word 000100 is formed at the output of the memory block 42 via address code 100 and a logic level appears at the third input of the AND-NE element 26, the gating signal passing after this does not change The state of the element IS-NE 26 and the trigger 5, since this element is currently closed by the logic level O, passing from the inverse output of the trigger 20, which is set to one when it is executed. The SRI of the fourth operation. The specified trigger is reset by the signal from the output of the second element OR 43, while simultaneously delayed by the signal of the synchronous output of the driver 13 is set to the one state trigger 21 .. The device operates in a similar way when the levels of the logical M are received from the outputs of the input block 45 when performing other sequential operations . During operation, the operator may make a mistake by skipping one or several operations, thereby violating the sequence of their execution,; and with further work only part of previously missed operations. To control the ERR and the possibility of their analysis by the instructor. Or .. by the operator after the end of the cycle of operations, information is needed on the operations performed after skipping one or several operations. It is important when training the operator that the program can be stored in the memory unit 42 to control the execution of an arbitrarily specified sequence of operations. Consider the operation of a device with a sequence of operations, characterized by successive operations 1, 2, 3, b, 7 and 5.. Sequential execution of the first three operations does not lead to the appearance at the outputs of the AND-NE 24 elements to 25 and the triggers 3 and; 4 error signals. Performing the sixth operation (switching the fifth control element of the data entry unit 45) immediately after the third violates the sequence of operations. In this case, the address word 101 at the output of memory block 42 generates the information word 001000, and the signal corresponding to the logic (4th bit) is fed to the third input of the AND-27 element, and its second input receives the logic level from the inverse trigger output 21, and when a gating signal from the output of the delay element 2 is received at the first input of the NAND 27 element, an error signal is generated at the output of the NAND element 27, which triggers the trigger b into one state, the trigger 22 goes over and the unit state along the delayed signal with inverse the output of the driver 14. The seventh operation after the sixth does not lead to the appearance of an error signal at the output of the NAND 28 element and the trigger 7. The fifth operation (switching the fourth control of the data input unit 45) is characterized by a positive pulse entering the generator 13 while the code 000100 appears at the output of the Memory block 42, the logic level 1 from the third bit of the memory block 42 enters the third input of the AND-NOT element 26, the logic input from the trigger 20 arrives at its second input, uyuschy violation in a sequence of performing fifth operations. As a result, when the gating signal arrives at the first input of the NAND 26 element, it changes its value. the state is similar to trigger 5, which corresponds to the error fixation. From the outputs of the flip-flops 3-8, error signals are sent to the display unit 9, by means of which they are displayed as special characters. When povleniya on the blocking output block 7 input. Data levels lotinezskoy. . The first. Same error signal in the form of a logical level. . With the output of one of the triggers 3-8, the unit state of the AND-HE unit 53 of the interlock block 1 (FIG. 2) goes to zero, the logic level O arrives at the inputs of the And blocks 46-51 and prohibits the input of signals from the control units 45. Data input to the formers -10-15 and the outputs 17 of the device. The implementation of the proposed device provides a quick change (rewriting) of programs for carrying out a sequence of operations, which makes it possible to control the execution of an arbitrarily specified sequence of operations, as well as provides for blocking signals from controls when an error signal is present, memorizing an error and preventing an operator from erroneous operation. performing operations that are erroneous.

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Claims (1)

DEVICE FOR CONTROL 'PERFORMANCE OF THE DIST- SEQUENCE VIY OPERATOR, containing the unit of indication, a group of elements NOT, two. · Groups of elements AND NOT and the first corpse .. of triggers, and the inputs of elements NOT groups are information inputs of the device, the outputs of elements NOT groups are connected to the first inputs of the corresponding elements AND -NOT the first group, the inputs of the display unit are connected to the direct outputs of the corresponding triggers of the first group, the zero inputs of which are combined and are the installation input of the device, which is necessary to increase the reliability of control,a memory block, an encoder, a group of formers of single pulses, a second group of triggers, two OR elements, a delay element and a blocking unit that contains an OR element, an NAND element and a group of AND elements are inserted into it, and the direct outputs of the triggers of the first group are connected to the corresponding inputs of the 'OR element of the blocking node, the output of the OR element is connected to the first input of the AND-NOT element, the output of which is connected to the first inputs of the AND elements of the group, the second inputs of which are combined with the inputs of the corresponding elements of the NOT group The odes of the AND elements of the group are outputs of the blocking unit and are connected to the start inputs of the corresponding single pulse generators of the group, the direct outputs of which are connected to the group of information inputs of the encoder and the corresponding inputs of the first OR element, the output of which is connected to the synchronization input of the encoder and the input of the delay element, the output of which is connected with the first inputs of all AND-NOT elements of the second group, the outputs of which are connected to the single inputs of the corresponding triggers of the first group, inverse outputs the single pulses of the group are connected to the unit inputs of the corresponding triggers of the second group and the inputs of the second OR element, the output of which is connected to the * second inputs of all the AND elements of the first group, the outputs of which are connected to the first-zero inputs corresponding triggers of the second group, the inverse outputs of which are connected to the second inputs of the * corresponding elements AND NOT of the second- 'group, the third inputs of which are · connected to the corresponding information outputs, of the memory unit, the address input of which connected to the output of the encoder, the mounting input coupled to the second inputs of all triggers zero second group 'and mounting input device, the second input of AND-NO element is an input device startup. . i