SU674072A1 - Simplex information transmitting-receiving apparatus - Google Patents

Description

(54) SIMPLE DEVICE FOR RECEPTION AND TRANSMISSION OF INFORMATION

Connected to the fourth input of the parity block.

The drawing shows a block diagram of the device.

The receiving-transmitting device contains the shift register 1, the control unit 2, the parity check block 3, 5, the block of elements AND 4, the element AND 5, the switch b.

The parity check block 3 executes the parity check function of the received code and provides the parity of 10 code transmitted to the communication line, regardless of the information code on the set inputs of the transmitted information.

The block of elements And 4 is not an information translator; The received 15 information is recorded in the shift register 1 itself and can be output to the addressee in a forward or reverse code from the register cells 1p - n + 1p. The block of elements 4 and 4 determines such a 20 state of shift register 1, when zero levels are set in all its cells, the signals are removed from the zero positions of the cells of shift register 1. Thus, the block of elements 4 25 compares the state of cells of shift register 1.

The device operates in such a way that, at the end of the full cycle of operation, it always returns to the initial state. In this case, the parity check unit 3 and all bits of shift register 1, except for the first one, are set by the signal from output 7 to the zero state, and the first register bit .. is set by the signal from output 8 to one state.

If there is a transmitted information in the communication line - in the absence of its own transmission cycle, the information sequence of 40 pulses is at input 9, and the corresponding sequence of clock pulses of shift is at input 10. In this case, the control unit 2 unlocks the shift register 1 and 45 and the parity check unit 3 simultaneously blocks itself with signals from outputs 7, 8, excluding the possibility of switching the device on to transfer. From the control unit 2 to the shift register 1, the shift pulses from output 11 are received, synchronous with the input pulses from output 8. The pulses ensure that the information 55 of the code sequence from the input of the device 9 is input into p; subsequent bits. Upon receipt of n + 1 clock pulses from output 11, in n + 2p, the shift register register 1 is set to 60, and the control unit 2 receives a signal from output 12 about the end of reception.

Upon termination in the communication line of the clock sequence of pulses of the signal 65

The control unit 2 is unlocked with the device 10, depending on the content of the received information, the presence or absence of a fault in the received sequence, the control unit 2 will either return the device to its original state or accept it in the transfer mode.

When the device is switched into the transfer mode, the control unit 2 by the signal from output 8 sets the first bit 1p of shift register 1 to one state, overwrites the information from the information source to the input of device 13 into information

2p

n + 1p

bits

register

the shift 1 unlocks the switch 6 by the signal from output 14. After that, the shift register 1 receives the shift clock from output 11, which provides the information code sequence from output 15 and the corresponding sequence of clock pulses from output 16 to the communication line /.

Preliminary recording in the first, 1p shift register of 1 logical unit during transmission provides the ability to use shift register 1 not only as an information converter, but also as a timing device for determining the moments of interrogation of the parity check unit 3 and the end of transmission of the code sequence. The polling signal from the output 17 of the parity control unit 3 is indicated by the block of elements 4 and 4 when switching to the zero state in the first bits of the register, and the signal from output 18 ends with the transmission of element 5 from the transition to the zero state of all bits of shift register 1.

The identification of the various transmission cycle times is provided by pre-setting the unit state of the first bit of shift register 1.

The signal from output 18 ends with the transmission to control unit 2 and ensures that the device returns to its original state.

The system eliminates the need to use any special timing device, for example, a clock counter ensuring the cyclical operation of the device.

Claims (2)

1.Tutevich V.Ya. Telemechanics. M., Energie, 1973, p. 359. 2. Il'in V.A. Telecontrol and telemetry M., Energie, 1974, 5 s. 250-257.