JPS6322502B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmitting/receiving device, and an object of the present invention is to enable data processed in a receiving device to be checked and read out in a transmitting device, and to enable all data processed in a receiving device to be read out in a transmitting device. It is an object of the present invention to provide a data transmitting/receiving device which can simplify the configuration of the receiving device and easily achieve so-called energy saving by burdening the control function of the receiving device. below,
The present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention,
It basically consists of a transmitting device 1 and a receiving device 2. Thus, the transmitting device 1 mainly includes a shift register 4 that converts parallel transmitted data 3 into serial data, and
An encoder 5 combines the output from the shift register 4 with a clock signal and a control signal, modulates it into a predetermined pulse width, and sends a predetermined pulse signal to the receiver 2 via an output circuit 6 such as a buffer. and a decoder 17 that decodes the signal sent from the receiving device 2 via the input circuit 16 after being subjected to predetermined processing in the receiving device 2.
It consists of a shift register 18 that converts the signal from this decoder 17 into parallel, and a latch circuit 19 that latches the signal from this shift register 18.

On the other hand, the receiving device 2 mainly uses the transmitting device 1.
The output pulses from the encoder 5 are sent to the output circuit 6,
A monomulti 9 which is applied to the input terminal (T input end) via the input circuit 7 and operates on the rising edge of the monomulti 9, and an inverted output (output) of this monomulti 9 and the input of the monomulti 9 via the delay circuit 8 are added. gate 10, and the output of gate 10 is connected to delay circuit 1.
1 to the reset input terminal (R input terminal), and input the monomulti 9 output (Q output) as a shift pulse to the clock input terminal (CK input terminal), and The output is given to the data input terminal (D input terminal) and the parallel/shift control input terminal (P/S input terminal), and the shift register 14 assembles the received data, and the latch control input terminal (LE input terminal) from the shift register 12. It consists of a latch circuit 13 that latches a signal from a shift register 14 in response to a signal applied to the shift register 14, and an output circuit 15 that sends the data in the latch circuit 13 to the transmitter 1 side via the shift register 14.

Next, the operation of the data transmitting/receiving apparatus according to the present invention configured as described above will be described in detail with reference to FIG.

First, in the transmitter 1, transmission data 3 is taken in parallel to a shift register 4 and output in series. The encoder 5 pulse width modulates the serial output signal of the shift register 4 into a clock signal and a data signal, respectively, as shown in FIG. 2a. In other words, the clock signal is a long pulse with a long pulse width, and is generated every other bit time in a number corresponding to the number of bits of the transmitted data 3. On the other hand, the data signal is a long pulse that corresponds to the number of bits of the transmitted data 3. It precedes the clock signal and is represented by a short pulse with a pulse width, thereby forming a data stream signal. When the encoder 5 finishes transmitting the data signal, it continues to output a short pulse control signal and a long pulse read clock signal in accordance with the number of bits of the transmission data 3.

The serial output signal of the encoder 5 is transmitted to the input circuit 7 of the receiver 2 via the output circuit 6. Monomulti 9 is triggered at every rising edge of the input pulse,
The output pulse width is set to an intermediate value between the long pulse and short pulse of the encoder 5 output. Therefore, the output signal of the monomulti 9 becomes as shown in FIG. 2b. On the other hand, the inverted output terminal of the monomulti 9 is connected to one input terminal of a gate 10, and this gate 10 receives the input signal of the monomulti 9 via the delay circuit 8 as its other input, and At the falling edge of the output signal, it is determined whether the input signal of the monomulti 9 is still continuing, and when this input signal is continuing (long pulse), it is output, and when it is not continuing ( (short pulse), no output occurs. The output waveform of this gate 10 is as shown in FIG. 2c.

In the shift register 12, data "1" at the D input is shifted to the upper digit every time the monomulti 9 output rises, and is reset when the gate 10 output, that is, a long pulse is detected. Therefore, at the moment of rise of the gate 10 output, the output digit corresponds to the number of short pulses received before the long pulse.
The output of the shift register 12 is at the "1" level. This situation is shown in FIGS. 2d and 2e. Since the received and decoded data signal is set in the second digit output _Q2 of the shift register 12, this output is sent to the input terminal of the shift register 14 to assemble the received data. When the reception of all bit information of the data signal is completed, the shift register 12 is
The output _Q4 of is set, and the received data of the shift register ₁₄ is transferred to the latch circuit 13 at the rising edge of Q4.

Note that f and g in FIG. 2 are the waveforms of the shift register 12 outputs Q ₃ and Q ₄ , respectively.

In this way, the transmission data 3 of the transmitting device 1 is transmitted to the latch circuit 13 of the receiving device 2.

Then, with the first bit of the read clock signal, the data stored in the latch circuit 13 is transferred again to the shift register 14 via its output terminal DO. Thereafter, this data shown in FIG. 2h is synchronized with the read clock signal and serially transmitted from the output terminal SO to the decoder 17 through the output circuit 15 and the input circuit 16 on the receiving device 2 side.
The decoder 17 decodes this data and sends it to the shift register 18, and transfers it to the latch circuit 19 when all answered data is available. The contents of the data sent to this latch circuit 19 are displayed on a display circuit (not shown) such as a multi-digit display LED, and this and the above-mentioned transmission data 3 are displayed.
By comparing the above, the transmitting device 1 can easily check whether the data transmitting/receiving device according to the present invention has operated normally.

Note that the delay circuits 8 and 11 in the figure are for preventing malfunctions due to the operation delay time of the monomulti 9 and the shift register 14, respectively.

According to the present invention configured as described above, data to be transmitted is pulse width modulated into a data signal,
Furthermore, the transmitting device 1 includes an encoder 5 that outputs a control signal and a read clock signal, and controls the receiving operation of the receiving device 2 by the output signal of the encoder 5, and also reads out the contents of the received data and outputs a clock signal. By reading it out on the transmitting device 1 side and displaying it, it is possible to check the transmitted data 3 and the received data, and easily check whether the transmitted data 3 has been transmitted and received correctly. be able to. Further, in this case, since the receiving device 2 does not require a special control device or the like, the configuration of the receiving device 2 can be simplified.

If the various logic circuit elements of the receiver 2 are made of, for example, CMOS integrated circuits with low power consumption, and the pulse train of the receiver 2 is rectified by a bridge rectifier circuit or the like and then smoothed to form a rectified power supply, this rectified power supply This can be used as a power source for driving the logic circuit element, and the receiving device 2 can be miniaturized by eliminating the need for an external power source.

Furthermore, the rectified power supply allows the content of received data to be stored for a short time.

In the above embodiment, for convenience of explanation, it is assumed that the number of bits of the transmission data 3 and the control signal are both 4 bits.
By increasing the number of bits 2 and 14, it is possible to arbitrarily increase the number of 3 bits of transmission data, and furthermore, by increasing the number of bits of the control signal, the control contents can be varied, Substantially the same effect can be expected with this as well.

Furthermore, as an application of the present invention, in a time limit mechanism that sets a time limit from the outside using a time limit setting device, the transmitting device 1 according to the present invention is used as the time limit setting device, and the latch of the receiving device 2 according to the present invention is used in the time limit mechanism. By replacing the circuit 13 with a preset counter, it is possible to form a timer that can easily store set values.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a timing chart showing the operation. 1... Transmitting device, 2... Receiving device, 3... Transmitting data, 4... Shift register, 5... Encoder, 6... Output circuit, 7... Input circuit, 8... Delay circuit, 9... Monomulti, 10...Gate, 11...Delay circuit, 12...Shift register, 13...Latch circuit, 14...Shift register, 15...Output circuit, 16...Input circuit, 1
7...Decoder, 18...Shift register, 19
...Latch circuit.

Claims (1)

[Claims] 1. In a data transmitting/receiving device configured to transmit data from a transmitting device 1 to a receiving device 2 and returning data received by the receiving device 2 to the transmitting device 1, the transmitting device 1 converts parallel transmitted data 3 into serial data. First shift register 4 converting into data
an encoder 5 that combines the output of the first shift register 4 with a clock signal and a control signal to perform pulse width modulation; and a first encoder 5 that buffers the output of the encoder 5 and sends it to the receiver 2.
an output circuit 6, a first input circuit 16 that receives return data from the receiving device 2, a decoder 17 that demodulates data from the output of the first input circuit 16, and a parallel It consists of a second shift register 18 that converts into data and a first latch circuit 19 that holds the output of the second shift register 18.
is a second input circuit 7 that receives the signal from the transmitter 1, a first delay circuit 8 to which the output of the second input circuit 7 is applied, and an output of the second input circuit 7 that is the T input. Monomulti 9 given at the end
and a gate circuit 10 to which the output of the first delay circuit 8 and the output of the monomulti 9 are applied.
The output of this gate circuit 10 is applied to the R input terminal via the second delay circuit 11, and the Q output of the monomulti 9 is applied to the CK input terminal,
and a third shift register 12 to which a signal corresponding to logic "1" is applied to the D input terminal; a fourth shift register 14 in which the second output of the third shift register 12 is given to the D output terminal, and the output of the second most significant digit of the third shift register 12 is given to the P/S input terminal;
A second latch circuit to which the parallel data input/output terminal and data input/output terminal of the fourth shift register 14 are connected, and the output of the first high-order digit of the third shift register 12 is applied to the LE input terminal. 1
3, and a second output circuit 15 for sending the serial data output of the fourth shift register 14 to the transmitting device 1. This is performed using a bit-synchronized clock signal using a pulse width signal and a data signal using a short pulse width signal inserted into the bit time between these clock signals. and a readout clock consisting of a continuous long pulse width signal,
A data transmitting/receiving device characterized in that the transmission data 3 received and decoded by the receiving device 2 can be confirmed and read on the transmitting device 1 side.