JPH03822B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data transmission device used for transmitting data to a remote location in a remote control device such as a power line transport system.

[Background technology]

FIG. 1 shows a schematic configuration example of a general remote control device to which the present invention is applied, in which data input to a transmitter 10 is transmitted to a receiver 12 via a transmission line 11, and from the receiver 12. This will be output as data output. Figure 2 shows an example of the format of transmission data sent from the transmitter 10 to the receiver 12. One frame of transmission data consists of a start mark, channel data, and control data, each of which has a number of bits. consists of 1 bit of start mark, 4 bits of channel data, and 4 bits of control data, and two frames are transmitted in one data transmission. Figure 3 shows transmission line 1
This shows an example in which the transmission data transmitted via 1 is transmitted by a carrier signal of frequency c in synchronization with the AC power waveform, and data ``1'' and ``1'' constituting the start mark, channel data, and control data are shown. Data “0” divides the half cycle of the power supply waveform into four, and each of the four divided parts is used as a sub-bit.The start mark is “0101,” data “1” is “0111,” and data “0” is “0100.” ”
It shall be composed of sub-bits. Here, it is assumed that data transmission by amplitude modulation is used such that a carrier wave exists for sub-bit data "1" and no carrier wave exists for sub-bit data "0". FIG. 4 shows a transmission/reception block used in the transmitter 10 and the receiver 12, in which 9 is a modem for modulating and demodulating carrier waves, 1 is a transmission circuit for data transmission, and during transmission, a parallel input port is used. Load the data you want to transmit to and set the transmission start input Ss to “H”, then from the I/O port with modem 9 to modem 9,
Data such as a start mark, channel data, and control data are sequentially sent, and the modem 9 modulates each data into a carrier wave and supplies it to the transmission line 11. Also, during reception, the data from the start mark that is sequentially reproduced by the modem 9 is determined, and only when the channel data matches its own channel, the transmitter 10
Outputs the control data from the parallel output terminal P _I. Further, at the transmission end timing (control data end timing), a transmission end signal is output.
FIG. 5 shows the timing of each part of the transmission circuit 1 shown in FIG. 4, in which a indicates the data to be transmitted, b indicates the input timing of the transmission start input Ss, and c indicates the parallel input port P. d indicates the timing at which data is read from _I , and d indicates the timing at which transmission ends. Start signal transmission. The control data to be transmitted next is read immediately before the control data transmission timing, and a transmission end pulse is output after the control data ends.

In the case of continuous data transmission in the above-mentioned remote control device, conventionally, a microcomputer system, etc. was used to read continuous data and transmit it continuously by operating the program. However, in the case of a system using such a system, the circuit configuration is complicated,
There was a problem that became an obstacle to miniaturization and cost reduction.

[Purpose of the invention]

When transmitting data to a remote location in a remote control device or the like, the present invention is capable of transmitting continuous data efficiently and reliably, and furthermore, the circuit configuration is simplified and the data transmission can be made smaller and cheaper. The purpose is to provide a device.

[Disclosure of the invention]

FIG. 6 shows a block diagram of an embodiment according to the first invention of the present invention, which includes a transmission circuit 1 and a modem 9 similar to the conventional example shown in FIG. 4, as well as a key matrix circuit 2, a key scan circuit 3, First-in, first-out buffer circuit 4 [hereinafter referred to as FiFo memory circuit 4],
It has an oscillation circuit 5 and the like. In addition, FIG. 7 shows the timing of each part of the circuit shown in FIG. The write pulse c of the circuit 4 is a pulse given from the output port A of the FiFo memory circuit 4 to the oscillation circuit 5;
While data remains in the memory circuit 4, this A port remains at "H". Figure d shows the data transmitted from the transmission circuit 1 via the modem 9, in which data 1 to data 4 are sent out in sequence, and Figure e shows the data transmitted to the transmission circuit 1. The end signal is used to read data from the FiFo memory circuit 4, and f in the figure is the oscillation output of the oscillation circuit 5.
While the A port of the FiFo memory circuit 4 is "H", an oscillation output is output to the transmission circuit 1.

Thus, in the embodiment shown in FIG. 6, the key matrix circuit 2 first inputs the data to be transmitted (here, 4-bit data is transmitted, so a maximum of 16 types of data from 0 to 15 are transmitted). It goes without saying that by increasing the number of bits, it is possible to transmit a wide variety of data.) The data in the key matrix circuit 2 is converted into 4-bit parallel data by the key scan circuit 3, and each time a key in the key matrix circuit 2 is pressed, the key scan circuit 3 converts the decoded 4-bit parallel data and write pulse into 4-bit parallel data. The output is obtained as shown in Figures 7a and 7b. Next, the FiFo memory circuit 4 sequentially stores the input data every time the write pulse is "H", and while the data remains in the FiFo memory circuit 4, the output of the output port A is "H". ” In addition, data is outputted in the FiFo memory circuit 4 every time the read input So becomes "H", and when the data in the FiFo memory circuit 4 becomes empty, all data output ports become "L". At the same time, the output of output port A also becomes "L". However, for the first data input, data is output even without a read pulse, and output port A also becomes "H". Next, while the output port A is "H", the oscillation circuit 5 oscillates at a constant cycle and continues to output strobe pulses to the transmission start port Ss of the transmission circuit 1 as shown in FIG. 7f. The transmission circuit 1 starts data transmission when a pulse input that changes from "L" to "H" is received at the Ss port. The first data to be sent at this time is data 1, and with the subsequent read pulse, data 2 is loaded into the input and data 2 is transmitted, and in this way, data 3 and data 4 are transmitted sequentially. Finally, when the memory contents of FiFo memory circuit 4 become empty,
The output of output port A becomes “L”, and the oscillation circuit 5
stops oscillating, and in transmission circuit 1, the transmission start port
Since Ss becomes "L", transmission is stopped.

FIG. 8 shows an embodiment according to the second aspect of the present invention, in which a frequency dividing circuit 6 and an AND gate 13 are further added to the circuit of the embodiment shown in FIG. FIG. 9 shows waveforms of various parts of the embodiment shown in FIG. 8, and a and b in the figure are data and write pulses given from the key scan circuit 3 to the FiFo memory circuit 4, and c is a division pulse. The output pulse of the circuit 6, d is the output pulse of the output port A of the FiFo memory circuit 4, and e is the AND gate 1
3, and f is the oscillation output pulse of the oscillation circuit 5. In addition, g in the same figure shows the transmission circuit 1 and modem 9.
, h indicates a read pulse from the transmission circuit 1 to the FiFo memory circuit 4, and i indicates data given from the FiFo memory circuit 4 to the transmission circuit 1.

Thus, in the circuit of the embodiment shown in FIG. Memory circuit 4
An AND gate 13 performs an AND with the output of the output port A, and the output of the AND gate 13 controls the oscillation of the oscillation circuit 5. As a result, data is transmitted at the transmission start input terminal Ss of the transmission circuit 1 every time the write pulse of the key scan circuit 3 is output twice. In the circuit of the embodiment shown in FIG. 8 according to the second invention, data transmission is performed every two times the write pulse of the key scan circuit 3 is output for the following reason.
In the embodiment according to the first invention shown in FIG. 6, there is no problem when data is transmitted continuously, but when the data transmission interval is sufficiently longer than one data transmission time, There was a problem where unnecessary data was sometimes sent between data that should be sent. In other words, after data 1 is input, if data 2 is not input, after data 1 is sent, transmission circuit 1
The next read pulse prepares to send the next data, but at this time there is no data to be sent in the FiFo memory circuit 4. This is because after data 1 has been transmitted, the output port A has also become "L" and the oscillation circuit 5 has also stopped oscillating, and no input is given to the transmission start input Ss of the transmission circuit 1, but the transmission circuit This is because 1 itself is transmitted twice, so the first transmission is followed by the second transmission. Therefore, since the data output of the FiFo memory circuit 4 is all "L", the data sent at this time is also all "0" data, and there is a problem that this mode of transmission data "0" cannot be used. It is. Thus, the second invention of the present invention, an embodiment of which is shown in FIG. 8, is provided in order to solve the problems of the first invention as described above. Since data transmission is performed each time, data transmission problems like those according to the first invention do not occur.

FIG. 10 shows another embodiment according to the second invention, in which a reset circuit 7 is further added to the embodiment of FIG. The FiFo memory circuit 4 and the frequency dividing circuit 6 are reset when the next write pulse does not occur within the same period. FIG. 11 shows the waveforms of each part of the circuit in FIG. 10, where a and b are the data and write pulses given from the key scan circuit 3 to the FiFo memory circuit 4, and c is the output pulse of the frequency divider circuit 6. , d is the output pulse of the output port A of the FiFo memory circuit 4, e is the output pulse of the AND gate 13,
f is the transmission data transmitted from the transmission circuit 1 and modem 9, g is the read pulse given from the transmission circuit 1 to the FiFo memory circuit 4, h is the oscillation output pulse of the oscillation circuit 5, and i is the transmission data from the FiFo memory circuit 4 to the transmission circuit. 1, j is the reset circuit 7
This is a reset pulse given to the FiFo memory circuit 4 and the frequency divider circuit 6 from 0 to 1, and the reset is active high. Thus, in the case of the circuit of the embodiment shown in FIG. 8, the circuit of the embodiment shown in FIG.
This was provided in consideration of the fact that the last data remains in the FiFo memory circuit 4, and when the next key operation is performed, it is transmitted first and may cause an error in data judgment on the receiving side. It is a thing,
As described above, when the write pulse is not output from the key scan circuit 3 for a certain period of time, the voltage across the capacitor in the reset circuit 7 reaches a predetermined voltage, and the frequency divider circuit 6 and the FiFo memory circuit 4 are reset. By doing this, if no key operation is performed for a certain period of time, the output of the frequency divider circuit 6 will be set to "L", and all the memory contents of the FiFo memory circuit 4 will be cleared, so there will be no remaining data to be transmitted, and the process will continue. Data transmission through key operations is performed correctly.

FIG. 12 shows an embodiment according to the third invention of the present invention, in which a decoding circuit 8 is added to the embodiment of FIG. 8 according to the second invention. Figure 13 shows the waveforms of each part of the circuit in Figure 12, where a and b are the data and write pulses given from the key scan circuit 3 to the FiFo memory circuit 4, respectively, and c is the frequency divider circuit. 6
, d is the output pulse of the output port A of the FiFo memory circuit 4, and e is the decoded output from the decoding circuit 8. Here, an example is shown in which only data 3 is decoded. Further, in the figure, f is the output pulse of the AND gate 13, and g is the transmission data transmitted from the transmission circuit 1 and modem 9, in which irrelevant data 0 is transmitted after data 3. Furthermore, h is a read pulse given from the transmission circuit 1 to the FiFo memory circuit 4, i is the oscillation output of the oscillation circuit 5, and j is data given from the FiFo memory circuit 4 to the transmission circuit 1. In the case of the circuit of the embodiment of FIG. 8 according to the second invention described above, the circuit of FIG. 12 has a configuration in which data transmission is performed every two pieces of input data, so that the transmission end data is the odd-numbered input data. In such a case, there is a problem that the transmission end data may not be transmitted, so this is provided to solve this problem. However, in the embodiment circuit of FIG. 12, the decoding circuit 8 decodes only the transmission end code among the output codes from the key scan circuit 3 (here, data 3 is an example of the transmission end code). The frequency dividing circuit 6 is set by the output of the decoding circuit 8, and even if the output of the frequency dividing circuit 6 is "1", the output is forcibly changed to "H" by the decoding circuit 8. By doing this, when data 3 is output, the output of the frequency divider circuit 6 becomes "H", and at this time, the FiFo
Since the output port A of the memory circuit 4 is at "H", the output of the AND gate 13 is at "H", the oscillation circuit 5 oscillates, and the transmission circuit 1 always transmits the data 3. If this data 3 is the odd-numbered data of the input data, after data 3 is sent, data 0 is further sent as shown in Figure 13g, but data 0 at this time is the transmission end code.Data 3 It can be distinguished from the data 0 that should originally be transmitted. Further, if the transmission end code data 3 is an even number, the data will be transmitted without any problem as in the embodiment of FIG.

〔Effect of the invention〕

In the first aspect of the present invention, a transmission circuit, a key matrix circuit, a key scan circuit, a first-in first-out buffer circuit (FiFo memory circuit),
Since the oscillation circuit is configured as described above, continuous data can be efficiently and reliably transmitted sequentially, and the circuit configuration is simple because there is no need to employ a complicated circuit configuration such as a microcomputer system. This has the effect of realizing miniaturization and cost reduction. Further, in the second invention, since a frequency dividing circuit is provided to divide the frequency of the write pulse, the data is transmitted all at once each time several pieces of data are input by key operation. This has the advantage that even when the data transmission interval is sufficiently longer than the time for one data transmission, reliable data transmission can be performed without any trouble. Further, in the third invention, since a decoding circuit is provided to monitor the output of the key scan circuit, data of a specific code among the code data to be transmitted is
This has the effect that when a transmission end code is transmitted at the end of data transmission, the transmission end code can be transmitted extremely reliably and easily.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of a general remote control device, Fig. 2 is an example of the format of the transmission data shown above, Fig. 3 is a waveform diagram of the transmission signal shown above, and Fig. 4 is a block diagram of the transmission/reception block shown above. 5 is a time chart of the circuit shown in FIG. 4, FIG. 6 is a block diagram of an embodiment of the first embodiment of the present invention, FIG. 7 is a time chart of the circuit shown in FIG. 6, and FIG. A block diagram of an embodiment according to the second invention of the present invention, FIG. 9 is a time chart of the circuit shown in FIG. 8, FIG. 10 is a block diagram of another embodiment of the second invention, and FIG.
Figure 1 is the time chart of the circuit shown in Figure 10 of the same page.
2 is a circuit diagram of an embodiment according to the third invention of the present invention,
FIG. 13 is a time chart of the circuit shown in FIG. 12, where 1 is a transmission circuit, 2 is a key matrix circuit, 3 is a key scan circuit, 4 is a first-in first-out buffer circuit (FiFo memory circuit), 5 is an oscillation circuit,
6 is a frequency dividing circuit, 7 is a reset circuit, and 8 is a decoding circuit.

Claims (1)

[Claims] 1. A transmission circuit that reads control data prior to transmission of control data, starts data transmission when a strobe pulse is input to a transmission start input, and outputs a transmission end pulse for each data transmission. , a key matrix circuit for inputting transmission data, a key scan circuit for encoding the data of this key matrix circuit, a first-in first-out buffer circuit for sequentially inputting and outputting the output of the key scan circuit, and this first-in first-out buffer circuit. 1. An oscillation circuit whose oscillation is controlled by the output of the oscillation circuit and whose output is input to the transmission circuit. 2 A transmission circuit that reads control data before transmitting control data, starts data transmission when a strobe pulse is input to the transmission start input, and outputs a transmission end pulse for each data transmission, and a transmission circuit that inputs the transmission data. a key matrix circuit for encoding data from the key matrix circuit; a key scan circuit for encoding the data of the key matrix circuit; a first-in, first-out buffer circuit for sequentially inputting and sequentially outputting the output of the key scan circuit; It comprises a frequency dividing circuit that divides the frequency of the write pulse, and an oscillation circuit whose oscillation is controlled by an AND output of the output of the frequency dividing circuit and the output of the first-in, first-out buffer circuit, and whose output is input to the transmission circuit. A data transmission device characterized by: 3. The data transmission device according to claim 2, further comprising a reset circuit that resets the frequency divider circuit and the first-in first-out buffer circuit when a write pulse from the key scan circuit is not generated for a certain period of time. 4 A transmission circuit that reads control data before transmitting control data, starts data transmission when a strobe pulse is input to the transmission start input, and outputs a transmission end pulse for each data transmission, and a transmission circuit that inputs the transmission data. a key matrix circuit for encoding data from the key matrix circuit; a key scan circuit for encoding the data of the key matrix circuit; a first-in, first-out buffer circuit for sequentially inputting and sequentially outputting the output of the key scan circuit; A frequency dividing circuit that divides the frequency of the write pulse, an oscillation circuit that controls oscillation by AND outputting the output of this frequency dividing circuit and the output of the first-in first-out buffer circuit, and inputs the output to the transmission circuit, and data of the key scan circuit. 1. A data transmission device comprising: a decoding circuit that monitors an output and forcibly sets the frequency dividing circuit when a specific data output is detected.