JPS6040749B2 - serial transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a serial transmission device that supplies a clock from a receiving side to a transmitting side, and particularly relates to a serial transmission device suitable for cases where there are large variations in the processing time of received data.

FIG. 1 is a diagram showing an example of a subordinate serial transmission device.

In FIG. 1, if device 1 is on the transmitting side and device 2 is on the receiving side (the present invention relates to transmission in this direction), then on the transmitting side 1, data to be sent from the parallel data line 91 is first sent to the transmission data storage circuit 11. be taken in. Next, receiving side 2
The clock line 104 is generated by the clock generation circuit 5 of
The captured data is converted into serial data by the parallel-to-serial conversion circuit 21 in response to a clock signal sent through the parallel serial conversion circuit 21, and is sent out through the transmission data line 102. On the receiving side 2, the sent serial data is taken into the serial/parallel conversion circuit 32 by the clock signal generated by the clock generation circuit 5, and when the number of bits for one character has been input, the received data is stored as parallel data. The data is transferred to a circuit 42, from where it is transferred to a processing device or the like via a parallel data line 92. In addition, from device 2 to device 1
When serially transmitting data to
, storage circuit 12, parallel-to-serial conversion circuit 22, data line 103, serial-to-parallel conversion circuit 31, received data storage circuit 4
1. Data is sent in the order of data line 91.

By the way, if the amount of data to be transmitted increases and the data is to be sent in a short time, the clock must be made faster.

However, if the data contains data that requires a long time to process, the next data cannot be retrieved for data processing, and the sent data may be lost. The following four methods can be considered as countermeasures against this problem. {1}
The clock rate is slowed down so that only one piece of next data is sent within the maximum processing time for one piece of data.

'21 Equipped with a buffer memory that can store all the data sent within the maximum processing time for one data. {
3} While data is being processed, stop the clock to prevent the next data from being sent.

{4' A signal indicating that data is being processed is sent to the sending side, and this signal causes the sending side to stop sending the data.

However, these methods have the following drawbacks.

First, method [1'] lowers the data transmission speed, which defeats the purpose of transmitting data at high speed. '
In method 2, the amount of data to be temporarily stored increases as the transmission speed increases, and it is necessary to constantly provide a large buffer to manage this. Sometimes this results in a very wasteful system. For example, if the transmission rate is 50 kilobaud and the maximum processing time for one data is 100 milliseconds, a buffer memory of 5 kilobits is required. {3'
Methods (4) and (4) are the same in that the data transmission on the transmitting side is controlled on the receiving side.

As shown in Figure 2, the second method is to provide a gate circuit where the clock signal is sent to the outside, and prevent the clock signal from being sent to the transmitting side based on the clock control signal 101 sent from the processing device. It is intended to do so. {
In method 4}, it is sufficient to consider that such a control circuit is provided on the transmitting side. The problem with these methods is that in the case of a leg, it is impossible to distinguish between a malfunction in the other party's equipment or an abnormality in the line, which is usually detected when the clock signal drops, and the abnormality detection function cannot be used. In the case of '4-, one cable must be added between the sending side and the receiving side. Furthermore, these methods have the problem of timing when the transmitter stops sending data. In other words, in the '3l method, it is not possible to stop the clock in the middle of data transmission, so it is necessary to provide a sufficient time interval between data to stop the clock and stop the transmission of the next data. . This leads to a reduction in the overall transmission speed, and the signal transmission delay time varies depending on the transmission distance, and the control circuit becomes complicated to take this into account. The method {4} also has a similar problem. An object of the present invention is to eliminate the drawbacks of the prior art described above, and to provide a simple method that can maintain a high overall transmission speed without causing loss of transmitted data even if there is data that requires a long processing time. The object of the present invention is to provide a serial transmission device with a circuit configuration.

In order to achieve the above object, in the present invention, the receiving side determines the required processing time of the received data, and depending on the result, the following data is
This feature is characterized in that the speed of the clock sent to the transmitting side is varied so that one or more clocks are not transmitted. Hereinafter, the details of the present invention will be explained with reference to Examples.
FIG. 3 is a diagram showing an embodiment of the present invention. In FIG. 3, in addition to the subordinate clock generation circuit 5, a frequency dividing circuit 6 for generating a slower clock, a selection circuit 7 for selecting the divided clock, and a selection circuit 7 are controlled. A decoding circuit 8 is added which monitors the received data in order to produce a signal that reflects the received data. Now, assuming that the normal data transmission speed is 50 kilobaud and 1 data is 11 bits,
The processing time allowed for one data is approximately 220 microseconds, and when data requiring a longer processing time is received, it is necessary to delay the next data.

Assume that data that require such a long processing time include data that requires 1 millisecond to process (data 1) and data that requires 100 milliseconds to process (data 2). Then, the transmission speed when only one data is sent during data processing is 11 kilobaud or less for data 1,
Data 2 is 110 baud or less. Therefore, in FIG. 4, which shows the clock control part of FIG. 3 in more detail, the frequency dividing circuit 6 sets the input 1 of the selection circuit 7 to 50 kilobaud, the input 2 to 9,600 baud, and the input 3 to 110 baud. is provided. The received data is input to the decoding circuit 8 at the same time as being sent to the processing device. When the received data is normal data, outputs 1 and 2 of the decoding circuit 8 are both 0, and the selection circuit 7 selects the input 1 of 50 kilobaud. When the previous data is detected by the decoding circuit 8,
The output of the decoding circuit 8 becomes 01, the selection circuit 7 selects the input 2, and the 9,600 baud clock signal is selected and output. Further, when data 2 is detected, the clock signal becomes 110 baud. In this way, when data that requires a long processing time is detected, the clock speed is immediately reduced, and if the speed of the subsequent data is set to 9,600 po or 110 baud, one piece of data will be sent. It is possible to fully complete the processing of the previous data during this time. According to this method, even if the clock becomes slower, the length of one bit only becomes longer, so there is no problem in switching even from the middle of the transmitted data, and there is no problem with the timing between transmission and reception.

Furthermore, there is no extra waiting time between transmitted data, and the transmission speed can be increased to the maximum reception capability of the receiving side. In the embodiment shown in FIG. 3, the received data is monitored by the decoding circuit, but this may be done by the software of the processing device and the decoding circuit may be omitted.

As is clear from the above description, according to the present invention, by adding a relatively simple circuit, it is possible to efficiently and reliably transmit data that requires different processing times.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing an example of the configuration of a conventional serial transmission device, FIG. 2 is a diagram showing a conventional clock control method, and FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 shows the characteristics of the present invention. FIG. 1... Sending side, 2
...Receiving side, 5...Clock generation circuit, 6...Divide circuit, 7...Selection circuit, 8...
・Decoding circuit. Many! Diagram 2 and 3 *mu diagram

Claims (1)

[Claims] 1. A serial transmission device configured to serially transmit data from the transmitting side to the receiving side using a clock signal at a predetermined speed supplied from the receiving side to the transmitting side,
The apparatus further comprises a means for determining the processing time required for the data received by the receiving side to be processed by the receiving side, and based on the determination result of the determining means, whether the received data is processed within the processing time. For example, the clock control means supplies a clock signal at the same speed as the predetermined speed to the transmitting side, and supplies a clock signal at a speed slower than the predetermined speed to the transmitting side unless the received data is processed within the processing time. What is claimed is: 1. A serial transmission device comprising: a serial transmission device comprising: a serial transmission device; and controlling that data that continues within a received data processing time is transmitted from the transmitting side.