JPS62226248A - Memory address checking system - Google Patents

Abstract

PURPOSE:To shorten the access time of a data processing system and to improve the system performance by transferring independently the address signal regardless of the check bit. CONSTITUTION:When a memory controller 1 receives an address signal 100 from a central processing unit, etc., a transmission part 10 sends immediately the signal 100 to a memory device 2. While a check bit generating part 11 produces a check bit signal 200 for the signal 100 and a transmission part 10a sends a check bit signal 201 later than the part 10. The device 2 starts immediately a memory access when a reception part 20 receives an address signal 101 and at the same time stores temporarily an address signal 102 in a register 21. Then an error check part 22 decides the presence or absence of the error of the signal 102 and transmits an error detecting signal 300 when a reception part 20a receives the signal 201.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory address check system, and more particularly to an improvement in a memory address check system for detecting errors that occur during address signal transfer.

[Conventional technology]

Memory devices are widely used for data storage, such as in data processing systems. Such a memory device is connected to a central processing unit or the like via a memory control device 4.

Generally, a memory address for instructing access to such a memory device is generated by a central processing unit or the like and sent to a memory control device. The memory control device and the memory device usually have their own means for checking memory address transmission errors.

That is, as shown in FIG. 2, the memory control device 51 includes a check bit generating section 61 that generates the check bit 250 of the address signal 150, and the transmitting section 60 simultaneously sends out the address signal 150 and the check bit 250.

Then, the receiving section 70 of the memory device [52 receives them and sends them to the error checking section 71, and also sends the address signal 1.
50 starts memory access. At the same time, the error check section 71 determines whether or not there is an error in the address signal 150 and sends out an error detection signal 350.

In such a memory address check system, the address signal 150 is queued in the memory controller while the address signal 150 is being generated. Therefore, since the sending of the address signal 150 is delayed accordingly, there is a drawback that the access time to the memory is increased.

[Problems to be Solved by the Invention] The problems to be solved by the present invention, in other words, the purpose of the present invention is to provide a memory that improves the above-mentioned drawbacks by uniquely transferring address signals independently of check bits. The purpose is to provide an address check method.

[Means for solving problems]

The memory address check method of the present invention includes: a first transmitter that sends out an address signal; a check bit generator that receives the address signal and generates a check bit for the address signal; a memory control device having a second transmitting section that transmits the check bit; a first receiving section that receives the address signal transmitted by the first transmitting section; a register that starts reading or injecting data according to the address signal and temporarily stores the address signal; a second receiving section that receives the check bit sent by the second transmitting section; a memory device comprising: an error check section that inputs the stored address signal and the check bit received by the second receiving section, determines whether or not there is an error in the address signal, and sends out an error detection signal; and is configured to read or write the data in advance of the error detection signal of the address signal.

〔Example〕

Hereinafter, a memory address check method according to the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, address signal 10 in memory control device 1
0 becomes the address signal 102 in the memory device 2 and starts memory access, and in parallel, error processing of the address signal is executed and an error detection signal 300 is sent out.

In the memory control device 1, the transmitter 10 sends an address signal 1
00 is input and sent as the address signal 101. The check bit generating section 11 generates an upper pit and sends out a check bit signal 200. Also, the transmitter 10a
inputs the above check bit signal 200 and sends it out as a check bit signal 201.

In the memory device 2, the receiving section 20 receives the address signal 101.
is input and sent as the address signal 102.

The register 21 receives the address signal 102 described above, temporarily stores it, and sends it out as an address signal 103.

The receiving unit 20a also receives a check bit signal 201 and sends it out as a check bit signal 202. Then, the error check section 22 uses the address signal 103 mentioned above.
and an error check signal 202, it determines whether or not there is an error in the address signal, and sends out an error detection signal 300.

In such a memory address check method, an address signal 100 is sent from a central processing unit or the like to a memory control device fi.
1 is received, the transmitter 10 immediately transmits it to the memory device 2. In the meantime, ~Kubito Ryotsuki (11
Since the check bit signal 200 of the address 0 address signal 100 of the value IP is generated, the transmitter 10a transmits the check bit signal 20'1 later than the transmitter 10 described above.

Immediately when the receiving unit 20 receives the address signal 101, the memory device 2 starts memory access and temporarily stores the address signal 102 in the register 21. Then, after the receiving section 20a receives the check bit signal 201 with a delay of υ from the receiving section 20, the error checking section 22 determines whether or not there is an error in the address signal 102, and sends out an error detection signal 300.

In this manner, the address signal is sent to the memory device in advance of the check bit signal to initiate memory access without waiting for the check bit signal.

〔Effect of the invention〕

As explained above in detail, according to the memory address check method of the present invention, the memory control device can immediately transfer the address signal to the memory device and start memory access, thereby reducing the access time as a data processing system. This has the effect of improving system performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory address check method according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional memory address check method. DESCRIPTION OF SYMBOLS 1...Memory control device, 2...Memory device, 1o/10a...Transmission unit, 11...
・・Check bit generation part, 20・20a・・・・
Receiving section, 21...Register, 22...
Engineering 2-Che, Ribe. Agent Patent Attorney Susumu Uchihara”°1.゛ ,+
+, -+ Figure 1 + -----% t Suzume 1p Discipline 100~1
03.・7-Address signal 2 ----- ;I'f
= So table ff 200~2
oz --- One handiwork / Kuhi 2 Toy No. signal

Claims (1)

[Scope of Claims] A first transmitter that sends out an address signal, a check bit generator that receives the address signal and generates a check bit of the address signal, and a check bit that is delayed from the address signal. a second transmitter that transmits the address signal; a first receiver that receives the address signal transmitted by the first transmitter; and a memory control device that transmits the address signal received by the first receiver. a register that starts reading or writing data and temporarily stores the address signal, a second receiving section that receives the check bit sent by the second transmitting section, and the address temporarily stored in the register. a memory device having an error check section that inputs the signal and the check bit received by the second receiving section, determines whether or not there is an error in the address signal, and sends out an error detection signal. . A memory address check method, characterized in that reading or writing of the data can be executed prior to the error detection signal of the address signal.