JPS6376599A - Remote control circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit and to obtain a remote control circuit with a low cost by constituting a reception part with a pulse counting circuit decoder, and a gate IC such as a data latch. CONSTITUTION:A pulse string T1 outputted from a transmission part, goes through a piece of communication line 4 and i.s inputted to the pulse counting cricuit 5 of the reception part. The pulse counting circuit 5 counts the leading of the pulse string T1, and outputs a binary data constituted of the number of the leading to a decoding circuit 7. The circuit 7 outputs a data T2 to the data latch circuit 8 in accordance with the inputted binary data. The pulse string T1 outputted from the transmission part is also inputted to a pulse reception end detecting circuit 6 which detects the end of the pulse string T1 by making use of that the pulses are not transmitted beyond the period t1 of the pulse, and outputs a latch signal T3 to the CLK terminal of the data latch circuit 8. In such a way, the control of the data latch circuit of the reception part can be executed by varying the number of the pulse strings.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a remote control circuit, and particularly to a remote control circuit that uses a core communication line to communicate between a transmitting section and a receiving section that are separated according to the number of pulses. The present invention relates to a remote control circuit suitable for remote control.

[Conventional technology]

Conventionally, as a remote control method, a general-purpose data control procedure such as a basic procedure or a high-level data link control procedure (HDLC procedure) is used between a transmitter and a receiver connected by a communication line to transmit data from the transmitter. There is a method that uses a microcomputer or the like to transmit data, determine whether the data has been received in a receiving section, and control the receiving section. Incidentally, related devices of this type include, for example, Japanese Patent Laid-Open Nos. 59-219051 and 60-19848.

[Problem that the invention attempts to solve]

In the above-mentioned conventional technology, by changing the data pattern, it is possible to control as many data pattern combinations as possible, but the circuit for this pattern discrimination becomes complicated, so it is difficult to turn on the lamp.

When performing fifl ji control such as off, there is a problem in that it is expensive.

An object of the present invention is to provide an inexpensive circuit for remotely controlling an external device using a single communication line.

[Means for solving problems]

”-The purpose of the description is to provide a pulse generator that outputs pulses of a predetermined period, a pulse transmission number designation circuit that designates the number of pulse transmission,
A transmitter 477 provided with a pulse transmitting U1'1 control circuit etc. that controls the pulse transmitting interval by the pulse transmitting number designation signal.
a pulse counting circuit that counts the pulses transmitted from the transmitting section via the transmitting circuit and outputs binary data; and a decoding circuit that decodes the binary data counted by the counting circuit. , a pulse reception end detection circuit that detects the end of reception of the pulse transmitted from the transmitter;
a receiving section provided with a data latch circuit that launches the output signal of the decoding circuit with the output signal of the pulse receiver a end detection circuit, and the transmitting section and the receiving section are connected by a communication line, From the transmitter, the number of pulses to be transmitted is designated by the pulse transmission number designation circuit, and the pulse transmission time control circuit creates a time for transmitting pulses from the pulse generator and a time for not transmitting pulses, and A specified number of pulses are transmitted, the number of pulses is counted by the pulse counting circuit in the receiving section, and the binary data output of the image is decoded by the decoding circuit.

This is achieved by latching data in the data latch circuit using the output signal of the decoding circuit using the output signal of the pulse reception end detection circuit to obtain a predetermined output signal.

[Effect]

The uninvented remote control circuit includes a pulse generator that outputs pulses at a predetermined period and pulse transmission! ! a transmitter provided with a pulse transmission number designation circuit for specifying the number of pulse transmissions, a pulse transmission time control circuit that controls a pulse transmission interval based on the pulse transmission number designation signal, and a pulse transmission unit that counts the pulses transmitted from the transmission unit. a pulse counting circuit that outputs binary data, a decoding circuit that decodes the counted binary data, and a pulse reception detection circuit that detects the end of reception of the pulses sent from the transmitter. and a data latch circuit that latches the output signal of the decoding circuit No. 111 with the output signal of the pulse reception end detection circuit.
Connect the transmitter and the receiver with a single line, specify the number of pulses to be transmitted from the transmitter using the pulse transmission number designation circuit, and when the pulse is transmitted [;1 The control circuit creates a time period for transmitting pulses from the pulse generator and a time period for not transmitting pulses, transmits the specified number of pulses, and counts the number of pulses using the pulse counting circuit in the receiving section. Then, the binary data output after counting is decoded by the decoding circuit, and the output signal of the decoding circuit (*if) is latched by the data latch circuit according to the output signal of the buffless reception completion detection circuit, and the data is latched into a predetermined output. The signal is used to control the external device (11).

〔Example〕

An embodiment of the present invention will be described below using a seedling in FIG.

FIG. 1 is a block diagram showing the 11 parts and the 4Jj parts of the control circuit of the present invention. In the unit shown in the figure, 1 is a pulse generator that generates a pulse at a predetermined period, 2 is a pulse transmitter signal number designation circuit that specifies the number of pulse transmissions, and 3 is a pulse generator designated by the pulse transmission 411 number designation circuit. When sending the number of pulses (1-1 convex pulse sending 1)::j
jjj, (control circuit, 4 is the number of passes, line, 5 is 1) Count the pulses sent 1Δ from the transmitter in II. 2! ↑So-・
Pulse, which outputs evening? 1" several times - each, 6 is the pulse reception end detection circuit that detects the end of pulse reception, 7 is the pulse reception end detection circuit that detects the end of pulse reception. A decode circuit decodes the output signal of the t-number circuit, and 8 is a data latch circuit that launches the output of the decode circuit with the output signal of the pulse reception end detection circuit.

Figure 2 shows each checkpoint! - timing chart 1
− is. In the figure, T1 is the output signal of the receiving section,
T2 is the input signal of the data latch circuit, T3 is the data latch signal output from the pulse reception end detection circuit, and T
4 is a clear signal of the pulse counting circuit outputted from the pulse reception end detection circuit.

Here, a case will be described in which the output υ]- is turned ON.

By setting the number of pulse transmissions to ll 2 +1 by the pulse transmission number designation circuit 2 of the transmitting section, the pulse transmission time control circuit 3 transmits two pulse trains from the pulse generator 1, and then transmits the pulses as shown in FIG. at least the pulse period t
! Control is performed so that no more pulses are transmitted. Therefore, the pulse train has a waveform as shown in FIG. 2TI.

The pulse train T1 output from the transmitter passes through one communication line 4 and is input to the pulse counting circuit 5 of the receiver. The pulse counting circuit 5 counts the rising edges of the pulse train T1 and outputs binary data constituted by the number of rising edges to the decoding circuit 7. The decode circuit 7 outputs data to the data latch circuit 8 according to the input binary data. The waveform input to the data latch circuit 8 is as shown in FIG. 2 T2. Also, [)? output from the transmitter? The pulse train T1 is also input to a pulse reception end detection circuit 6, which detects the end of the pulse train T1 by not transmitting a pulse for a pulse period t1 or more, and outputs a latch signal to the CLK terminal of the data latch circuit 8. The latch signal has a waveform shown as T3 in FIG. The output of the decoding circuit 7 is 1. J is I-
Since 1 and K are at L, when the latch signal falls, Q becomes H and output 0 of data latch circuit 8 turns ON, as shown in the truth value in the table below.

Further, a signal obtained by delaying the rij latch signal of the pulse reception end detection circuit 6 is sent to the CL R of the pulse counting circuit.
Input to the terminal, clear the pulse 30 circuit, and wait for the next pulse to be received.

Therefore, according to the first embodiment, the data latch circuit of the receiving section can be controlled by changing the number of pulse trains.

〔Effect of the invention〕

According to the present invention, since the receiving equalizer section can be constructed of a pulse jF number circuit decoder, a gate IC such as a data latch, etc., the circuit can be simplified and an inexpensive remote stop control circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a remote control circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart of each check point in FIG. 1. 1... Pulse generator, 2... Pulse transmission number designation circuit, 3... Pulse transmission time control circuit, 4 ylll line,
5. Pulse counting circuit, 6. Pulse reception end detection circuit. 7 decoding circuit, 8... data launch circuit. Patent Applicant: Hitachi Shonan Electronics Co., Ltd. Representative Patent Attorney Tadashi Akimoto Figure 1 Figure 2 U T4 Size - 11ri m - Ministry of Procedure ■ Author (self-motivated) November 6, 1986

Claims (1)

[Claims] 1. Transmission equipped with a pulse generator that outputs pulses of a predetermined period, a pulse transmission number designation circuit that designates the number of pulse transmission, and a pulse transmission time control circuit that controls the pulse transmission interval by the pulse transmission number designation signal. a pulse counting circuit that counts pulses transmitted from the transmitting section via a communication line and outputs binary data; a decoding circuit that decodes the binary data counted by the counting circuit; and the transmitting section. a receiving section including a pulse reception end detection circuit that detects the end of reception of the pulse transmitted from the pulse reception end detection circuit; and a data latch circuit that latches the output signal of the decoding circuit with the output signal of the pulse reception end detection circuit. , the transmitting section and the receiving section are connected through a communication line, the transmitting section specifies the number of pulse transmissions by the pulse transmission number designation circuit, and the pulse transmission time control circuit specifies the pulse transmission number from the pulse generator. A time for transmitting and a time for not transmitting pulses are set, the specified number of pulses are transmitted, and in the receiving section, the number of pulses is counted by the pulse counting circuit, and the binary data output after counting is decoded. A remote control circuit characterized in that the output signal of the decoding circuit is decoded by a circuit, and the data is latched by the data latch circuit using the output signal of the pulse reception end detection circuit to obtain a predetermined output signal.