SU1300482A1 - Interface for linking computer with using equipment - Google Patents

Abstract

The invention relates to computing technology, in particular, to devices for matching interfaces. The aim of the invention is to reduce equipment costs and expand the scope. The device contains four receivers 4, 2, 17, 18, four transmitters 1, 3, 19, 20, control node 9, pulse generator 21, multiplexer 6, parity node 5, comparison node 10, encoder 14, command register 13, decoder 12 , 8 state byte register, parity decoder 15, 16 instruction encoder. 1 hp f-ly, 2 bb

Description

The invention relates to computing, in particular, to devices for matching interfaces.

The purpose of the invention is to reduce equipment costs and expand the scope.

FIG. I presents the block diagram of the proposed device; in fig. 2 is a control node diagram.

The devices for interfacing a computer with a subscriber comprise (FIG. 1) a first transmitter 1, a second receiver 2, a second transmitter 3, a first receiver 4, a parity node 5, a multiplexer 6, an address encoder 7, a status byte register 8, a control node 9, Comparison node 10, updated status byte register 11, decoder 12, command register 13, encoder 14, parity decoder 15, command encoder 16, third 17 and fourth 18 receivers, third 19 and fourth 20 transmitters, 21 pulse generator.

Control node 9 contains (Fig. 2, multiplexer 22, fixed memory 23, first 2A, second 25 and third 26 registers.

The device works as follows.

Depending on the specific state of the computer or subscriber (external device), the following I / O sequences of initial sample signals may be performed; the sequence of signals sampled by the subscriber; sequence of data transmission signals; sequence of signals for the end of the operation (state transfer).

The computer begins a sequence of initial sampling signals at the address of the external device to the first information input of the ADR-K identification signal device and the FBG-K control signal to the first control input of the device. The address from the information input through the first receiver 4 is fed to one input of the comparison node 10. If the arriving address coincides with the address arriving at the second input of the node 10 in comparison with the output of the address encoder 7, then the Address is identified signal, which is fed to the input of the control node 9.

Node 9 is a firmware automat (FIG. 2). The Address signal is recognized and the ADR-K and VBR-K signal passing through the second receiver 2 are fed to the input of node 9, where they are fed to the information inputs of multiplexer 22. In the initial state, the automaton is in the wait state these signals, i.e. From the output of the register 26, the control input of the multiplexer 22 receives a code permitting the passage of signals through the multiplexer 22 to the input of a permanent memory (PP) 23. As a result, the output of the PC 23 sets the contents of the cell. The address code will be determined by the combination of signals received from multiplexer 22 and the code received from the output of register 26. According to a signal from the generator 21, the information set at the output of the permanent memory 23 is entered into a register. In register 24, a bit corresponding to the RAB-A signal will be set, a new code will be recorded in register 25, which will allow selection of PP cells 23 from another area, and a code allowing 22 input signals to pass through the multiplexer will be recorded in register 26, on the next cycle of the machine.

The signal RAB-A through the second transmitter 3 is fed to the first control output of the device. In response to the RAB-A signal, the computer resets the ADR-K signal. After the ADR-K signal is reset, node 9 generates a code arriving at the control input of multiplexer 6, as a result, the address from the output of the address encoder 7 through multiplexer 6 and the first transmitter 1 enters the first information output of the device. Simultaneously with the issuance of the address in node 9, an ADP-A signal is produced through the second transmitter 3 which enters the computer. The computer in response to the address of the device and the ADR-A signal resets the VBR-K signal. The computer compares the issued address with the received one, if they match, issues a command to the first information input and the UPR-K signal. The 8-bit command code through the first receiver 4 is fed to the input of the encoder 14, from the output of which the 3-bit code goes to the information input of the register 13 of commands. Signal

UPR-K through the second receiver 2 is fed to the input of node 9, which generates from the reception of the reception room, which is fed to the input of the register register 13 commands and allows the command to be written into the register. Next, node 9 resets the ADR-A signal. As soon as the ADR-A signal is reset, the computer resets the UPR-K signal. After that, node 9 generates an address code, which is fed to the input of multiplexer 6. As a result, the 8 status byte through the multiplexer 6 and the first transmitter 1 are sent to the first information output by the device status byte. At node 9, the UPR-A signal is generated, which, through the second transmitter 3, arrives at the output of the device. If the device can execute the command, then the status byte is zero. In response to the UPR-A, the computer responds with an INF-K signal, which means that the computer receives a status byte. The INF-K signal through the second receiver 2 enters node 9. The RAB-A and UPR-A signals are reset by this signal, then the computer resets the JNF-K signal, completing the initial sampling sequence. If the Record command was transmitted at that, the encoder 16 commands, receiving the command code from the register of 13 commands, and the enabling signal from node 9 generates a readiness signal for the GI-I source, which is transmitted to the subscriber through the third transmitter 19

In the case of issuing commands Read or Refine, the encoder 16 commands forms the readiness signal of the receiver GN-I, which goes to the subscriber connected to the device.

When a device requires communication with a computer to transmit data or state in a computer, as well as to receive data from a computer, node 9 via the second transmitter 3 does not send a TRB-A signal. The computer transmits a VBR-K signal to the computer TRB-A signal, which through the second receiver 2 enters the input of node 9. After this, the output of node 9 is set to RAB-A, to TRB-A it is reset. Further, as in the case of a sequence of initial sampling, the address of the device and the ADPA-A signal are given. The computer receives the address and responds with a UPR-K signal. This means to continue. Then

ADR-A is reset, and the computer in response resets the UPR-K signal. At this point, the sequence of sampling signals entered by the subscriber ends, and then either the data transmission sequence or the transmission status follows.

Consider the data transfer sequence. After receiving the instruction Continue, node 9 generates a control signal, according to which the brute force 16 passes through the third forward request from the RR-I receiver. In response, the subscriber sets the data information byte of the device to the second information input and, on the second control of the device, inputs the gate signal of the CTP-K source to the second control unit. Node 9 generates a code that arrives at the input of multiplexer 6, allowing information to pass through multiplexer 6, the first transmitter 1 to the computer. Then the node 9 generates a signal INF-A, coming through the second transmitter 3 to the computer. The computer, in response to INF-A, infects INF-K, which through the second receiver 2 enters the input of node 9. After this, node 9 generates a control signal on which block 16. resets the signal UP-I, in response, the subscriber resets STR-K. Then the INF-A is reset, and the computer resets the INF-K signal. The duration of the communication of the device with the computer can be determined both from the computer side, saving the FBG-K signal, and from the device side, keeping the RAB-A.

If there is a request for data transmission from a computer, an INF-A signal is established. The computer responds by issuing a byte of data to the first information input of the device and an INF-K signal. The end of the data reception from the computer is the same as in the transmission of data to the computer.

The end sequence of the operation is performed as follows. Consider for example the sequence of the end of the Read operation. The operation can be completed both by the computer and by the subscriber.

If the termination occurs from the computer side, then during data transmission, in response to the INF-A signal, the computer responds with an UPR-K signal, not an INF-K signal, which means an indication of a Stop. After that, the device resets

signals INF-A, RAB-A, GP-I. Upon a Stop order, the subscriber continues to work until the end of the operation and remains occupied until the status byte with the operation end indicators that the computer can accept either when executing the sequence of signals input by the subscriber or when performing the sequence of signals for the initial sample.

Transmitting a status byte with operation end indicators during a sequence of sampled signals entered by the subscriber. One iH3 of the control bus of the second control of the device's entrance through the quarters of the receiver 18 to the node 9 receives the signal VUK (External device ended). According to the signal of the VUK, the node 9 generates a signal of the TRB-A, actions in the computer. From the moment the TRB-A signal arrives on the computer, the sequence of the sampling signals entered by the subscriber begins. This sequence is described. After receiving the instruction Continue at node 9, a code arriving at the input of multiplexer 6 is detected, which allows the output from the register output 8 bytes of state, in addition, the UPR-A signal is generated. The computer in response generates an INF-K signal, which means the reception of a computer state byte. Upon receiving this signal, node 9 resets the RAB-A and UPR-Ao signals. Then the computer resets the INF-Co signal. This completes the state transfer.

Claims (2)

During the transfer of a computer state, instead of INF-K, it can give a UPR-K signal. This means that the computer instructs you to remember the status. In addition, the computer can control the state transfer by issuing a BLK-K signal that blocks the transfer of the state. If the BLK-K signal is cleared, the transmission of the status byte with termination indicators is repeated until the computer receives the status byte. Invention Formula - 1. A device for interfacing a computer with a subscriber, containing the first and second receivers, the first and second transmitters, a multiplexer, a parity check node, an address coder, a status byte register, a status byte register, a control node, the comparison node, the command register, the parity decoder, the information inputs of the first and second receivers being inputs of the device for connecting to the information and control outputs of the computer, respectively, the information outputs of the first and second transmitters being outputs of the device For connecting to the information and control inputs of a computer respectively, the output of the address encoder is connected to the first information input of the multiplexer and the first information input of the comparison node, the output of which is with the start input of the control node, the first output and the first input of the logic condition of which are connected to the first information input and output of the status byte register, respectively, the second information output of which is connected to the second information input of the multiplexer, the output of which is connected to the first information input of the first transmitter and information input parity control node, the output of which is connected to the second information input of the first transmitter, the information output of the second receiver and the information The second transmitter input is connected to a second logic condition input and a second control node output, respectively, the third output of which is connected to the control input of the multiplexer, the third information input of which is connected to the register output of the updated status byte, the information input of the parity decoder and the second information input the comparison node is connected to the corresponding bits of the group of information outputs of the first receiver, characterized in that, in order to reduce equipment costs, it is expanded and fields of application, a generator of 5 pulses, a decoder, an encoder, a third and fourth receivers, a third and fourth transmitters, a command coder, and informational outputs of the third and fourth transmitters are outputs of the device for connecting to the subscriber’s control and information inputs, respectively, the information inputs of the third and fourth receivers are the inputs of the device for connection, to information correspondingly, the output of the pulse generator is connected to the clock input of the control node and the gate input of the status byte register, the second information input of which is connected to the third input of the logical condition of the control node, information output of the fourth receiver, with the first information input of the register of the updated status byte, the gate input of which is connected to the output of the decoder, the information input of which is connected to the third information input of the inspecting the status byte, the information input of the command encoder and the output of the command register, strobe the input of which is connected to the fourth output of the control node, the fifth output of which is connected to the enabling input of the command encoder, the information output of which is connected to the information input of the third transmitter, the third output information the receiver is connected to the fourth information input of the multiplexer; the second information input of the specified byte-state register is connected to the output of the parity decoder, the information ny instruction register input connected to the output of the encoder, an information input and a fourth data input connected to the transmitter W 15 004828 corresponding bits of the group of information outputs of the first receiver. 2. The device of claim 1, wherein the control node contains a multiplexer, a permanent memory, three registers, the first, second, third and fourth information inputs of the multiplexer being the first, second, third inputs of the logical conditions and the input the start of the control node, respectively, the gate inputs of the first, second and third registers are the clock input of the control node, the first, second, third, fourth and fifth outputs of the first register are the first, second, third, fourth and fifth outputs of the control node Accordingly, in the control unit, the information input of the first register is connected to the first information output of the permanent memory, the second information output of which is connected to the information input of the second register, the output of which is connected to the control input of the multiplexer, the output of which is connected to the first address output  the input of the permanent memory, the third information output of which is connected to the information input of the third register, the output of which is connected to the second address input of the post-memory. 20 25 Editor M, Pandora Phi1.2 Compiled by S. Pestmal Tehred A. Kravchuk Proofreader p. Cherni Order 1150/48 Circulation 673 Subscription VIIIPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and Printing Enterprise, Uzhgorod, Projecto st., 4