RU2108680C1 - Digital information receiving device - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has input unit 1, code converter 2, shift registers 3,4, clock generator 6, AND gates 7,9, threshold unit 8, OR gate 10, switch 11. EFFECT: improved design. 2 dwg

Description

 The invention relates to telecommunications.

The purpose of the invention is the expansion of functionality by receiving messages transmitted by the signals / 2 ⁿ + 1 / - position code.

 In FIG. 1 shows a structural electrical diagram of the proposed device, FIG. 2 are diagrams explaining the operation.

 The device comprises an input unit 1, a code converter 2, shift registers 3, 4, 5, a clock pulse generator 6, a first AND element 7, a threshold unit 8, a second AND element 9, an OR element 10, a key 11.

 A device for receiving discrete information works as follows.

Reception of messages (see Fig. 2, a) transmitted in start-stop mode by signals of a 2 ^2- position code.

Initial state of the device: threshold block threshold 8 - U, where 0 <U <u $\genfrac{}{}{0ex}{}{\text{n}}{}$$\genfrac{}{}{0ex}{}{}{\text{2}}$ ., key 11 is closed.

In the pauses between reception cycles from the output of input block 1, a high (stop) potential is fed to the input of code converter 2 (code converter 2 converts the 2 ^n- position code into a two-position code) and the input of threshold block 8. In the first low order bit of shift register 3, the unit is written " Due to this, a high potential is supplied to the first input of the And 7 element from the output of the first least significant bit of the shift register 3. At the second input of the And 7 element, a high potential is supplied from the output of the threshold unit 8. A high potential from the output of And 7 passes through the OR 10 element to the signal outputs of the device, the phasing input of the shift register 3 and the input of the clock generator 6. If there is a high potential at the input of the generator 6, the latter is in the off state.

 With the arrival of the starter parcel at the output of block 1, a low potential is established, which causes a low potential at the output of the threshold block 8, which causes a low potential in series at the second input and output of the And 7 element, at the output of the OR element 10 and, accordingly, at the signal outputs of the device, phasing input register 3 shift and at the input of the generator 6 clock pulses. Changing the potential level from high to low / zero / at the phasing input of shift register 3 provides the entry in the shift register 3 of the code combination "100 ... 0", i.e. “1” is written in the high order of register 3, and “zeros” in the other places. At the same time, at the outputs of the discharges, with the exception of the output of the senior discharge, from register 3, low potentials are established.

 The low potential from the output of the first least significant bit of shift register 3 prohibits the passage of high-level signals from the second input of AND element 7 to its output. The passage of high-level signals from the first and second inputs of the And 9 element to its output is prohibited by the low / zero / potential supplied from the zero potential bus through a closed key 11 to the third input of the And 9 element. The establishment of a low potential at the input of the generator 6 includes a generator 6. C generator output 6 clock pulses are supplied to the shift / synchronizing / inputs of the registers 3, 4, ..., 5 of the shift. The signals of the on-off code from the corresponding outputs of the code converter 2 are fed to the information inputs of the reception of the signals of the serial code of the registers 3, 4 ,. .., 5 shift. Under the action of clock pulses arriving at the synchronizing inputs of shift registers 3, 4, ..., 5, the code combinations of the received signal are recorded in the latter. After writing to the registers 3, 4, ..., 5 of the entire received code combination in the first low-order bit of the shift register 3, the "unit" is written, which at the beginning of the reception cycle was recorded in the high-order bit of register 3.

 The high potential from the output of the first low order bit of register 3 allows the passage of high potential from the second element And 7 to its output. The high potential at the second input of the And 7 element forms the threshold unit 8. The high potential from the And 2 output (after writing to the registers 3, 4, ..., 5 of the entire received code combination) passes through the OR 10 element to the signal outputs of the device and the input of the generator 6, which is turned on.

 The appearance of a high potential at the signal outputs of the device provides the input of the received code combination into the terminal device connected to the receiver, while the signal is not used from the output of the second least significant bit of register 3 of the shift, because in this category “zero” is written, which corresponds to the informationally insignificant premise “start”.

 With the arrival of a new starting package at the input of the device, the cycle of its operation is repeated.

Reception of messages transmitted in start-stop (see Fig. 2, b; d) and synchronous (see Fig. 2, c, e) modes by signals (2 ⁿ + 1) - position code.

The initial state of the device: threshold threshold block 8 - U ₁ , where u $\genfrac{}{}{0ex}{}{\text{<figure-callout id="2" label="n" filenames="00000002.png" state="{{state}}">n</figure-callout>}}{\text{2}}$ <<U ₁ <U (2 ⁿ + 1) (see Fig. 2, b - d), the key, 11 is open.

 The operation of the device (see Fig. 1) is similar to the above. At the same time, the device automatically adapts to various structures of the code combinations of the received messages (the structure of the code combinations of the messages in Fig. 2, b and c contains information-insignificant starting parcels; the structure of the code combinations of the messages in Fig. 2, d and e do not contain the starting parcels) required working register length 3.

 The choice / establishment / of the necessary working length of the register 3 is provided by the elements And 7 and 9.

 As can be seen from the description of the operation of the device and the frame structure of the received messages, the claimed device in comparison with the prototype has wider functionality, since it provides reception of messages transmitted in start-stop mode by three signal structures (see Fig. 2, a, b, d) and in synchronous mode by two signal structures (see Fig. 2, c, e).

Claims (1)

A device for receiving discrete information containing an input unit, the output of which is connected to the input of the code converter, the outputs of which are connected to the inputs of the signals of the serial code of the shift registers, the outputs of the information bits of which are the outputs of the device, the synchronizing inputs of the shift registers are connected to the output of the clock generator, the output the first low order of the first shift register is connected to the first input of the first element And, characterized in that, in order to expand the functional zmozhnostey by receiving messages transmitted signals (2 ⁿ + 1) -way code entered threshold unit, a second AND gate, an OR gate and a key block with a threshold input connected to the output of the input block, and output - with the first and second input first input the second element And, the second input of the second element And is connected to the output of the second least significant bit of the first shift register, the phasing input of which is connected to the input of the clock generator, and connected to the output of the OR element, which is the signal output of the device, inputs of the element OR connected to the outputs of the first and second AND gates, the third input of the second AND gate connected to the output switch coupled to the bus zero potential.

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