SU398945A1 - DEFAULT CODES - Google Patents

Description

ISO: Bribery refers to the computational tech nInIs: ke and is intended for code converters.

A decoder is known that contains matching schemes and a shift register; To eliminate interference (spurious emissions at the outputs of the ycTpoiV space), saudiadein gating output schemes are used with signals generated by a special discharge pulse generation circuit that complicates the devices.

The proposed device is distinguished by the fact that the first discharge discharge outputs of the first reverser; the corresponding counter is connected to the inputs; All the elements of the AND-NOT decoding unit, This allows us to simplify the device and increase its noise immunity by eliminating a special scheme for generating permissive pulses.

On the fit. 1 shows a diagram of the device; m of fig. 2 - time-methane stress diagrams.

The device contains a reversible counter 1 (in the current screen - two-bit) with bits 2 and L, a decoding unit 4, pulse inputs 5 and 6, 1 outputs 7. All logical nodes of the device are 1element; The reversible counter bits have potential outputs 9-12. The first digit of the counter has (pulse outputs .3 and 14 and PULSE input 15.

The operation of the device is described for the case when output signals appear at the output of a 6-decoder block; numbering of diagrams on fng. 2 corresponds to the numbering of the inputs and outputs of the elements of the device; in FIG. one.

The device works as follows. The sequence of input pulses is cher, input 15 is fed to the input of the first bit 2 of the reversing counter /.

Diagrams 9-12 (see Fig. 2) hara: they measure potential changes at the corresponding counter outputs /.

If there are no gating and multi-pulses at the output 16 of the decoding unit 4, corresponding to the number 2, a parasitic pulse appears (Diagram 16, a). When gating the elements of "AND-NOT 8 decoder block 4 signals from the immersive output /, the first bit 2 of the counter / the high pulse disappears (d11Ar1M.ma 16, b), since the element" AND-NOT 8, And meyun-1; output 16, is closed for a time equal to the duration of the pulse at output 13. The specified pulse appears at the inputs of the AND-HE 8 elements of the decoding unit 4 for the time t (the delay time of the electronic terminal IS-NOT 8) after the signals from the potential outputs 9 -12 counters / and overlaps potential potentials, at least by 2m. Since the transfer of the second and subsequent bits of the reversible counter / when working in a mode

summation occurs under the influence of even ampulses separated by wa output 13, bit 2, then to suppress parasitic; impulses: D0 statically stream the AND-NOT elements of the decoding unit with 4 pulses from output 13. Beli counter i / operating in the subtraction mode, the strobe pulse is removed from output 14.

Thus, the nep ibiii, bit 2, reversed 1 counter / is used as a scheme for developing permissive pulses.

P ip e d W e invented and

A code decoder (c), containing a decoding unit and a reversible counter, implemented on the potential logic elements "AND-NOT, the potential outputs of the bits of the reversible counter are connected to the inputs of the corresponding elements" AND-NOT decoding unit, characterized in that device and increasing its noise immunity, the pulse outputs of the first bit of the reverse counter are connected to the inputs of all elements of the AND-NOT DECISION block.