JPH0586690B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to digital data communication, particularly to a bit synchronization device for N-to-N loop transmission for implementing a bit synchronization method in loop-based N-to-N communication. be.

[Conventional technology]

FIG. 5 is a conceptual diagram showing the connection state of N-to-N loop transmission stations implementing the conventional loop transmission method,
In the figure, 31, 32, 33, and 34 are respective transmission stations, and 30 is a transmission line connecting each station 31, 32, 33, and 34, and information flows in the directions shown by the arrows.

FIG. 6 shows a conventional bit synchronization circuit, where S1 is information sent from the upstream station among the stations 31 to 34, and 1 is a clock generator that generates a sample synchronization clock C1 from the information S1. The circuit 2 is a memory circuit for sampling the information S1 using the synchronous clock C1, and the circuit S2 is the information that the memory circuit 2 sends to the next station.

Next, the operation will be explained. Information S from upstream station
1 is input to the clock generation circuit 1, a clock pulse C1 as shown in FIG. 8 is generated.
First few bits of data frame a, b, c, d
While the clock signal S1 is being input, the information S1 from upstream and the clock pulse C1 generated from it are not synchronized due to the delay in stabilizing the clock generation circuit, the data in the memory 2 is not fixed, and the output signal S2 is also not synchronized with the clock pulse C1. It becomes indeterminate as shown in Figure 8. Next, when the information S1 from upstream and the clock pulse C1 are synchronized, it becomes possible to obtain correct data as shown in e, f, g, . . . in FIG.

[Problem that the invention seeks to solve]

Since the conventional bit synchronization method is as described above,
In N-to-N communication without a master station as shown in FIG. 3, each time the transmitting station changes, the clock C1 of each station must be synchronized with the transmitted information S1. As shown in the frame diagram,
A flag 21 for synchronization is required for each information transmission, which poses a problem in that transmission efficiency decreases.

This invention was made in order to solve the above-mentioned problems, and is a method of bit transmission in N-to-N loop transmission that does not require resynchronization even if the transmitting station changes in N-to-N communication without a master station. The purpose is to obtain a synchronization device.

[Means for solving problems]

The bit synchronizer for N-to-N loop transmission according to the present invention monitors the generation timing of the sampling clock and the sending clock, and synchronizes the sampling clock between the generation of the sending clock and the next generation. occurs twice in a row, the transmit data latch/send circuit shifts the number of stages of the shift register into which the received information is read to the later stage, and the number of stages from the time the sampling clock is generated to the next time is increased. If the transmission clock is generated twice in succession, the transmission data latch/transmission circuit shifts the number of stages of the shift register into which the received information is read to the previous stage.

[Effect]

The bit synchronizer for N-to-N loop transmission according to the present invention transmits information from a transmitting station using the clock of the transmitting station, and in multiple stations, receives information from upstream and generates a clock from the received information as in the conventional system. The information is taken in, but the information is always sent to the downstream station at the clock timing of the own station, and the frequency error between the take-in clock and the sending clock is corrected by a data buffer on a frame-by-frame basis.
Once synchronized with the received information from the upstream station, there is no need to resynchronize even if the transmitting station changes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a clock generation circuit that generates a sampling clock C1 based on reception information S1, and 2A is a clock generation circuit that sequentially receives reception information S1 in synchronization with the sampling clock C1 generated by the clock generation circuit 1. , a shift register for shifting the reception information S1, 3 a transmission clock generation circuit for generating a transmission clock C2 for transmitting the reception information S1 received by the shift register 2A to the downstream station, 5 a transmission clock generation circuit for transmitting the reception information S1 received by the shift register 2A to the downstream station; The received reception information S1 is read from a predetermined number of stages (tap (number of stages) 14 at startup), and the reception information S1 is sent to the downstream station in synchronization with the transmission clock C2 generated by the transmission clock generation circuit 3. A transmitting data latch/sending circuit 4 monitors the generation timing of the sampling clock C1 generated by the clock generating circuit 1 and the transmitting clock C2 generated by the transmitting clock generating circuit 3, and determines whether the transmitting clock C2 is generated. If the sampling clock C1 is generated twice in succession between the time when the sampling clock C1 is generated and the next generation, the transmitting data latch/sending circuit 5 shifts the tap of the shift register 2A that reads the received information S1 to the subsequent stage. (For example, if it is set to tap 14, it will move to tap 15), and if the sending clock C2 is generated twice consecutively between the time when the sampling clock C1 is generated and the next time it is generated. In this case, the transmit data latch/send circuit 5 shifts the tap of the shift register 2A that reads the received information S1 to the previous stage side (for example, if it is set to tap 14, shifts to tap 13), and 6 is a frequency comparison circuit for transmitting data. The end of the received information S5 sent out by the data latch/sending circuit 5
When the flag 22 is detected, the transmission data latch/send circuit 5 sends a reset signal that controls the frequency comparison circuit 4 to reset the tap of the shift register 2A into which the received information S1 is read to a preset tap (tap 14 in this example). It is a detection circuit.

Next, the operation of the bit synchronization circuit having such a configuration will be explained using timing charts shown in FIGS. 2, 4, and 5. First, with reference to FIGS. 2 and 4, the case where the upstream station's sending clock frequency is higher than its own station's sending clock frequency will be explained.

A data frame as shown in FIG. 2 flows from upstream. 21 is this data frame,
22 is an end flag.

In FIG. 3, the received information S1 is always sent out by the transmitting clock of the upstream station and always has a constant phase. Therefore, in the steady state, the clock generation circuit 1 is synchronized, and the received information S1 In contrast, a stable information acquisition clock C1 is obtained. Note that during the first synchronization pull-in, such as when power is turned on, a synchronization error will occur several times because the data frame does not have a flag for synchronization, but synchronization will be achieved by retrying the data transmission. Be taken. Incidentally, when the power is turned on, etc., a flag for synchronization may be sent as in the conventional system. In this case, the above-mentioned synchronization error will not occur, so the data Transmission retry operations are no longer necessary.
And each tap 13, 1 of the shift register 2A
4 and 15, it is possible to obtain voltage pulses obtained by temporally delaying the received information S1 in synchronization with the clock C1, as shown in FIG.

On the other hand, using the own station's sending clock C2, the fourth
At the timing shown in the figure, the end flag 22 of the immediately preceding data frame is detected, the end flag detection signal S3 is output, and the frequency comparison circuit 4 outputs S4.
Reset the center tap to 14. From now on, in the frequency comparison circuit 4, the clocks C1 and C
Compare the two frequencies, and depending on the size,
Performs tap control of the shift register 2A. Also,
Since the pulses of the clocks C1 and C2 are generated alternately at the timing of ~ of the sending clock C2, the output S4 of the frequency comparator circuit 4 always indicates the voltage of the tap 14, and this center tap 1
Sampling of the transmission data is performed from 4 onwards, but since the pulse of clock C1 occurs twice consecutively between the timings of ~ on clock C2, this is detected in the frequency comparator circuit 4, and the output data is output from S4. The voltage command at tap 15 is output as a voltage command, and the sampling of the transmission data is performed from tap 15. As a result, the overshift of the shift register 2A by clock C1 is corrected, that is, the sending clock frequency of the upstream station is changed to that of the sending clock of the own station. Corrections are being made for cases where the value is higher than that. In this way, even if there is a frequency difference between the clocks C1 and C2, the data S5 sent to the downstream station is
will get you the correct one.

Further, the end flag detection circuit 6 detects the end flag, outputs an end flag detection signal S3, and resets the output S4 of the frequency comparison circuit 4 to the center tap 14 in preparation for the reception operation of the next frame.

Next, referring to FIG. 4, the case where the upstream station's sending clock frequency is lower than the own station's sending clock will be explained.

Similarly to the explanation in FIG. 4, at the timing of ~ of the sending clock C2,
2 occur alternately, so the output S4 of the frequency comparison circuit 4 always selects the tap 14, and the transmission data is sampled from this tap 14. Since no pulse is generated at all, the frequency comparator circuit 4 detects this, and outputs the voltage command of the tap 13 to the output S4. This correction is performed when the shift register 2A is not shifted, that is, when the upstream station's sending clock frequency is lower than that of the local station's sending clock.

Hereinafter, the reset operation using the end flag is the same as in the case of FIG.

In the above embodiment, the number of stages of the shift register 2A is three, but the number of stages can be set to any number as required.

Further, in the above embodiment, the frequency comparison circuit is reset by detecting the end flag for each frame, but even if the reset is performed every several frames or by providing a dedicated frame for reset,
It has a similar effect.

〔Effect of the invention〕

As described above, according to the present invention, information from a transmitting station is sent out using the clock of the transmitting station, and in multiple stations, clocks are generated and taken in from information received from upstream, and information is always transmitted to downstream stations. In addition to transmitting information at the clock timing of the own station, the configuration is configured to correct the frequency error between the clock for taking in these clocks and the transmitting clock for each data frame before transmitting. If it is synchronized with the clock of the received information from the master station, there will be no need to resynchronize the bits even if the transmitting station changes in N-to-N loop transmission without a master station, resulting in efficient data communication. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram of a bit synchronizer in N-to-N loop transmission according to an embodiment of the present invention, FIG. 2 is a data frame diagram of received information, and FIG.
4 and 4 are time charts of signals in each part of the circuit in FIG. 1, FIG. 5 is a conceptual diagram of N-to-N loop transmission, FIG. 6 is a block connection diagram for implementing the conventional bit synchronization method, and FIG. 7 is a conventional data frame diagram, and FIG. 8 is a time chart of signals of various parts of the circuit in FIG. 6. 1 is a clock generation circuit, 2A is a memory circuit (shift register), 3 is a transmission clock generation circuit, 4
5 is a frequency comparison circuit, 5 is a transmission data latch/send circuit, and 6 is a reset signal detection circuit.

Claims (1)

[Claims] 1. A clock generation circuit that generates a sampling clock based on the received information, and a shift register that sequentially receives the received information in synchronization with the sampling clock generated by the clock generation circuit and shifts the received information. , a transmission clock generation circuit that generates a transmission clock for transmitting the reception information received by the shift register to the downstream station, and a transmission clock generation circuit that reads the reception information received by the shift register from a predetermined number of stages, and A transmission data latch and transmission circuit that transmits information to a downstream station in synchronization with the transmission clock generated by the transmission clock generation circuit; a sampling clock generated by the clock generation circuit; and a sampling clock generated by the transmission clock generation circuit. The timing of occurrence with the sending clock is monitored, and if the sampling clock is generated twice in succession from the time when the sending clock is generated until the next time, the above sending data latch/sending circuit is activated. If the number of stages of the shift register that reads the received information is shifted to the later stage, and the sending clock is generated twice in succession between the time when the sampling clock is generated and the time when the next sampling clock is generated, When the transmit data latch/send circuit detects a frequency comparison circuit that shifts the number of stages of the shift register into which the received information is read to the previous stage side, and an end flag of the receive information sent out by the transmit data latch/send circuit, the transmit data A bit synchronization device for N-to-N loop transmission, comprising a reset signal detection circuit that controls the frequency comparison circuit to reset the number of stages of the shift register into which the data latch/sending circuit reads received information to a preset number of stages.