JPH0250665B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data transfer method for transferring parallel data between a transmitting side device and a receiving side device.

(Prior art) (1) The transmitting side device and the receiving side device transfer data while confirming a response using shake-in-hand.

(2) The transmitting side device and the receiving side device transfer data using the same clock signal.

Similar methods have been used.

Regarding (1), although there are advantages such as the fact that the clock frequencies of the two devices can be completely different and the distance between the two devices being large, the data transfer
Since a response is confirmed every time a large amount of data is transferred, this becomes an overhead and has the drawback of reducing the throughput of data transfer.

Regarding (2), data can be transferred using the same bandwidth as the clock frequency, so compared to (1), the data transfer throughput is improved and data transfer can be performed at high speed, which is an advantage, but the distance between the two devices is limited by clock frequency,
Since both devices use the same clock, each device is no longer independent, and a failure of the device containing the clock source causes a failure of both devices as a whole.

(Object of the Invention) The present invention has been made to solve these conventional problems, and its purpose is to speed up parallel data transfer between a sending device and a receiving device. The objective is to provide a data transfer method that can be used.

(Structure of the Invention) In order to achieve the above object, the present invention has a transmitting side device and a receiving side device having almost the same frequency but independent clock sources, and the transmitting side receives parallel data as well as a clock and a synchronization signal. The receiving side detects the phase difference between the clocks and adjusts the receiving clock to a phase that allows correct reception, and adjusts the receiving clock when receiving a synchronization signal periodically sent from the sending side device. In addition, in the transmitting side device, the data immediately after the synchronization signal is invalidated, which will be explained in detail below.

(Embodiment) Fig. 1 is a block diagram for explaining a preferred embodiment of the data transfer system of the present invention. It is composed of a source (OSC) 3 and a driver circuit 4. The receiving side device has reception buffer (RBUF) 5, A buffer (ABUF)
6, B buffer (BBUF) 7, receiver circuit 8,
Phase difference detection circuit (DET) 9, control section (CONT)
10, a multiplexer (MPX) 11, a clock source (OSC) 12, and a control section (CONT) 13.

On the transmitting side, the OSC 3 generates the φ1 clock shown in FIG. 2a and the φ2 clock shown in FIG _. There is a time difference of /2. Transmission data SDATA is sequentially sampled and held in SBUF1 by the φ1 clock. Similarly, SSYN is sequentially sampled and held in SBUF1 by the φ1 clock. This SSYN is
It is generated from SYN GEN2 in synchronization with the φ1 clock, and the details will be described later.

In this way, the data shown in FIG. 2c is sequentially sampled and held in the SBUF1. The data in Figure 2c is determined by the clock C1 of the φ1 clock.
The data is held by clock C2, and the data is held by clock C3. Here td is
This is the circuit delay of SBUF1. Although not shown, the same applies to SSYN. In Figure 2, SDATA is sampled at the rising edge of the φ1 clock, but this is just a rising edge for convenience.
Depending on the circuit of SBUF1, it can also be a falling edge. In the following description, it will be assumed for convenience only that all circuits that operate in synchronization with the clock operate on the rising edge of the clock.

On the receiving side, data and synchronization signals are RBUF
5 are sequentially sampled and held. This RBUF
5, the φ2 clock of the transmitting side OSC 3 is applied via the driver circuit 4 and the receiver circuit 8 as the φ2' clock of FIG. 2d, and sampling is performed.

To make it easier to understand the operation of the other circuits on the receiving side, we will explain here that the sending and receiving sides operate asynchronously using separate clocks (however, the clock periods are almost the same, and the receiving clock period is T _R ). Problems that sometimes occur during data transfer will be explained using FIG.

In FIG. 2, the φ2' clock is almost synchronized with the transmitter clock φ2 clock (FIG. 2b), although it is delayed due to transmission delay. but
The reception clock 1, which receives the data sampled and held by the RBUF 5, is asynchronous with the transmission clock, so the data sampling timing is not constant. Therefore, if the φ2' clock and the reception clock 1 deviate as shown in FIG. 2f or 2h, the setup time or hold time will not be available and normal reading will not be possible.

If such a situation occurs, it is conceivable to use a receiving clock 2 which has the same period as the receiving clock 1 but is time-shifted by T _R /2. By using the reception clock 2 in this manner, the sampling position is approximately at the center of RDATA, allowing normal reading. For this reason, in the present invention, the phase difference between the φ2' clock and the receiving clock 1 is detected and the phase difference is delayed or within a certain range in the advancing direction (indicated by ta in FIG. 2). In that case, RDATA is sampled using reception clock 2 instead of reception clock 1. Furthermore, the timing for detecting the phase difference is generated from SYN GEN2 on the transmitting side. This SYN
SSYN signal generated from GEN2 and φ1 clock,
The relationship with the SDATA signal is shown in FIG.

As shown in Figure 3, the SSYN signal is generated at a constant cycle (N clocks), and during one clock cycle when the SSYN signal goes from high level to low level, invalid data shown by the cross in Figure 3b is generated. It is sent out and used for phase difference detection on the receiving side. The invalid data sending timing and sending period are not limited to the example shown in FIG. 3, but considering the efficiency of data transfer, the shorter the sending period is, the better. It is better to increase the pulse interval of the SSYN signal to reduce the number of invalid data transmissions, but this increases the width of the phase change and there is a risk of erroneously detecting a phase lead or lag.

Next, the explanation of the operation of the receiving side circuit in Fig. 1 is shown in Figs.
This will be explained using FIG. 4 shows the case where the receiving clock 1 is shown in FIG. 2 f, FIG. 5 shows the case where the receiving clock 1 is shown in FIG. 2 h, and FIG. 6 shows the case where the receiving clock 1 is shown in FIG. This is a case where the difference between the transmitting clock and the receiving clock 1 is within the specified range.

In Fig. 4, a is the φ2' clock with period T _S , and b
is the SDATA′ signal of the input data of RBUF5, c is also the SSYN′ signal, and d is the output data of RBUF5.
RDATA signal, e is also RSYN signal, f is
The φX clock of the input clock of ABUF6, that is, the reception clock, g is the output data of ABUF6.
ADATA signal, h is also ASYN signal, i is
The BDATA signal of the output data of BBUF7, j is also the BSYN signal, k is the Valid signal of the output of CONT13, is the φA clock of the output of OSC12, m is the φB clock, and the φA clock and φB clock have the same period T _R , and are shifted in time by T _R /2.

In Fig. 4, the clock C1 of the φ2' clock,
RDATA signal by C2, C3, C4.
, samples of each data are held. Also, invalid data marked with an x is sampled and held by the clock Cx. Similarly, the RSYN signal is sampled and held by clock C2.
The ADATA signal and ASYN signal are sampled and held by the φX clock. At this time, as the φX clock, either the φA clock or the φB clock is selected by the MPX 11, but in FIG. 4, it is assumed for convenience that the φA clock is selected. When the ASYN signal becomes significant (eg, high level) at the C2 clock of the φX clock, DET9 checks whether the significant edges (rising edges in this embodiment) of the φ2' clock and the φX clock are closer than specified. Details will be described later. FIG. 4 shows a case where the φX clock has caught up with the φ2' clock and is approaching the φ2' clock more than the specified value, and in this case, the DET9 notifies the CONT10 that the F signal is significant (for example, at a high level).
This causes CONT10 to INH to MPX11 in synchronization with the φX clock during the period when the ASYN signal is significant.
Give the signal and PHASE signal. Details will be described later. The INH signal sent from CONT10 instructs to inhibit the clock Cx of the φX clock when the F signal of DET9 is significant. The PHASE signal also instructs phase switching at time A in FIG. 4f. Therefore, after time A, MPX 11 selects the φB clock and uses it as the φX clock. Note that the φX clock is not shown, but until the point A when the phase switches, the φB clock is out of phase with the φX clock by T _R /2.
After time A, the clock becomes the φA clock, which is out of phase with the φX clock by T _R /2, and MPX11.
is output from. Details regarding these will be described later. ADATA signal and ASYN signal of ABUF6 are φX
After being sampled and held by the clock as shown in Figure 4g and h, the BDATA is then sampled by the φA clock.
The BSYN signal is sampled and held as shown in Figure 4 i and j, and the synchronization between the received data and the receiving clock is completed, but the received data has a difference between it and the data as shown in Figure 2 b. Invalid data marked with an "x" is inserted into the BDATA signal, and the data of the BDATA signal shown in FIG. The Valid signal is used for this purpose, and after one clock period has elapsed since the BSYN signal became significant based on the BSYN signal in CONT13, the BDATA signal is sampled while the BSYN signal continues to be significant. The Valid signal shown in FIG. 4k is switched so that this is not performed.

Therefore, the receiving side only needs to sample the BDATA signal using the φA clock or φB clock when the Valid signal is significant (for example, high level).
, and significant data can be continuously received.

Figure 5 shows the case where the φ2' clock is catching up with the φX clock and is closer than the specified value.
DET9 makes the B signal significant. This results in
CONT10 does not make the INH signal significant and immediately changes the PHASE signal at time A to switch the phase.
The other difference from Figure 4 in the explanation is that in this case, no extra data is sampled between the BDATA signal and the data, so Figure 5 i shows
The Valid signal remains significant.

Figure 6 shows a case where the phase difference between the φX clock and the φ2' clock is within the specified range, and the received data can be read normally in this state.
In this case, neither the F signal nor the B signal is significant. This causes CONT10 to inhibit clock Cx, but
Unlike the case in FIG. 4, at time A, the PHASE signal is not changed and the phase is not switched. And Valid
Signals are controlled in the same manner as in FIG.

Next, the operation of the DET9 in FIG. 1 will be explained in more detail. However, what I will explain here is
This is just one example for understanding the above-mentioned operation of the DET 9, and it goes without saying that the above-mentioned operation can also be performed by other methods.

FIG. 7 shows the internal circuit of the DET 9, and the timing generation circuit 91 generates the A output shown in FIG. 9e.
This signal is low during the rising edge _t1 of the φ2' clock and remains high until the next rising edge. DLY92 generates the B output of FIG. 9b. This signal is the φX clock shifted by _t2 hours. The timing generating circuit 93 generates the C output shown in FIG. 9f. This signal is high for time _t3 after the rising edge of the φ2' clock and is low until the next rising edge.
DLY94 generates the D output of FIG. 9c. This signal is the φX clock shifted by _t4 hours.
In the above, times t ₂ and t ₄ define the limit of the phase difference between the φ2' clock and the φX clock. Figure 9 shows a case where the time from clock C1 of the φX clock to clock C2 of the φ2' clock exceeds the specified _t2 hours, that is, when the φX clock catches up to the φ2' clock and approaches it more than the specified value. The B output rises within the range where the A output is at a high level. Therefore, if the ASYN signal goes high in this state, the slip-flop (F・F)
The F signal output from the circuit 95 becomes high level as shown in Fig. 9f, which means that the ASYN signal becomes low level and the FF
It remains high until 95 is forced to reset. On the other hand, since the rise of the D output does not occur within the range where the C output is high level, the B of FF96
The signal (FIG. 9i) remains at a low level. Further, this FIG. 9 corresponds to the state shown in FIG. 4 described above.

FIG. 10 corresponds to the state shown in FIG. 5, and is a case where the φZ' clock catches up with the φX clock and approaches the φX clock more than the specified value.
It becomes like i.

FIG. 11 corresponds to the state shown in FIG. 6, which is a case where the phase difference between the φX clock and the φZ' clock is within the specified range, and the F signal and B signal become as shown in FIG. 11h.

FIG. 8 is a circuit diagram showing the details of CONT 10 in FIG. , F signal or B signal becomes high level, the PHASE signal is switched only by the first φX clock as shown in FIGS. 9k and 10k. In FIG. 11, since both the F signal and the B signal remain at low level, the PHASE signal is not switched. On the other hand, the differentiating circuit 103
The significant state of the ASYN signal is pre-differentiated by one clock and is set to a low level by one clock of the φXC clock. The output of the differentiating circuit 103 and the B signal are input to a two-input OR circuit 104, and
The switching of the INH signal is controlled as shown in FIG. j and FIG. 11i.

For MPX11, this INH signal is significant (low level)
When , the clock pulse signal is suppressed and the PHASE
The φA clock and φB clock are selectively output according to the signal.

In Figures 9 to 11, the φX clock and φZ' clock are closer than specified (Figures 9 and 1).
0), it is desirable to set the times t ₁ to t ₄ so that the F signal or the B signal becomes significant and phase switching is performed.

At this time, when the F signal and the B signal become significant at the same time, the PHASE signal switches as shown in FIG. 8, but the INH signal does not become significant and the same operation as in FIG. 10 is performed.

Next, the relationship between the synchronizing signal sending period N (see FIG. 3) and the width of the phase difference detection band will be considered. Figure 12 shows a case where the φ2' clock period T _S is slightly larger than the φX clock period T _R (T _S > T _R ) and the φX clock approaches the φZ' clock in a manner that it catches up with it, which is the case in Figure 4 described above. This corresponds to 13th
The figure shows a case where the φX clock period T _R is slightly larger than the φ2' clock period T _S (T _R > T _S ) and the φZ' clock approaches in such a way that the φX clock catches up, which corresponds to the case in Figure 5 above. It is something to do. 12th
As can be seen from Fig. 13, the phase differences between the two clocks t ₁ , t ₂ , t ₃ , t ₄ , t ₅ decrease by | _{T Since} the phase relationship _{between the} two clocks must not be reversed until a periodic signal of Here the right side
T _R /M is the width of the phase difference detection band and is expressed as 1/M of the receiving side clock period T _R .

With a crystal oscillator, a frequency accuracy of about 10 ^-4 can be easily obtained, so ｜T _R rT _S ｜ T _R ×2 × 10 ^-4 From this, N≦1/(M × 2 × 10 ^-4 ) Let M be 8. Then, N≦625 When N=625, the data transfer rate is 1/625, or 0.16%, lower than the bandwidth at the same clock frequency due to the influence of invalid data immediately after the synchronization signal.

That is, in this embodiment, a data transfer rate of 99.84% of the bandwidth can be obtained without changing the clock frequency.

(Effects of the Invention) As described above in detail, the transmitting side device and the receiving side device have almost the same frequency, but each has an independent clock source, and the transmitting side receives parallel data as well as a clock and a synchronization signal. The receiving side detects the phase difference between the clocks and adjusts the receiving clock to a phase that allows for correct reception, and adjusts the receiving clock when receiving a synchronization signal periodically sent from the transmitting side device. In addition, the data immediately after the synchronization signal is invalidated by the transmitting device,
It has the advantage of being able to transfer data without data dropout using a bandwidth that is almost the same as the clock frequency.

Furthermore, since the phases of the data (and synchronization signal) and transmission clock can be set appropriately on the transmitting side, only signal waveform distortion is a problem, and there is no effect of propagation delay, so the distance between the two devices can be relatively large. There are advantages.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a transmitting side device and a receiving side device in a preferred embodiment of the present invention, and FIGS. 2 to 6 and 9 to 13 are diagrams for explaining the operation of FIG. 1. 7 is a schematic block diagram of the phase difference detection circuit 9 in FIG. 1, and FIG. 8 is a time chart diagram.
1 is a schematic block diagram of the control section 10 shown in FIG. 2...Synchronization signal generator, 3...Clock source, 9
... Phase difference detection circuit, 10, 13 ... Control section, 1
1...Multiplexer, 12...Clock source.

Claims (1)

[Claims] 1. In a data transfer method in which parallel data is transferred between a transmitting device and a receiving device, the transmitting device and the receiving device have almost the same frequency but each has an independent clock source. The transmitting device sends a clock and synchronization signal along with parallel data with invalid data inserted immediately after the synchronization signal, and the receiving device transmits the synchronization signal when it receives the synchronization signal periodically sent from the transmitting device. A data transfer method that detects the phase difference between a clock and a receiving clock, adjusts the receiving clock to a phase that allows correct reception, and transfers parallel data.