JPS5828982B2 - Digital signal regeneration repeater - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a self-synchronized digital signal regeneration repeater, in which a timing signal is generated by an input drive method with high phase stability when receiving data, and the output signal is free from timing jitter. It is an attempt to improve the performance of the device by using a less output driving method and by eliminating the need for output based on timing signals.

A large number of regenerative repeaters are used to transmit digital signals, and these regenerative repeaters require a synchronization signal (timing signal) to identify the presence of an input signal.

Conventional synchronization signal transmission methods include self-synchronization, external synchronization, and the like.

The external synchronization method is a method of sending a synchronization signal to a line separate from the signal (data) line, and requires a line for the synchronization signal.

On the other hand, the self-synchronization method generates a timing signal from its own signal pulse itself, and does not require a synchronization signal line.

For this reason, self-synchronization methods are more widely used.

There are two types of self-synchronization methods: an input drive method that obtains a timing signal from an input signal pulse train, and an output drive method that obtains a timing signal from an output signal pulse train.

The input drive method has good phase stability of the timing signal obtained from the received signal, and the output drive method has less timing jitter, each having advantages and disadvantages.

Now, as shown in Figure 1, when the signal is logic ``1'', as shown in 101 for the original signal 100, the polarity is not reversed at the center of the time slot, and when the signal is logic ``O'', the polarity is not reversed at the center of the time slot. As an example, a case will be explained in which transmission and reception are performed using a timing signal whose polarity is inverted at the center of the time slot and whose polarity is inverted from that of the adjacent pulse at the end of the time slot.

Reference numeral 200 in FIG. 2 is a received signal from a transmission path, and in the input drive method, a timing wave shown at 201 is created from a pulse train of this signal.

This timing wave 201 is generated by counting a certain period of time from the start point of each bit of the received signal 200, as shown by 202.

However, since the elements of the received signal 200 are subject to distortion due to noise and various distortions in the transmission path, the 200
As shown in Figure 2, the distance between bits is not constant, and a phenomenon called timing jitter is unavoidable.

Therefore, in order to reproduce and relay, as shown in Figure 3a (this,
An N-bit shift register 300 is provided, and the N bits of the received signal are temporarily stored in the shift register 300 in response to the shift pulse from the timing wave generation circuit 301, and then the output pulse from the internal basic clock generation circuit 302 is stored in response to the output pulse from the internal basic clock generation circuit 302. It is common to extract data from the shift register 300 and send it out.

However, in the circuit shown in FIG. 3A, nothing can be done until the relay reproduction operation is performed until the received signal is stored in the shift register 300, so that the relay reproduction operation ends after the storage.

Furthermore, since the capacity (N bits) of the shift register 300 is determined in advance, the number of bits that can be continuously transmitted and received is limited.

It has drawbacks such as. Furthermore, even in the case of other conventional circuit repeaters that do not have a buffer, such as a shift register, those that adopt this input drive method have the disadvantage that the data length is limited due to considerations with timing jitter.

Next, in the output drive method, an output signal 200 is generated by a synchronization timing signal shown at 203 with respect to the received signal 200 in FIG.
4 is output and relayed.

An output circuit using this output drive method is shown in FIG.

This output circuit includes the internal basic clock generator 30 of the repeater.
3, and a timing wave generation circuit 304 that generates a timing signal from the signal from the basic clock generator 303.

Initially, a timing wave is generated from the timing wave generation circuit 304 for the received signal, and the received signal is sampled by the circuit 305 based on the timing signal.
A sampling signal is output from.

This method is also called the start-stop synchronization method, and its advantage is that the timing of the output signal is small, but it has the following drawbacks.

Since the frequency of the received signal is different from the frequency of the basic clock of the repeater, errors occur when the signal is continuously relayed.

Since noise and various distortions in the transmission path must also be taken into account, the number of bits that are continuously transmitted and received must be limited in advance.

The present invention has been developed in view of the above circumstances, and therefore uses an input drive method with good phase stability when receiving data, and also ensures that the relay operation is within 1/2 bit time of the received data and does not cause timing jitter. The present invention attempts to provide a regenerative repeater that uses an output drive method for the I/O output signal and has an internal number memory to compensate for the timing difference between the input operation and the output operation.

Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 4 is a diagram showing the overall configuration of the present invention.

In the figure, 400 is a receiving section, 401 is a timing signal generator that detects changes in the received signal and generates timing pulses for reception, 402 is a transmitting section, and 403 is a timing signal generator that detects the presence or absence of the received signal and generates timing pulses for output signals. This is a timing signal generator that generates.

404 is an 1-bit register that stores the received signal according to the timing pulse sent from the timing signal generator 401, and 405 is a register file that temporarily stores the received signal when the received signal is slightly earlier than the relay transmitted signal.

406 looks at the states of the timing signal generators 401 and 403 and the register file 405, and determines whether to apply the input signal to the register file 405I, the signal from the receiver 400 or the output signal from the register 404; It is a timing signal generator that generates the set timing signal.

Details of each part will be explained below with reference to FIGS. 5 to 8.

FIG. 5a is a detailed diagram of a portion corresponding to the receiving section 400 of FIG. 4, and as shown in the timing chart of FIG.
It outputs signals BUFA and BUFB synchronized with the basic clock BCLK to PUT.

In addition, rl shown at the end of each signal name in Figures 5 to 10
j, rOJ indicates that the signal is active when it is logic '1' or '0'.

FIG. 5 is a detailed diagram of a portion corresponding to the transmitter 402, which operates depending on the timing signal 5CLKK9) sent from the timing signal generator 403.

Figure 5 a, b! Here, the signal CD output from the receiver 400 to the timing signal generator 401 is a signal that captures the BUFA and BUFf3@ signals.

Further, the BSY signal is a signal that becomes active when either the reception signal output from the reception section 400 or the output signal output from the transmission section 402 is present. Timing signal generator 403! This will be sent.

However, in FIG. 4, the BSY signals are RBSYA, B (receiving side), and DBSYA.

It is indicated as B (sending side).

J-KF/F 600.601 in FIG. 6a corresponds to the 1-bit register 404, and the J-KF/F 600.601 in FIG. 5a! BUFA and BU sent from the receiver 400 shown here
The FBfH signal is latched at the falling edge of the LD signal from the timing signal generator 404.

Also, FIG. 6 corresponds to the register file 405.

In the register file 4051, registers 603 to 610 are used to store data, and registers 611 to 614 are circuits that control which of the registers 603 to 610 stores data.

Data is set in the registers 603 to 610 when the SET signal from the timing signal generator 406 is active ('1''). For example, in the initial state, SE
When the T signal becomes active, data from F/Fs 600 and 601 is loaded into registers 606 and 610.

As shown in FIG. 10, when the SET signal is active, the 5ETST signal is always active, so register 6
14 xi Set in response to the falling edge of the BCLK signal,
Its output FUL1tl becomes active.

The next 5 ETST signals S from the timing signal generator 406
When the ET signal arrives, the data in registers 606 and 610 are held as they are, and F/F6 is transferred to registers 605 and 609.
The data from 00.601 is set, and at the same time register 613 is set and its output becomes active.

Similarly, registers on the right (606, 610) -→
F/F600 in the order of (605, 609) →...
, 601 is set.

On the other hand, registers (606, 610), (605, 609)
, (604, 608), and (603, 607) are read out using the 5 output from the timing signal generator 403.
Controlled by CLK and CB signals.

The register (603
,607) → (604°608) → (605,609)
→ (606, 610), and are shifted to the right one bit at a time, and sequentially read out from the final stage register (606, 610).

In response to this reading, registers 611 to 614 are set to register 6.
11. It is reset by the CB signal from the timing signal generator 403 in the order of 612, 613, and 614.

As can be seen from the above explanation, since the manual data is set from the right side in FIG. 6, it is more efficient than using a conventional shift register to retrieve the data.

Also, the received signal BUFA, BUFB or F/F 600, 6 is generated by the GA multiplied signal from the timing signal generator 406.
The output of 01 is sent to registers 603-611 of register file 405 in FIG.

FIG. 7a shows a circuit corresponding to the timing signal generator 403, in which the BSY signal from the receiver 400 and the transmitter 402 is
While the signal is active, the three J-KF/Fs operate as quinary counters in synchronization with the basic clock signal BCLK, and the 5CLK and CB signals are transferred to the register 60 in FIG.
3 to 614.

The reason why this circuit uses a quinary counter is to reduce the time of one bit of data to 1/10.

Then, if either the received signal or the output signal is present, the BSY signal becomes active, and as shown in Figure 9, the midpoint of the quinary count (between counts 2 and 3)
generates a timing pulse 5CLK that becomes active.

As described above, timing pulses 5CLK and CB are used as control signals for reading data from registers 603-610 in FIG.

FIG. 1 shows a circuit corresponding to the timing signal generator 401, which counts the CD signal sent from the receiver 400 in synchronization with the basic clock signal BCLK to generate timing pulses LDc! :An octal counter that generates CA.

The timing pulses LD and CA become active when the count values are 2 and 7, as shown in FIG.

The octal counter of this timing signal generator 401 constantly counts from the bit start point of the received data, and the timing pulse LD is sent to the 1-bit register 40.
4, the bits are synchronized, so registers 600 and 601 (i.e., register 4
04) is set to data with good phase stability.

By the way, the 5CLK signal output from the timing signal generator 403 and the LD signal output from the timing signal generator 40'1 may become out of phase if the relay operation continues.

In FIG. 9, the timings 900 and 901 have different phases.

Therefore, in the present invention, in order to reduce the timing jitter of the transmission signal, data reading from the register file 405 and transmission control of the transmitter 402 are performed in synchronization with the 5CLK signal.

A register 404 and a register file 405 are provided to compensate for the phase shift between the 5CLK signal and the LD signal.

If the 5CLK signal and the LD signal are in phase, there is no need to temporarily set the received data in the register file 405.

However, if the phases do not match, the received data must be set in the temporary register file 405.

The transmitter 402 receives the BUFA sent from the receiver 400.
, B[JFB signal and RO read from register file 405 (JTA, ROUTB signal is selected, but if data is set in register file 405, FU from register file 405
The ROUTA signal and ROUTB signal are selected by the L1 signal.

The operation of the timing signal generator 406 shown in FIG. 8 will be explained with reference to FIG. 10.

Note that the explanations of (1) to (6) below refer to 1 to 6 in Figure 10.
It corresponds to the timing diagram.

(1) If not even one bit of data is stored in the register file 405, the FUL1 signal is in the “0” state, and the C signal sent from the timing signal generator 401 is
When the A signal and the CB signal sent from the timing signal generator 403 become active (logic "1" signal) at the same time, the transmitter 402 outputs the B signal as shown in FIG.
Since the UFA and BUFB signals are selected, there is no need to store the received data in the register file 405, so the timing signal generator 406 activates the 5ETST signal, SET signal, and GA signal output to the register file 405. do not.

(2) CA-1”CB in the state of FULl-’0”
− In the case of “0”, the received data from the receiving unit 400 needs to be temporarily stored in the register file 405.

Therefore, in Figure 6, GAO-l", 5ETST-
'1', 5ET must be set to 'l'.

5ETST="l" causes the FUL 1 signal of the register file 405 to become active at the falling edge of the basic clock signal BCLK.

Thereafter, when an output timing wave is generated, the CB signal becomes active.

Since FULl-“1”, read data ROUTA from the register file 405 is sent to the transmitter 402.
, ROUTB is sent (l!:(!l-).

When CB=''l'', the FUL1 signal is reset at the fall of the basic clock signal BCLK.

(3) When the FUL1 signal is "1", one or more bits are stored in the register file 405.

First, when CB-"1", CA-O'", FtJLl-1
” Therefore, the read data ROUTA and ROUTB from the register file 405 are sent to the transmitter 402.

CB-1", the FUL1 signal is J-KF/F61
If 3 is set, it remains active, but if J-KF/F513 is set, FUL
The i signal is reset.

After that, when CA-"l" and CB-'0", the received data BUFA and BUFB must be stored in the register file 405, so GAO='"l", 5ETST
-l''.

(4) In the state of FULl-“l”, CA-“1”, CB-
When '0', transmit data BUFA, B as in (2)
UFB must be stored in register file 405.

After that, even if CA-"'0" and CB="O", the transmitter 402 selects the read data ROUTA and ROUTB from the register file 405 because it is FULl-1".

(5) When FUL1="O", CA-"0"CB-1
”, the transmitter 402 selects the received data BUFA and BUFB from the receiver 400.

This condition occurs after the receive signal has ended, when the output signal is still present and the BSY signal is active.

This completes the relay operation.

Thereafter, when CA="1" and CB"0", the received data BUFA and BUFB are stored in the register file 405.

This is similar to (2).

(6) CA-“1”, CB= in the state of FUL1=“l”
When “l”, the transmitter 402 sends the register file 405
Read data from ROUTA.

Select ROUTB.

At the same time, received data BUFA and B from the receiving section 400 are also received.
UFB must also be stored in the register file 405, but since activating the SET signal at the same time as the 5CLK signal is dangerous in terms of timing,
Receive data BUFA by signal.

Store BUFB to J-KF/F600.601 (i.e., register 404) and store J-KF/F600.601 (i.e., register 404) in the next timeslot.
The contents of KF/Fs 600 and 601 are stored in the register file 405 (GA1'1'').

J-KF/F If 613 is reset, CB-
``l'' causes FULl-'0'', but in the next time slot a 5ETST signal is issued, so FUL1 again.
=“1”.

As described above, the timing signal generator 406
, SET, and GA signals.

In addition, GAl-"1" is FULI-1"CA=
"l", CB-1", only in the next time slot, each signal of 5ETST and SET becomes active in GAl-1?1 or GA-1-0", and CA-
This is the time of "l", CB-0".

As is clear from the above, the digital signal regeneration repeater of the present invention has the following advantages.

(1) Phase stability is high because the timing wave for reception is created by capturing changes in the received signal and counting for a certain period of time from the start point of each bit.

(2) The capacity of the register file can be determined by taking into account the stability of the own oscillator, the noise of the transmission line, and various distortions, and there is a degree of freedom in the number of bits that can be continuously transmitted and received.

(3) Since the received signal is not necessarily input into a shift register, the reproduction speed is improved.

(4) Since the output signal is output using a timing wave synchronized with this, the timing jitter of the output signal is small.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram showing the relationship between the original signal and the transmitted signal;
The figure is a waveform diagram when a timing wave is generated from a conventional received signal, Figure 3a is a block diagram showing a conventional receiving circuit, Figure 3 is a block diagram showing a conventional transmitting circuit, and Figure 4 is a block diagram of the conventional transmitting circuit. A block diagram of the relay device of the invention, FIGS. 5a and 5b are the receiving section 400 of FIG.
, a detailed circuit diagram of the transmitter 402, FIGS. 6a and 6b are detailed circuit diagrams of the register 404 and register file 405 in FIG. 4, and FIGS. 7a and b are detailed circuit diagrams of the timing signal generator 40L in FIG.
403, FIG. 8 is a detailed circuit diagram of the timing signal generator 406 of FIG. 4, and FIGS. 9 and 10 are waveform diagrams of each signal. 400...Reception section, 401...Reception timing signal generation section, 402...Transmission section, 4
03...Transmission timing signal generation section, 404
... Register, 405 ... Register file, 406 ... Set timing signal generation section.

Claims (1)

[Claims] 1. A receiving circuit that synchronizes the received signal and captures changes in the received signal, a receiving timing signal generation circuit that generates a timing wave to take in the received signal using an input drive method, and a receiving circuit that synchronizes the received signal and captures changes in the received signal. A register file that temporarily stores the received signal data when it is slightly faster than the transmitted signal, a transmission timing signal generation circuit that captures the start of the received signal and generates a timing signal for the transmitted signal, both timing signal generation circuits and the register. A set timing signal generation circuit that generates a set timing signal for the register file by looking at the state of the file, and a transmitting circuit that selects whether the output of the receiving circuit or the output of the register file is collapsed and transmits the selected signal. A digital signal regeneration relay device characterized by: