WO2004046943A1

WO2004046943A1 - Signal processing circuit

Info

Publication number: WO2004046943A1
Application number: PCT/JP2002/012069
Authority: WO
Inventors: Hiroyuki Rokugawa; Masaaki Kawai
Original assignee: Fujitsu Limited
Priority date: 2002-11-19
Filing date: 2002-11-19
Publication date: 2004-06-03

Abstract

Data identification is performed for each of parallel input data signals by a predetermined clock signal. From the phase of the clock signal used for the data identification, a phase relationship with a predetermined phase is calculated. The parallel input data signals after the aforementioned identification are phase-shifted by a predetermined amount decided according to the detection phase relationship.

Description

Description Signal processing circuit Technical field

The present invention relates to a signal processing circuit, and more particularly, to a signal processing circuit that can efficiently realize synchronous processing of parallel signals. Background art

With the development of communication technology, high-speed signal transmission technology is being introduced not only in trunk systems but also in offices and subscriber systems, and as a result, the application area of broadband information transmission such as moving images has been dramatically increased. Is spreading. Along with this, the technology for transmitting large-capacity signals in systems or equipment is becoming important, not only in communication systems but also in information systems.

In communication and information systems, many ^^ signals form a meaningful information sequence by using multiple signals such as pite. As a technology for transmitting large-capacity signals at high speed, there is a technology to collectively parallelize multiple signals. However, between a signal that transmits a number of parallel β-mediums and a number of parallel signals are transmitted at once through a plurality of transmission media, the receiving unit is affected by the propagation time of each ^ ¾ media. When a signal is received at, it is difficult to perform data by matching the phases between the data signal and the figij clock signal. That is, if the clock signal is transmitted from the speaker side in parallel and used in the receiving unit for signal identification. Since the temporal phase condition of the propagated signal is unknown in the receiving unit, it is unknown. In some cases, data cannot be received in the correct phase.

For this reason, the transmission / reception system for parallel signals, especially the receiver, receives the transmitted signal correctly.

In order to properly perform signal processing on the signal after receiving it, it is necessary to enable signal processing with a common mouth signal. Therefore, it is necessary to perform a so-called synchronization process for aligning the phases between the parallel data in advance. It becomes important.

FIG. 1 shows an example of a configuration for performing parallel signal reception and synchronization processing. In general, in a parallel transmission system, as described above, the propagation delay time of each transmission medium varies, so that a finite variation (skew) occurs in the phase of the received data on the receiving side. When the receiver receives this parallel signal, it is necessary to apply a signal having an appropriate phase relationship to the received data as the identification cook signal to perform the identification processing.

At this time, the phase of the signal input to the receiver differs according to the transmission characteristics of the channel, and the phase of the output signal after data identification corresponds to the used identification (acquisition) phase. Will be different. In a normal transmission system, as described above, it is necessary to identify the received parallel signal with a clock signal of a common phase and then perform synchronization processing for transfer to the next processing circuit. However, as described above, it may be practically impossible to perform synchronization processing on an identification signal having a different phase with a clock signal having a common phase as it is.

For this reason, there is a method in which the received signal is separated into low-speed (low-rate) signals for each signal on each transmission line (channel) once, and then synchronization processing between channels is performed. However, in this case, a large-scale circuit is required for performing a synchronization process for searching for a bit that can be processed by a common-phase clock signal in many low-speed signals. Such a tendency becomes more remarkable especially as the speed of the data on each transmission path increases.

In addition to such a method, a method is conceivable in which a FIFO for converting the identification signal into a signal having a phase corresponding to the clock signal on the system side of the receiving unit is provided after the 段 ^ processing in the receiving unit. . However, when a FIFO is applied, a large number of memory areas are required to absorb the phase difference between signals, and the FIFO has a structural write / read speed limit. The processing speed is reduced. Disclosure of the invention

In view of such a situation, the present invention considers that when receiving parallel signals for each channel, After identifying the received data with a clock signal that has a unique phase, the signal processing circuit is simplified to perform synchronization processing that aligns the phase of the identified signal to the extent that signal processing with a common clock signal is possible. It is intended to provide a simple circuit configuration.

In order to achieve the above object, the present invention has a configuration in which a phase relationship between parallel input data signals is detected, and each data signal is phase-shifted by a phase shift amount corresponding to the detected phase relationship. With this configuration, it becomes possible to synchronize parallel data signals at high speed with a simple configuration. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram for explaining synchronization of parallel data signals.

FIG. 2 is a schematic block diagram of a signal processing circuit according to one embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of each identification / phase shift unit in FIG. FIG. 4 is a diagram showing an example of a circuit configuration applicable to the identification / phase difference detection unit in FIG. 5A and 5B are diagrams for explaining the principle of detecting a data signal change point by the circuit example shown in FIG.

FIG. 6 is a circuit diagram (part 1) illustrating a circuit configuration example of the phase difference control unit in FIG. FIG. 7 is a circuit diagram (part 2) illustrating a circuit configuration example of the phase difference control unit in FIG. FIG. 8 is a diagram for explaining the operation of shifting the phase of the data signal after identification to the phase of a predetermined synchronization signal.

FIG. 9 is a time chart as an example in which phase information is represented by digital values.

FIGS. 10A and 10B are diagrams for explaining a configuration example of the phase shift unit in FIG.

FIG. 11 is a circuit diagram showing a general circuit example applicable to the flip-flop circuit shown in FIG. 10B.

FIG. 12 is a diagram for explaining a cook signal applicable to the embodiment of the present invention.

FIG. 13 is a circuit diagram showing an example of a counter circuit for expressing the phase of the click signal shown in FIG. 12 by a digital value. FIG. 14A is FIG. 14B, and FIG. 14C is the digitally expressed phase information of the click signal shown in FIG. 12 which can be applied to the embodiment of the present invention. FIG. 7 is a diagram for explaining an example of a control signal and a phase shift control signal, and an example of a rule for determining assignment of a phase shift amount of a two-stage phase shift unit.

FIG. 15 is an operation flowchart for explaining the operation of the embodiment of the present invention. FIG. 16A, 16B, 16C, 16D, 17A, 17B, and 17C show the detection of the phase relationship between the identification data signals and the amount of phase shift according to the embodiment of the present invention. It is a time chart for explaining the determination and the phase shift operation by the two-stage phase shift unit. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 2 shows a schematic configuration of a signal processing circuit according to one embodiment of the present invention. The signal processing circuit includes an IJ / phase shift processor 3, a synchronization processor 4, and a clock generator / separator 2. The circuit collectively receives n-channel parallel signals DA-1, DA-2,..., DA-n transmitted in parallel via a predetermined transmission medium in a communication network, an information processing circuit, or the like. This is a circuit for performing data m and synchronization processing.

Here, these parallel signals are signals having a predetermined relationship with each other, for example, bit information, and proper processing can be obtained by being processed in synchronization with each other. Then, the circuit performs synchronization processing, that is, the phase difference between them is kept within a predetermined range, so that when a predetermined signal processing is performed in a signal processing circuit in a subsequent stage, processing using a common clock signal is performed. It becomes possible.

In FIG. 2, n-channel parallel signals DA-1, DA-2,..., 0-11 are first processed by the phase shift processing unit 3. The processing unit 3 is composed of n key IJ / phase shift processing units 3-1, 3-2,..., 3-n as many as the number of parallel signal channels. Each time, the data of the received signal is changed by a clock signal, and the phase of the signal of the shifted data is shifted by a predetermined amount as described later.

Further, the clock generation distribution unit 2 obtains the clock signal for data identification by internally generating or inputting the clock signal from outside, and distributes the clock signal to a predetermined circuit block including the phase shift processing unit. The synchronization processing unit 4 converts the modulation data signal output from the phase shift processing unit 3 into a clock signal having a common phase. Synchronization between signals is achieved by performing identification processing.

FIG. 3 is an internal block diagram of the unit 3-1 in the identification / phase shift processing unit. The other units 3-2, 3-3,..., And 3-n have the same configuration as the unit 31, and a duplicate description will be omitted. The identification / phase shift processing unit 3-1 includes an identification Z phase difference detection unit 21, a phase control signal generation unit 22, and a phase control unit 23-1, 23-2, 23. —3, a phase shift control signal generator 24, and phase shifters 25-1, 25-2.

In the signal processing circuit according to the present embodiment, the received data is subjected to clock generation in each of the identification / phase shift processing units 3-1, 3 -2,. Each of them is identified by the clock signal generated / distributed by the / distribution unit 2. Further, in each of the identification / phase shift processing units 3-1, 3-2,..., 3-n, the signal is processed to the extent that the synchronous identification processing can be performed by the common synchronization signal in the subsequent synchronization processing section 4. Adjust the data signal phase after identification so that the inter-channel phase difference is small and ideally zero. In the synchronization processing unit 4, the identification data signals from the identification / phase shift processing unit units 3-1, 3-2,..., 3-n are synchronously identified by a common clock signal.

In the above-described embodiment of the present invention, as described later, the phase of the data signal after identification in the identification / phase shift processing unit 3-1, 3-2,. The phase is shifted and output until it has an appropriate relationship with the phase of the cook signal. Hereinafter, the operation of the identification / phase shift processing unit 3-1 will be described with reference to FIG. The other units 3-2 to 3-n also operate in the same manner as the unit 3-1, and duplicate explanations are omitted.

In the figure, an identification / phase difference detection unit 21 identifies input data and determines the phase relationship between a data signal DA-1 and a clock signal CL-1 with a reference clock signal. It is detected as a relative phase relationship. The phase control signal generation unit 22 performs the identification Z based on the phase relationship information between the data DA-1a and the clock signal CL-1 output together with the identification data signal from the identification / phase difference detection unit 21. It generates phase control information of the identification cook signal CL-11 to be supplied to the phase difference detection section 21.

The phase control unit 23-1 is the clock signal CL input to the identification / phase difference detection unit 21. -Controls the phase of 1 based on the phase control information generated by the phase control signal generator 22. The phase shift control signal generation section 24 calculates the phase shift amount for the data identified and output by the identification Z phase difference detection section 21 based on the phase control information output from the phase control signal generation section 22. , And outputs it as a control signal to control the phase of the feedback signal supplied to the phase shifters 25-1, 25-2. Then, the phase control units 23-2 and 23-3 output the above-described cook signal having a phase according to the phase control signal generated by the phase shift control signal generation unit 24.

The phase shift units 25-1, 25-2 are adapted to output the clock signals output from the phase control units 23-1, 23-2 to the identification data signal output from the identification / phase difference detection unit 21. The data identification processing is performed by the clock signal, and as a result, the phase of the input data signal is shifted according to the phase of the clock signal.

Hereinafter, the operation of each unit shown in FIG. 3 will be described more specifically. When the input data DA-1 is identified by the clock signal CL-11 in the identification / phase difference detection unit 21, the phase of the coupled signal is determined based on the phase information of the identified coupled signal. And the phase difference between the reference clock signal and the base phase of the predetermined clock signal. The phase information in this case may be analog information, but is digitalized in this embodiment in order to pursue easiness of processing and the like.

Based on this phase information, the phase control signal generator 22 generates a control signal for controlling the phase of the clock signal identifying the data so that it has a more appropriate relationship with the phase of the data to be identified. Is generated and supplied to the phase control unit 23. As a result, the identification cook signal CL-1 can always perform identification with the data signal DA-1 in an appropriate position correlation. At this time, a phase control signal is supplied from the phase control signal generator 22 to the phase shift control signal generator 24.

As a result, in the phase shift control signal generation section 24, the phase of the cook signal used to identify the current data in the identification / phase difference detection section 21 is immediately identified and output. Obtains the phase difference between the data signal itself and the phase of a reference clock signal. Then, based on this phase difference information, the phase shift control signal generator 24 determines how much the identification data signal DA-1a is shifted in each of the phase shifters 25-1, 25-2. Equivalent The phase shift control signal is input to the phase control units 23-1, 23-2, and thereby the phase of the clock signal supplied to the two phase shift units 25-1, 25-2 is changed. Control.

As a result, the phase of the identification data signal DA-1b output from the phase shifters 25-1, 25-2 is within the phase difference within a certain range from the phase of the predetermined reference cook signal. Controlled to fit.

Similarly, the other identification / phase shift sections 3-2, 3-3,..., And 3-n respectively correspond to the identification data signals DA-2b, DA-3b,. Are also controlled so as to fall within a certain range of phase difference from the phase of the predetermined reference cook signal as described above. That is, control is performed so that all data signals output from the identification / phase shift unit 3 are in synchronization with a common signal having a certain phase difference from a common reference signal. Is done.

Therefore, this series of operations makes it possible for the subsequent synchronization processing section 4 to perform synchronization identification processing on all data signals with a common clock signal.

In practice, it is theoretically possible to process the clock signal phase information as described above by an analog-like operation. However, when the circuit scale and the fluctuations and variations of the circuit characteristics are considered. In this case, there are many uncertainties in terms of accuracy of the data. Therefore, in the embodiment of the present invention, such a problem is solved by converting the phase information and the phase control signal into digital information.

Therefore, first, the phase control of the clock signal in the phase controller 23-1 is controlled by a digital code. That is, the phase control signal S pc input to the phase control unit 23-1 is based on a digital code. Also, the phase difference information output from the identification / phase difference detection unit 21 is determined by checking whether the phase of the identification cook signal CL-1 is behind the phase of the data signal DA-1. Is output as a logical operation result, and the phase control signal S pc based on the digital signal is generated based on the advance / delay (E / L) information.

More specifically, the advance / delay information (EZL) of the clock signal output from the identification / phase difference detection unit 21 is set to a pulse, and the phase control signal generation unit 22 is set to an up-down counter having a certain number of bits m. It is realized by. Figure 4 shows one such case. FIG. 4 shows an example circuit diagram. That is, as shown in FIG. 5A, for example, the data DA is different in phase by 1/2 time slot from each other by D-F / F (D flip-flop) 31-1, 31-2, 32 as shown in FIG. 5A. It is identified by three types of clocks CLa, CLb, and CLc. Then, the result of the identification is logically operated by the exclusive OR circuits 33-1a, 33-lb, 33-1c, and the pulsing circuits 33-2a, 33-2b, 33-2c are calculated based on the result. Drive.

That is, for example, two adjacent data are identified by the clock signals CLa and CLc, and when these data have different signs from each other, that is, for example, in a state shown in FIG. The phase of the signal CLb may be detected as a transition point of the data DA, that is, a cross point. Further, if the identification result by the intermediate clock signal CLb is the same sign as the identification result by the preceding clock signal CLa (that is, in the case of the solid line in FIG. 5B), the phase of the clock signal CLb becomes the data signal DAb. Can be determined to be advanced. Similarly, if the identification result is the same as that of the subsequent clock signal CLc (in the case of FIG. 5B), it is determined that the phase of the clock signal CLb is behind the data signal DA. In each case, the pulse EZL-1 and EZL-2 are output and input to the up / down counter 22. According to the advance / delay information of the clock signal, the data signal DA is actually identified appropriately. By delaying / advancing the phase of the clock signal to be used, it is possible to always perform data identification with the clock signal of the appropriate phase.

More specifically, the noise generating circuit 33-2c is configured to output a pulse when the input value is H, while the pulse generating circuits 33-2a and 33-2b are each configured to output a pulse. A configuration is adopted in which a pulse is output when a pulse from c is input and an H input is supplied from each of the exclusive OR circuits 33-1a and 31-1b. As a result, a pulse is output as the signal E / L-1 when the above-mentioned mouth signal is in the advanced state, and conversely, as the signal E / L-2 in the case of the delayed state. Is output. When the pulse is received, the up / down counter 22 counts up when the advance signal pulse (pulse of signal E / L-11) is received, and counts up the delay signal pulse (pulse of signal EZL-2). In such a case, it is configured to count down. At the time of counting, the phase of the identification feedback signal used is delayed, and conversely the power down occurs. In some cases, the control is performed such that the phase of the identification cook signal is advanced.

That is, the phase controller 23-1 receives a peak signal having a phase number of m, and combines the peak signals in a vector manner to generate a peak of a desired phase. Configuration. That is, a clock signal having each phase obtained by dividing one time slot by 2 ^m is generated in accordance with the m-bit digital code. Here, an example of the configuration when m = 4 is described with reference to Figs. 6 and 7.

That is, a circuit as shown in FIG. 6 is considered as the phase control unit 23-1. The circuit consists of four differential transistor pairs, to which clock signals φ 0 and φ ΐ and clock signals / φ 0 and φ 逆 with opposite phases are input, respectively. Here, it is assumed that the clock signals φ 0 and φ 1 have a phase difference of 1/4 of the signal period from each other. In this case, since these correspond to cos ω t and si η ω t, respectively, a clock signal of an arbitrary phase is generated by using the respective positive or negative phase signals, adding weights and summing them. It is possible. That is, a composite cook signal represented by C (t; — a. (1 — ε η η ω ΐ + ax cos co t ··· ®) is obtained.

At this time, the weights p, q, r, and s for the current sources of the differential transistor pairs in FIG. 6 are realized by, for example, the configuration shown in FIG. That is, in this case, p and q, and r and s form catches with each other because of the opposite phases. Therefore, the current source to be turned on is represented by 2-bit digital data, and the current value is represented by a 2-bit code in units of current i as shown in Fig. 7. As a result, the four-stage weighted synthesis of the supply signal waveforms having the above four types of phases makes it possible to realize the above-described formula (1) of the composite signal. At this time the phase of the clock signal is one-to-one correspondence with Digitally Rukodo of 4 bits, 2 ⁴ = 1 6 types of clock signals of the phase is enabled generated corresponding to Di Jitaruko one de.

As described above, since the phase of the peak signal is represented by the m-bit digital code, for example, the reference peak signal is defined as the peak signal corresponding to the code “0000”, and All n-channel parallel signals should be synchronized to this phase Just fine. In this case, as shown in FIG. 8, the phase of the lt¾fj output data DAa in which the phase of the identification clock signal CL d matches the phase of the change point is shifted to the phase of the clock signal CL s to be synchronized.

The maximum amount of phase shift required for this is less than one time slot, that is, the amount of phase full of the phase corresponding to the elapsed time between adjacent transition points of the data signal DAa. Therefore, it is necessary for each of the phase shift sections 25-1, 25-2 in FIG. 3 to have a configuration in which each of them shifts a maximum of a half time slot at most, for example, a D-F / F. Here, the required shift amount is digitally compared and calculated by the phase shift control signal generator 24 with the above code “0000” and the code of the clock signal actually used for identification. It is easy to get. As a result, as shown in FIG. 9, for example, the phase of each post-identification signal DAa can be shifted so as to match the synchronous clock signal CLs “0000”.

For example, in the example of Fig. 9, when the code indicating the phase of the identification cook signal CL—1d is “0 1 0 0”, how far away from the reference clock signal CL s is the code “0 0 0 0”. Is calculated to obtain a code whose addition result is “0 0 0 0”, and the signal DA-1a is phase-shifted by a phase shift amount corresponding to the code. As described above, the phase shift can be shifted by about 1/2 time slot using the D / F / F, as described above. Therefore, as shown in FIG. 1, 2 5-2) can be realized.

In other words, if the distance between the phase of the data signal after identification and the phase to be synchronized is about one time slot, and if the phase shift is performed by one time, the phase of the data signal after identification is It will be identified near the mouth point, which may lead to incorrect identification. On the other hand, by dividing the allocated phase shift amount into a plurality of times, a phase shift operation is performed in which the identification is always performed near the center of the eye pattern, so that data identification can be performed correctly.

Here, various calculation methods are conceivable as to how to realize the phase shift in each of the two-stage phase shift units 25-1, 25-2. This is because the delay time varies depending on the characteristics of the process when forming the circuit, so it is best to optimize it for such factors. In the simplest case, the desired phase If the shift amount exceeds 1/2 time slot, the first-stage phase shifter 25-1 shifts the phase by 1Z2 time slot, and then the second-stage phase shifter 25-2 shifts the remaining amount. Let's shift the phase. If the phase shift amount is less than 1/2 time slot, the desired phase may be shifted only by the first phase shift means 25-1 or the second phase shift means 25-2.

Therefore, with this series of operations, it becomes possible for the subsequent synchronization processing section 4 to correctly perform synchronous processing on all data with a common clock signal.

As described above, in the embodiment of the present invention, in the schematic block diagram shown in FIG. 2, each of the identification / phase shift processing unit units 3-1, 3-2,. The configuration shown in Fig. 4 is applied, and the circuit shown in Fig. 4 is applied to the identification / phase difference detection unit 21 in each of the identification Z phase shift processing units 3-1, 3-2 · · · 3-η However, the circuits described in Figs. 6 and 7 can be applied to each of the phase control units 23-1, 23-2, and 23_3.

Further, in the above-described embodiment, the case where m = 4 is shown, but m is not limited to this, and may be generally set according to the corresponding system requirements. Next, a specific configuration example of the phase shift units 25-1 and 25-2 shown in FIG. 3 will be described. As described above, a DF / F as shown in FIG. 10A can be applied to each of the phase shift units 25-1 and 25-2. In this case, as shown in FIG. 10B, the input data DAa is identified by the phase shift clock signal CLs, and as a result, DAa, whose φ phase is delayed from DAa, is obtained. FIG. 11 shows a specific circuit example of the phase shift units 25-1, 25-2. Since this circuit example has the same configuration as a general F / F (flip-flop) circuit, the description of the circuit operation is omitted.

Next, the digitizing process in the phase control and the phase shift control in the above-described embodiment of the present invention will be specifically described. In the case of applying the up-down counter such as a phase control signal generation unit 22 shown in FIG. 3, the type of the counter, the phase control signal generation unit ² 2 depending on the configuration of the counter output signal, a phase shift control signal producing There can be various concrete configurations such as Narita 23, but here is an example. explain.

First, regarding the number of phases of the clock signal for the time slot, as shown in FIG. 12, the number of phases of the clock signal is set to 4 for simplicity, and the phase of each corresponding clock signal is set to CO , C1, C2, C3. Similarly, a clock signal having a corresponding phase may be referred to as CO, C1, C2, or C3. Further, at this time, the phase control signal for specifying the phase of the cook signal for data identification, which should be actually supplied from the phase controller 23-1 to the identification / phase difference detector 21. The digital code supplied from the generation unit 22 to the phase control unit 23-1 is also the same four types, and corresponds to “0”, “1”, “2”, “3” corresponding to C0, C1, C2, and C3, respectively. ".

FIG. 13 shows a circuit example of a four-stage shift register type counter applicable to the phase control signal generator 22. 14A, 14B, and 14C show the output of each stage from the left of the shift register of FIG. 13 and the corresponding digital code when the configuration of FIG. 13 is applied, and the phase control signal generation unit 22 based on these. The generated phase control signal S pc, the phase shift control signal S ps generated by the phase shift control signal generation unit 24, and the allocation of the phase shift amount to each of the phase shift units 25-1 and 25-2. The rules are illustrated below. Here, an example in which the phases of all data are synchronized with the clock signal C0 having the phase code "0" will be described.

That is, in the identification / phase shift unit cuts 3-1, 3-2,..., And 3-n identification / phase difference detection unit 21, four types of clock signals CO and C shown in FIG. The identification is currently performed by any of the clock signals 1, 2, and 3, and the information of the iigij clock signal phase is supplied to the phase control signal generation unit 22 as digital phase information. Is done. As a method of specifying a clock signal having a phase currently used for identification, for example, the following method can be considered. That is, specifically, for example, in the circuit as shown in FIG. 4, CLa, CLb, and CLc are adjacent to each other around the four types of clock signals CO, C1, C2, and C3. If a set of three types of clock signals are sequentially selected to perform the identification operation, and the sign of the identification result by the mouth signals CLa and CLc at both ends is different, the center mouth signal CL b can be recognized as the corresponding identification clock signal. The counter shown in Fig. 13 is a so-called cyclic counter. The output of each stage of the four-stage shift register is sequentially counted up from "0" to "1 J" by the clock input, and is "1" up to the highest level (right end). , The output of all stages is reset to “0” at the next clock input. Thereafter, the above operation is repeated according to the clock input. As a result, as shown in "Output of each stage of counter" shown in FIG. 14A, a four-digit output of thread combination representing codes 0 to 3 is sequentially obtained. Therefore, according to the current discrimination phase recognized by the discrimination / phase difference detection unit 21 in this manner, clock input to the counter of FIG. 13 is performed, and as a result, a counter output representing the corresponding discrimination phase is output. What is necessary is just to control so that a force may be obtained.

Here, the code “0” is the phase of C 0 in FIG. 12.For example, if the phase of the clock signal currently used as the identification clock signal is CO, after the identification in that case, In order to synchronize the change point of the data signal DAa, that is, the cross point, with the code “0”, that is, the same phase, as described above, a phase shift of approximately one time slot is required. That is, in this case, it is determined that the identification result data signal D Aa requires the maximum amount of phase shift.

On the other hand, if the phase of the peak signal currently used as the identification peak signal is C 3, the change point of the data signal DA a after the identification in that case, that is, the cross point, is As described above, in order to synchronize with the code “0”, that is, the phase CO that occurs immediately after, a phase shift of about 1 Z4 of one time slot is required. That is, in this case, it is determined that the identification result data signal D Aa requires a minimum amount of phase shift.

Further, the phase shift control signal generation section 24 generates a phase shift control signal Sps as shown in FIG. 14B. More specifically, as shown in the figure, this can be generated by a complementary code of the output value of each stage of the corresponding counter. Also, the allocation of the phase shift amount to each of the phase shift units 25-1, 25-2 by the phase shift control signal Sps is as shown in FIG. 14C. That is, in the case of this example, the shift amount corresponding to the total value of the upper two digits of the phase shift control signal Sps is allocated to the first-stage phase shift unit 25-1, and the shift amount corresponding to the lower two digits is calculated. The shift amount is assigned to the first-stage phase shift section 25-1. For example, in the case of the code “0”, that is, in the uppermost row of FIG. 14C, since the upper two digits are “1, 1”, 1 + 1 = 2, that is, the step of the click signal phase shown in FIG. Phase shifter for 1/2 time slot, which is twice as large as 1/4 time slot, is assigned to the phase shifter 25-1 in the first stage. In addition, since the lower two digits are also “1, 1”, 1 + 1 = 2, that is, a phase shift of 1Z2 time slot is allocated to the second-stage phase shift unit 25-2.

Similarly, in the case of the code “1”, that is, in the second stage of FIG. 14C, since the upper two digits are “0, 1”, 0 + 1 = 1, that is, the phase shift of 1/4 time slot is the first stage. Is assigned to the phase shift section 25-1 of Since the lower two digits are “1, 1”, 1 + 1 = 2, that is, the phase shift of 1Z2 time slot is allocated to the second-stage phase shift unit 25-2.

FIG. 15 is an operation flowchart showing the operation of each identification / phase shift unit 3-1: 3-2,..., 3 _n shown in FIG. 3 of the embodiment of the present invention. That is, after the input of the data signal of step S1, the data of the input data signal is identified by the identification clock signal phase-controlled by the identification clock (signal) phase control of step S3 (step S2). From the identification result of step S2, the phase relationship between the phase of the reference cook signal and the phase of the received data signal DA is detected by the configuration shown in FIG. 4 (step S4). In step S3, the phase of the identification cook signal to be used is determined based on the detected phase relationship, and data identification is performed using the identification cook signal of the determined phase (step S3). 2).

Further, the phase relationship detected in step S4 is based on the phase of the identification data signal among the identification Z phase shift units 3-1, 3-2,..., 3-n for each channel shown in FIG. The phase of the synchronization signal having a predetermined phase to be synchronized with the phase of each of the identification / phase shift units 3-1, 3-2,..., 3-n is currently used for identification. The phase difference between the phase of the identification cook signal and the phase of the identification cook signal is detected (step S5). More specifically, in the examples of FIGS. 14A, 14B, and 14C, the above-described phase difference is obtained by obtaining the complementary code of the value of each stage of the counter of FIG. Is detected. Further, the phase difference for shifting the phase of the identification data DAa and the phase shift amount for the two-stage phase shift units 25-1 and 25-2 are determined by a predetermined rule. (For example, Norail shown in Fig. 14C) (step S6). In steps S7 and S9, signals for specifying the phase of the phase-shifting identification cook signal are generated in order to perform the phase shift processing for the phase shift amount thus distributed. In steps S8 and S10, the desired phase shift is performed by identifying the data signal DAa with the phase shift identification cook signal of the designated phase in this manner (see FIG. 10 A, 1 OB configuration). The data signal thus phase-shifted is output to the synchronization processing unit 4 (step S11).

Hereinafter, an example of a processing process in the identification / phase shift unit 3-1, 3-2, 3-3,..., 3 _n according to an embodiment of the present invention will be described with reference to FIGS. 16A to 17 C. I will tell. FIG. 16A shows the waveforms of the input data D1, D2, and D3 (corresponding to the received data DA-11, DA-2, and DA-3 in FIG. 2, respectively). FIG. 16B shows the above-mentioned identification clock signal CO. , C1, C2, and C3 are shown.

As is clear from the figure, the optimal clock signals for identifying these data signals Dl, D2, and D3 are Cl, C3, and C2, respectively. That is, a clock signal in which a clock pulse rises near the center of the time slot of a data signal is most suitable for identifying the data signal.

FIG. 16C shows the results of discriminating the data signals Dl, D2, and D3 using these optimal discrimination clock signals (the output signals DA-1a, DA-2a, DA-3 of the discrimination Z phase difference detection unit 21). a). Here, similarly to the above case, the clock signal C 0 is used as a reference clock signal, and the phase thereof is used for the entirety of the identification / phase shift units 3-1, 3-2,. The output signal is synchronized. In this case, the distance between the phase of each of the signals D 1, D 2, and D 3 after identification shown in FIG. 16C (that is, the phases C 1, C 3, and C 2) and the base ^ (the vertical phase C 0) is +3, +1, and +2, which correspond to the values of the second, fourth, and third stages of the phase shift control signal Sp s in FIG.

That is, the corresponding phase shift control signal Sps is “0, 1, 1, 1” for the data signal D 1, “0, 0, 0, 1” for D 2, and “0, 0, 0, 1” for D 2, 0, 0, 1, 1 ". Therefore, according to the rule shown in Fig. 14C, each phase shift unit 25-1, The phase shift amount assigned to 25-2 is “+1, +2” for D1, “0, +1” for D2, and “0, +2” for D3.

FIG. 16D is a waveform diagram of each of the clock signals C0, C1, C2, and C3, and shows that a delay occurs with respect to that shown in FIG. 16B. That is, since a delay occurs in the circuit shown in FIG. 2, the phase relationship between the clock signal and the data signal after identification varies depending on the circuit characteristics. However, in this embodiment, the absolute phase between the data signal and the peak signal need not always be constant. That is, the purpose of this embodiment is to synchronize the data signals between the respective channels 1 to n (corresponding to the data signals DA-1 to DA-n) in the circuit in FIG. 2 only. Perform the necessary phase shift for each channel. In other words, the absolute phase is not an essential problem as long as synchronization between channels can be achieved.

FIG. 17B shows a waveform of each data signal after the phase shift unit 25-1 has shifted the phase by the above-mentioned assigned shift amount by the clock signal shown in FIG. 17A. That is, since the data signal D1 performs a phase shift of distance +1 at the first stage, the phase shift is performed from the original C1 to C2. Therefore, it is identified by the clock signal C2. On the other hand, D2 and D3 each perform a phase shift of a distance of 0 at the first stage, so they are re-identified by the original C3 and C2, respectively. That is, since the phase relationship between the data signal and the clock signal can fluctuate due to the delay in the circuit as described above, each data signal is identified again by the predetermined clock signal in the phase shift unit 25-1. By compensating for the change in the above-mentioned phase relation, it is compensated.

Next, FIG. 17C shows the waveform of each data signal after the phase shift by the above-mentioned assigned shift amount by the second-stage phase shift unit 25-2. That is, the data signal D1 is phase-shifted from the previous C2 to CO in order to perform a phase shift of distance +2 in the second stage, that is, is identified by the clock signal CO. D2 is phase-shifted (+1) from the previous C3 to CO, that is, identified by the clock signal CO. D3 is phase shifted (+2) from the previous C2 to CO, that is, identified by the clock signal C0. In this way, all data signals are finally synchronized with the phase C0.

As described above, according to the present invention, the reception processing corresponding to the skew in the receiving unit is performed in the batch transmission of the parallel signal in the large-capacity signal transmission in the communication device. This enables parallel processing of parallel signals without slowing down with a simple configuration. As a result, the circuit size of the receiving unit can be greatly reduced, the device size can be reduced, and power consumption can be reduced, and an efficient large-capacity information network can be formed.

The embodiments of the present invention are not limited to those described above, and various embodiments according to the technical idea of the present invention can be derived, and they are also included in the scope of the present invention.

Claims

• The scope of the claims

1 · A signal processing circuit comprising: a phase relation detecting means for calculating a phase relation of each of the parallel input data signals; and a phase shift means for phase-shifting the parallel input data signals by a predetermined amount determined based on the detected phase relation.

2. data identification means for performing data identification for each of the parallel input data signals with a predetermined peak signal;

Phase relationship detection means for determining a phase relationship with a predetermined phase from the phase of the cook signal used for the data identification,

A signal processing circuit comprising phase shift means for shifting the phase of the identified parallel input data signal by a predetermined amount determined based on the detected phase relationship.

3. The signal processing circuit according to claim 1, wherein the phase shift means divides a required phase shift amount to achieve a required phase shift amount in a plurality of times.

4. The signal processing circuit according to any one of claims 1 to 3, wherein the phase shift means achieves a required phase shift by performing a data identification operation using a clock signal having a predetermined phase.

5. The phase information is digital data, the phase relation detecting means calculates the phase relation by digital logic operation, and the phase shift means executes a required phase shift operation according to the phase relation information of the digital data. A signal processing circuit according to any one of claims 1 to 4.