JPS61214842A - Data sampling converting circuit for character multiplexing broadcast - Google Patents

Abstract

PURPOSE:To prevent bit errors due to the variance of pulse width by sampling packet data with plural sampling pulses discriminating the high level and the low level of data in accordance with a majority of high and low levels. CONSTITUTION:When the video signal of character multiplexing broadcast is inputted to a clock reproducing circuit 2 from an input terminal 1, a clock signal locked to a burst signal is generated and has the frequency divided by 1/5 in a frequency dividing circuit 9 to take out 5 kinds of sampling signal 9a-9e. Since an output terminal 17a of a ROM 15 goes to the high level when three or more out of input terminals 15a-15e go to the high level and an output terminal 17b goes to the high level when one of input terminals 15a-15e goes to the high level, an output terminal 24 of a ROM 23 goes to the high level when the output terminal 17a goes to the high level by early rising sampling pulses, and data is discriminated as the high level. Information data is sampled with sampling pulses different in phase similarly, and the high level is discriminated if data is discriminated as the high level three or more times, and the low level is discriminated if data is discriminated as the high level two or less times.

Description

Detailed Description of the Invention "Industrial Application Field" The present invention is a data sampling method for improving bit errors caused by external noise when converting a received signal into digital data in a teletext receiver. This relates to conversion circuits.

4. Prior Art The teletext signal is an I/O signal, as shown in Fig. 2(a).
A horizontal synchronizing signal, a color burst signal, a header, and information data are provided between H, and a unit packet is composed of this header and information data.
As shown in (b), it consists of a Glock run-in (CR), a framing code, and a service identification code.

Conventionally, the sampling clock for synchronizing with the clock run-in (cn) was created using a PLL clock regeneration circuit to generate 8fcs (28,64MHz), and then divided by 5 using a frequency divider circuit to obtain a single-phase clock pulse. (5
, 73MHz) was used.

``Problems to be solved by the invention'' Because the sampling clock only had a single phase, packet data was sampled at only one location. However, since the pulse width of packet data fluctuates due to weak electric fields and noise, there is a problem in that bit errors occur when converting to serial digital data.

"Means for Solving the Problems" The present invention has been made to solve these conventional problems, and includes a clock regeneration circuit that regenerates clock pulses from a character multiplexed signal, and A frequency divider circuit divides the frequency of the received clock signal to 1/n and generates n sampling pulses with shifted phases, and samples character multiplex packet data using the sampling pulses of this frequency divider circuit. It consists of a determination circuit that determines the digital data to be at H level or L level by majority vote of m consecutive sampling results.

"Operation" A clock signal locked to a burst signal is regenerated, and the frequency of this clock signal is divided by 5 to form five types of sampling pulses having different phases in sequence.

Packet data is sampled using this sampling pulse, and if the majority decision is made, that is, three or more are at H level, the packet data is converted to an H level, and if two or less are set to L level, the packet data is converted into a digital value.

"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.

(1) is a character multiplexed video signal input terminal, and this input terminal (1) is connected to a clock regeneration circuit (2) consisting of a PLL circuit.
) are combined. This clock regeneration circuit (2) includes a burst signal extraction circuit (3) and a first phase comparison circuit (4).
), a first voltage controlled oscillation circuit (VCO) (5) that oscillates a 3.58 MHz signal, a second phase comparison circuit (6),
It consists of a second voltage controlled oscillation circuit (VCO) (7) that oscillates a 28.64 MHz signal, and a frequency dividing circuit (8) that divides 28.64 MHz by 178 to obtain 3.58 MHz. 2 V CO (7) is 28.64MHz
It is coupled to a frequency dividing circuit (9) for dividing the frequency by 175 to obtain 5°73 MHz.

The first, second, third, fourth and fifth output terminals (9a) (9b) (9c) (9d) of this frequency dividing circuit (9)
(9e) is the first flip-flop (FF) circuit (
10a) (10b) (10c) (10d) (10
e), buffer circuit (11), oven collector AND circuit (12a) (12b) (12c) (12d
) (12e), third FF circuit (13a) (13
b) (13c) (13d) (13e). The clock run-in input terminal (14) is connected to the first FF circuit (10a) (10b) (10c)
(10d) is coupled to the other input of (10e) and is also coupled to the chip select terminal (16) of the ROM (15), and is coupled to the first FF circuit (10a) (10b).
) (10c) (10d) The Q output of (10e) is the input terminal (15a) (15b) of the ROM (15).
(15c) (15d) (15e). The first output terminal (17a) of this ROM (15) is connected to the buffer circuit (11) via an FF circuit (18).
Also, the output terminals (lla) (llb) (llc) (lid) of this buffer circuit (11)
(lie) is the second FF circuit (19a) (19b)
(19c) (19d) is coupled to one input terminal of (19e), and the other input terminal is connected to the FF circuit (18')
The second output terminal (17) of said ROM (15)
b) is coupled to. The second FF circuit (19a
) (19b) (19c) (19d) (19e)
The output terminals of the AND circuits (12a) (12b)
(12c) (12d) is coupled to the other input terminal of (12e). This AND circuit (12a) (12b
) (12c) (12d) The output terminal of (12e) and the data start input terminal (20) are connected to an AND circuit (21).

Also, the third FF circuit (13a) (13b) (13
c) (13d) The other input terminal of (13e) is connected to the information data input terminal (22), and this third F-F
Circuit (13a) (13b) (13c) (13d)
The output terminal of (13e) is the input terminal of ROM (15) (23a) (23b) (23c) (23d) (2
3e). This ROM (23) (7)
The output terminal (24) is coupled to one input terminal of the serial/parallel conversion circuit (25), and the AND circuit (21)
The output terminal is the chip select terminal (
26), and the inverter circuit (27)
It is coupled to the clock terminal (28) of the serial/parallel conversion circuit (25) via the serial/parallel converter circuit (25). Output terminals (25a)...(25h) of the serial/parallel conversion circuit (25) are coupled to a CPU (not shown) through a data bus.

In the above configuration, when a video signal of teletext broadcasting as shown in FIG. , then 3.58MH
The phase is synchronized with the z signal, and an 8fgc (28,64M)Iz) clock signal locked to the burst signal is generated. This clock signal is divided into 1 by the frequency dividing circuit (9).
75 and output terminals (9a) (9b) (9c
) (9d) From (9e), Figure 2 (d) (e) (
f) (g) 5 whose phases are sequentially shifted as shown in (h)
The types of pulse signals (A), (B), (C), (D), and (E) are extracted, and these serve as the sampling clock for packet data.

Here, lock run-in (
Assume that X) has been input. This clock run-in (X
) The sampling clock that rose earliest from the rising edge of L1 is pulse D5 in Fig. 2 (g), and then pulse E5.
, A6, B6, and C6. Then, the first FF circuit (10a) (10b) (10c) (10d) (
10e) outputs H in the order of (10d), (10e), and (10a). Here, the ROM (15) is configured such that when three or more of the input terminals (15a) to (15e) become H, the output terminal (17a) becomes H. ) (15e) (15a
) becomes H, the output terminal (17a) becomes H.

In addition, the output terminal (17b) is the input terminal (15a) to (15).
If any one of e) becomes H, it becomes H, so the pulse DI becomes H, and the same pulse as DI is output.

When the output terminal (17a) becomes H, a signal is sent to the buffer circuit (11) via the FF circuit (18),
Thereafter, the output side of the buffer circuit (11) is set to high impedance from that point on. When the output terminal (17b) becomes H, the second F-
F circuit (19a) (19b) (19c) (19d
) (19e), so the same F-
The F circuits are L, L, H, and L, respectively. AND circuit (12a) (12b) (12c) (12d)
(12e) are the output terminals (9) of the frequency divider circuit (9), respectively.
e) (9a) (9b) (9c) (9d) are connected so that they are shifted by one, that is, the previous pulse is input, so the clocks are synchronized as shown in Figure 2 (Q). The clock immediately before is output. This pulse is input to the AND circuit (12d), and the AND output with the signal in FIG. 2(i) which becomes H when data starts is shown in FIG.
The result is a pulse like k). In addition, the third FF circuit (
13a) (13b) (13c) (13d) (1
Information data and sampling clocks (A), (B), (C), (D), and (E) are added to the input side of 3e), and at the time of the pulse C6 in FIG. FF circuit (13a) (13b) (13c) (13
d) (13e) becomes H, L, L, H, H. That is, among pulses D5, E5, A6, B6, and C6, D5.
Since E5 and A6 become H, the output terminal (24) of the ROM (23) becomes H. Data (11 to t2) is determined to be at H level because three out of five sampling pulses are H, and there is one digital signal.

Similarly, information data is sampled using sampling pulses with different phases, and if there are three or more H levels, the H level is reached.
If H is 2 or less, it is determined to be L level.

In the above embodiment, the sampling pulse is divided by 5 of the clock run-in frequency, but the present invention is not limited to this.

"Effects of the Invention" As described above, the present invention samples packet data with a plurality of sampling pulses and determines the H level and L level of the packet data by majority vote between H and L. It is possible to prevent bit errors from occurring due to fluctuations in .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data sampling conversion circuit for teletext broadcasting according to the present invention, and FIG. 2 is a waveform diagram of the main part. (1)...Video signal input terminal, (2)...Clock regeneration circuit, (3)...Burst signal extraction circuit, (4
)...first phase comparator circuit, (5)...first vC
o, (6)...second phase comparator circuit, (7)...second VCO, (8)(9)...frequency divider circuit, (10a)
~(10e), (13a) ~(13e), (18), (
18'), (19a) to (19e)... flip-flop circuit, (12a) to (12e), (21) -AND circuit, (15) (23) -ROM. (25)...Serial/parallel conversion circuit.

Claims (1)

[Claims] (1) A clock regeneration circuit that regenerates clock pulses from a character multiplexed signal, and a clock signal regenerated by this clock regeneration circuit that is frequency-divided to 1/n and whose phase is shifted by n.
A frequency divider circuit for generating 1 sampling pulses, and a character multiplex packet data is sampled using the n sampling pulses of this frequency divider circuit, and the digital data is converted into H by a majority vote of the m temporally consecutive sampling results. 1. A data sampling conversion circuit for teletext broadcasting, comprising a determination circuit for determining level or L level.