JPH08242197A - Sacch data transmission. reception circuit for digital radio telephony equipment - Google Patents

Abstract

PURPOSE: To lighten the processing burden of a CPU and to avoid the delay of the processing of the CPU in the case of the transmission and reception of SACCH data through a physical slot for communication. CONSTITUTION: When a slot order bit '0' is detected out of the SACCH data by a significant slot inspection circuit 102, the layer 2 data of 14-bits and the layer 3 data of 1-bit to succeed this bit are accumulated in a register 112, and on the other hand, the layer 3 data of 15-bits in a burst to be received subsequently is accumulated in the register 122, and an output control circuit 106 divides the data accumulated in each register into the layer 2 data of 14-bits and the layer 3 data of 16-bits, and outputs them to the CPU. Accordingly, since the SACCH data to be transmitted is given after being converted into a form easy for the CPU to process, the reception processing of the CPU can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital radiotelephone device for performing radio communication by time division multiple access between a base station and a plurality of mobile stations, and particularly to SACCH data transmitted / received via a communication physical slot. The present invention relates to a SACCH data transmission / reception circuit of a digital wireless telephone device that transmits and receives.

[0002]

2. Description of the Related Art This type of telephone system adopts a digital system for communication between a mobile station called PS and a base station called CS, and analog signals such as voice signals are AD-converted and DA-converted. It is performed and wirelessly communicated as a digital signal. FIG. 6 shows the configuration of such a telephone device, in which a base station 1 is connected via a subscriber line L, and the base station 1 and four mobile stations 2a to 2d are wirelessly connected.

By the way, a 1.9 GHz band is used as a radio frequency band handled by this type of device, and the carrier frequency interval is 300 KHz. Then, communication can be performed between one base station and four mobile stations via one frequency band, and in this case, this frequency is time-divided into 8 time slots to 5 msec as shown in FIG. The base station 1 transmits data to each mobile station in the first four time slots, and receives data from each mobile station in the remaining four time slots.

[0004] Such TDMA (time division)
Since the same frequency can be used by the four mobile stations by the zone multiple access process, the radio waves can be effectively used. A 240-bit burst signal is assigned to each time slot (1 bit = 5/8 × 240 = 2.6 μsec), of which 224 data bits are 384 KHz.
It is transmitted by the clock. Now, the physical time slots for transmitting and receiving the burst signals communicated between the base station and each mobile station are roughly divided into control and communication physical slots, of which the burst signal format of the communication physical slot is Is as shown in FIG.

That is, the physical slot for communication is shown in FIG.
4 bit transient response ramp time R, 2
Bit start symbol SS, 6-bit preamble PR, 16-bit unique word UW, 180-bit information I, and 16-bit error detection CRC (Cyc
lic Redundancy Check) is assigned. The 180-bit information I consists of a 4-bit channel type signal CI, a 16-bit control channel SA, and 160-bit information I, and the information I is an information channel called TCH or FACCH. It is determined according to each channel (FIGS. 8B and 8C). In the FACCH channel, data transfer is performed by temporarily stealing the TCH channel.

By the way, as shown in FIG. 9, SACCH data (16-bit control channel SA data) received through such a communication physical slot is significant data only after receiving a burst signal twice. The first burst signal causes a 14-bit layer 2
The field data and 1-bit layer 3 information are received, and 15-bit layer 3 information is received by the subsequent second burst signal. The numbers in parentheses in FIG. 9 represent the number of bits. Then, the received SACCH data is directly stored in the reception register in the format shown in FIG.
I try to hand it over to the U side. The value of the slot order bit in the SACCH received in the first burst shown in FIG. 9 is "0", and the value of the slot order bit in the SACCH received in the second burst is "1". Sometimes indicates a significant slot of SACCH, then 1
Significant data is formed by the SACCH data received the second time and the data received the second time.

Therefore, when the SACCH data stored in the reception register is input, the CPU first sets
After confirming that the slot order bit of the SACCH in the second burst is "0", 14-bit layer 2 field data and 1-bit layer 3 information are input, and 2
After confirming that the slot order bit of the SACCH in the second burst is "1", the 15-bit layer 3 information accumulated in the reception register at the time of the second burst reception is input. Then, each input data is divided and stored in the layer 2 field and the layer 3 information, and the analysis processing of each information is performed. Further, since the SACCH data is transmitted in the format shown in FIG. 9, the CPU assembles the SACCH data to be transmitted in the format shown in FIG. 9, further adds the slot order bit, and then sets it in the transmission register. As a result, the data set in the transmission register is transmitted at the SACCH time position of the transmission burst. Even if it is not necessary to transmit the SACCH data, the C
SACCH idle data is set and transmitted by the PU.

[0008]

As described above, in the conventional base station and mobile station, when the SACCH data is received, the CPU directly detects the data accumulated in the reception register and performs the reception process. . Also, when transmitting SACCH data, the CPU directly sets the data in a predetermined format in the transmission register, and
Even when it is not necessary to transmit CH data, idle data is set in the transmission register. Therefore, the CPU
Since the transmission / reception process is complicated and the process is delayed, there is a problem that received SACCH data is accumulated without being processed, and proper SACCH data is not transmitted at the time of transmission. Therefore, an object of the present invention is to reduce the load on the CPU when transmitting and receiving SACCH data and to eliminate the processing delay of the CPU.

[0009]

In order to solve such a problem, the present invention is provided with a data receiving section for receiving SACCH data in data via a communication physical slot in a burst signal to be transmitted and received, SAC in the data receiver
A significant slot check circuit for detecting a significant bit from CH data, a first reception register for accumulating 14-bit layer 2 data and 1-bit layer 3 data following the detected significant bit, and a first reception 1 from the burst signals that are transmitted next after the data is stored in the register
A second reception register for accumulating 5-bit layer 3 data, and 14-bit layer 2 data and 16-bit layer 3 for the data accumulated in the first and second reception registers.
And an output control circuit for dividing and outputting the data.

Further, a data transmission unit for transmitting SACCH data in the data via the communication physical slot in the burst signal to be transmitted / received is provided, and the data transmission unit is provided with S
A first transmission register for accumulating 14-bit layer 2 data constituting ACCH data, a second transmission register for accumulating 16-bit layer 3 data constituting SACCH data, and first and second transmission registers In addition to adding the data stored in 1 to the burst signal to be transmitted by adding the extraction slot order bit “0” as 14-bit layer 2 data and 1-bit layer 3 data according to the transmission timing output of the timing generation unit, When transmitting the next burst signal, the remaining 15-bit layer 3
An output coupling circuit for adding the slot order bit "1" to the data and outputting the data is provided. In addition, the base station and the mobile station are provided with the data receiving unit and the data transmitting unit configured as described above. Further, the data transmission unit is provided with an idle data generation circuit for generating idle data as SACCH data and outputting it to the output coupling circuit when layer 2 data and layer 3 data are not transmitted. In addition, the first and second reception registers and the first and second transmission registers are each composed of two registers.

[0011]

When a significant bit is detected from the SACCH data, 14-bit layer 2 data and 1-bit layer 3 data following the significant bit are accumulated in the first receiving register, while the next received burst signal is stored. 1 in
The 5-bit layer 3 data is stored in the second reception register, and the output control circuit divides the data stored in the first and second reception registers into 14-bit layer 2 data and 16-bit layer 3 data. And output. As a result,
In the output control circuit, the SACCH data transmitted is C
Since the PU is converted into a form that can be easily processed and given, the reception processing of the CPU can be reduced. Also, for example, a CPU
While the 14-bit layer 2 data output from the SACCH data is stored in the first transmission register,
16-bit layer 3 forming the SACCH data
The data is accumulated in the second transmission register, and the output coupling circuit converts the data accumulated in the first and second transmission registers into 14-bit layer 2 data and 1-bit layer 3 according to the transmission timing output of the timing generation unit. As data, the slot order bit "0" is added and added to the burst signal, and at the time of transmission of the next burst signal, the slot order bit "1" is added and output to the remaining 15 bits of layer 3 data. As a result, the SACCH data is output in a predetermined format by the output coupling circuit, and the load on the CPU when transmitting the SACCH data can be reduced.

Further, by providing the data receiving unit and the data transmitting unit configured as described above, the SA of the CPU is
CCH data transmission / reception processing is reduced. Also, layer 2
SA when data and layer 3 data are not transmitted
Idle data is generated and transmitted as CCH data. As a result, it is possible to further reduce the load on the CPU when transmitting SACCH data. The first and second reception registers and the first and second transmission registers are each composed of two registers. As a result, the load on the SACCH data transmission / reception processing of the CPU can be further reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing an embodiment of the present invention,
An example of the mobile station 2 that wirelessly communicates with the base station 1 is shown.
In the figure, the mobile station 2 includes an antenna AT and a high frequency unit 2.
1, wirelessly connected to the base station 1 via a wireless unit including a modem unit 22, a wireless control unit 23, and a wireless interface unit 24.

Here, the unique word detection unit 2 is connected to the wireless interface unit 24 via the timing bus TBS.
5, timing generator 26, received CI checker 27, scrambler 28, CRC processor 29, data receiver 3
0, the data transmission unit 31, the transmission data connection unit 32, the simple confidential talk unit 33, the speed conversion units 34 and 35, and the voice processing unit 36.
Is connected. Although not shown, the data receiving section 31 and the data transmitting section 31 are supplied with a clock signal CK of 384 KHz, which will be described later.

In the system bus SBS, the reception CI check unit 27, the transmission data connection unit 32, and the speed conversion unit 3 described above are also included.
Each part except 4, 35 is connected, and CPU4
0, the operation unit 41, and the display unit 42 are connected. Further, the voice processing unit 36 is connected with a handset 43 and a ringer 44 required for a telephone call, and each unit as described above operates by power supply from a power supply unit (not shown). Further, the unique word detection unit 25 and the timing generation unit 26 are
384KH extracted by the wireless interface unit 24
It operates based on the clock signal CK of z 2. In addition,
Reference characters a and b respectively represent reception data and transmission data when the mobile station 2 communicates with the base station 1.

When such a mobile station 2 performs data communication with the base station 1, the data from the base station 1 is transmitted through one slot in which one frequency is divided into eight time slots every 5 msec. To receive. Then, the data is transmitted to the base station 1 through the slot delayed by four slots from the reception slot. The time slot is assigned a time of 625 μsec (5 msec / 8) per slot, and data for one slot is 24
Since it is 0 bit, 1 bit of data is about 2.6
It takes μsec. Therefore, the speed of data transmitted and received is 384 KHz. The physical slots are roughly divided into a control physical slot for transmitting / receiving control data and a communication physical slot for transmitting / receiving audio data and the like.

Next, the operation of the mobile station 2 configured as above will be described. First, in FIG. 4, the frequency is 1.9.
When a radio signal near GHz is transmitted from the base station 1 to the mobile station 2, the antenna AT, the high frequency unit 21, the modulation / demodulation unit 2
2. The wireless unit including the wireless control unit 23 and the wireless interface unit 24 removes the high frequency component from the wireless signal and demodulates it to output the received data a of the frequency 384 KHz from the wireless interface unit 24.

The received data a is received by the unique word detector 25 and the received CI checker 27, and each unit receives a unique word from the burst-shaped received data a based on each reception timing output of the timing generator 26. A channel type signal CI indicating the type of received data such as UW and channel type is detected. The detected information is fed back to the timing generation unit 26 and used to generate the timing required for subsequent data reception. Then, the generated timing signal is sent to the scramble unit 28 and the simple confidential talk unit 3 via the timing bus TBS.
3 and the voice processing unit 36 and other transmission / reception processing units.

In this case, the scrambler 28 removes the scramble for maintaining the DC balance of the code string applied to the received data a and outputs it to the data receiver 30. C
In the PU 40, if the received data a is control data via the control physical slot, these unique words U
The data such as the destination identification code and the outgoing identification code after the channel type CI accumulated in the data receiving unit 30 based on the reception timing output after detecting the W and the channel type signal CI and the data I are input via the system bus SBS. However, if these identification codes correspond to the own device, various protocol processes and received data processes are performed.

As described above, in the mobile station 2, when processing the received data a, the unique word detection section 25 and the received CI are received.
The inspection unit 27 detects the unique word UW and the channel type signal CI indicating the received data type, and generates the reception timing of the subsequent data based on these detections. The scramble unit 28, the CRC processing unit 29, and the data receiving unit 3
0, the data transmission unit 31, the transmission data connection unit 32, the speed conversion units 34, 35, and the like are configured to operate without the CPU 40 intervening. If the received data a is the information I of the physical slot for communication and this indicates a voice signal, the information is deciphered by the simple confidential section 33, and the speed converting section 34 outputs 32K.
The signal is expanded into a signal of Hz, converted into an analog signal by the audio processing unit 36, and output from the handset 43.

Next, when the CPU 40 detects the call operation of the operation unit 41, the CPU 40 creates data of the channel type CI and later based on the above-mentioned format and outputs it to the data transmission unit 31. The data transmission unit 31 sends this transmission data to the CRC processing unit 29 via the data connection unit 32 based on each transmission timing from the timing generation unit 26. The CRC processing unit 29 adds an error detection code to this transmission data and sends it to the scramble unit 28. The scramble unit 28 DC balances this transmission data and sends it as transmission data b to a radio unit such as the radio interface unit 24. . Then, in the wireless unit, when such transmission data b is received, it is modulated, and this modulated signal is superposed on a high frequency and transmitted to the base station 1 as a wireless signal.

In this way, the calling protocol is executed with the base station 1 to call the partner terminal, and the call is started in response to the partner's response. In this case, the audio signal from the handset 43 has a frequency of 32K in the audio processing unit 36.
Converted into a digital signal of Hz, and the speed conversion unit 35
Compressed to a frequency of 384 KHz by the simple secret section 3
Sent to 3. The simple confidential talk section 33 performs a secret story process on this voice data and sends it to the transmission data connection section 32. After that, this voice data is transmitted to the partner terminal via the base station 1 through the above-mentioned route.

Next, FIG. 5 is a block diagram showing the configuration of the base station 1 wirelessly connected to the mobile station 2. In the figure,
The same parts as those of the mobile station 2 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, the base station 1 omits the operation unit 41, the display unit 42, the handset 43, and the ringer 44 provided in the mobile station 2, and the voice processing unit 36 is connected to the line interface 5.
1 is connected.

In this case, the CPU 50 has the data receiving unit 3
For example, when calling data or the like is input from the mobile station 2 via 0, the line interface 51 is controlled to send a dial signal or the like according to the calling data to the line L, and at the same time, from the line L via the line interface 51. When receiving an incoming signal or the like, the incoming data is set in the transmission data register 31 and transmitted to the mobile station 2 side. The transmission of voice signals other than control data such as calling data and incoming data is performed in the same manner as in the mobile station 2. That is, the voice signal on the line L side via the line interface 51 is transmitted to the voice processing unit 36.
After being subjected to speed conversion and scramble processing, the data is transmitted to the mobile station 2 side via the radio section. Further, the voice signal from the mobile station 2 is received by the radio section, then scrambled and speed-converted, further voice-processed, and then transmitted to the line L side.

By the way, in the data transmitted / received by the base station 1 and the mobile station 2 through the communication physical slot, as shown in FIG. 8, a 4-bit channel type signal CI is followed by a 16-bit control channel. There is SA data. Such data of the control channel SA, that is, SACCH
The data becomes significant data only after receiving the burst signal twice, and 14-bit layer 2 field data and 1-bit layer 3 information are received by the first burst signal, and the subsequent second burst. The signal receives 15-bit layer 3 information. Thus S
Since the ACCH data must be transmitted / received in two bursts, the CPU transmission / reception process becomes complicated and the process may be delayed. Therefore, in this embodiment, the SACC received in the format shown in FIG.
The H data is converted by the data receiving unit 30 into a format that can be easily processed by the CPU and given. Also, CPU
The SACCH data transmitted from the data transmission unit 31 is converted into the format shown in FIG. 9 and can be transmitted.

FIG. 1 is a block diagram showing a main configuration of the data receiving section 30. In the figure, 101 is serial /
Parallel conversion control circuit, 102 significant slot check circuit, 103 write control circuit, 104 read control circuit, 105 status generation circuit, 106 output control circuit, 111/121 serial / parallel conversion circuit, 1
Reference numerals 12 and 122 are registers. In the figure, RTM is a timing indicating the reception range of the SACCH data generated by the timing generation unit 26, UWC is a signal indicating the detection result of the 16-bit unique word by the unit word detection unit 25, and CRCC is the CRC processing unit 29. Of the inspection result, RD is the CPU read signal, RSA is C
Received SACCH data given to the PU, ST1 to ST3 show status signals notified to the CPU.

By the way, SACCH data is transmitted / received with the slot order bits shown in FIG. 9 added. Here, when the slot order bit is “0”, the first SA
It indicates that the data is CCH data, and that the SACCH data is the second time when the slot order bit is "1" continuously. And, this order bit "0"
SA when “1” and “1” can be received as a continuous burst
This is a significant slot of CCH, and significant data is formed from SACCH data in which the slot order bit is “0” and SACCH data in which the slot order bit is “1”.

That is, first, in the significant slot check circuit 102, S is selected from the received data a based on the clock signal CK, the timing RTM, and the unique word detection result CRCC.
When the ACCH data is detected, the slot order bits "1" and "0" in this data are determined, and the determination result is notified to the serial / parallel conversion control circuit 101. The serial / parallel conversion control circuit 101 activates the corresponding serial / parallel conversion circuit based on the determination result of the slot order bits. That is, if the slot order bit is a significant bit of "0", the serial / parallel conversion circuit 111 is activated. Then, the SACCH data is converted into parallel data by the serial / parallel conversion circuit 111 and stored in the register 112. If the slot order bit is "1", the serial / parallel conversion circuit 121 is activated. Then, the SACCH data is converted into parallel data by the serial / parallel conversion circuit 121 and stored in the register 122.

Here, the significant slot check circuit 102 is
The following state transition is performed depending on whether the CRC inspection result is correct or not. That is, if the detected slot order bit is "0" and the CRC check result is abnormal, the standby state is again detected for the data having the slot order bit "0" included in the next and subsequent bursts. If the detected slot order bit is "0" and the CRC check result is normal, the system is ready to receive data in which the slot order bit included in the next burst is "1". Then, the data whose slot order bit is "1" is received, and CR
If the C check result is normal, the register 112 stores the first (first time) received SACCH data (data at the significant slot), and the register 122 stores the second received SACCH data. It

If data having a slot order bit of "0" is received, the slot order bit in the next burst is "1", and the CRC check result is abnormal at this time, the next and subsequent times are repeated. Becomes a standby state for detecting data in which the slot order bit included in the burst of "0" is "0". Also, when the data having the slot order bit of "0" is received, the slot order bit of "0" is received during the next burst.
If this is detected, this data is received on the first reception SACCH.
Data.

Here, each SACCH of the first and second times
When the CRC check result is normal when the data is received, the significant slot check circuit 102 determines that the write control circuit 1
A register write instruction is sent to the register 03. Then, the write control circuit 103 uses the register write instruction and the serial / parallel conversion guard instruction c from the status generation circuit 105 to output each serial / parallel conversion circuit 11 to the serial / parallel conversion circuit 11.
Register the parallel data of 1,121 in the register 11 respectively.
2, 122 is accumulated. On the other hand, the read control circuit 104
Is a register 11 according to a read signal RD from the CPU.
2 data or data in the register 122 is sent to the output control circuit 106.

The output control circuit 106 includes registers 112, 1
22 is input, the layer 2 field data in the register 112 shown in FIG.
As shown in (a), of the 16 bits, bits D6 and D
7 is given to the CPU as a 14-bit layer 2 field which becomes empty. Also, for the 15-bit layer 3 information shown in FIG.
The layer 3 information of the bit is added to the most significant bit, and
C as 16-bit layer 3 information as shown in (b)
Give to PU. Therefore, in the CPU, the output control circuit 106
The data RSA given by the above can be input as it is without being converted and protocol processing and the like can be performed, and the data receiving processing of the CPU can be reduced.

At this time, the status generation circuit 105
Then, based on the significant slot inspection result from the significant slot inspection circuit 102, the write control signal of the write control circuit 103, and the read control signal from the read control circuit 104, the statuses ST1 and ST of the registers 112 and 122 are determined.
2. The status ST3 indicating the discard of the SACCH data is output to the CPU side. It also outputs the above-mentioned serial / parallel conversion guard instruction c. After being notified by the statuses ST1 to ST3 that significant SACCH data has been received, the CPU reads the SACCH data by the above-mentioned read signal RD and analyzes and processes the data.

By the way, the registers 112 and 122 have a double buffer structure, and therefore, each unit can store 2 units (2 bursts) of SACCH data. Therefore, the entire apparatus stores 4 bursts of SACCH data. it can. Therefore, the SACC of the CPU
The load when receiving H data can be reduced. Here, the above-mentioned SACCH data discard status ST3
Has two units of SACC in each register 112, 122.
This is output when SACCH data having a significant bit is newly received while H data is stored. In this case, new data is discarded without being stored in the register.

Next, FIG. 2 is a block diagram showing the main part of the data transmission unit 31, showing the structure of the transmission unit for transmitting SACCH data. In the figure, 201 is a write control circuit, 202 is a transmission SACCH data set determination circuit, 203 is a parallel / serial conversion control circuit, 2
04 is a SACCH idle data generation circuit, 205 is a status generation circuit, 211 and 221 are registers, 21
Reference numerals 2 and 222 denote parallel / serial conversion circuits. In the figure, SSA is SACCH data output from the CPU in a format shown in FIG. 3, WR is a CPU write signal, and S
ST is the transmission slot timing from the timing generation unit 26, and STM is the SACCH from the timing generation unit 26.
Data transmission timing, RQ is SACC from CPU side
Each of the H data transmission requests is shown.

First, in the write control circuit 201, the CPU
When the data SSA is output from the side via the bus SBS and then the write signal WR is output, the write signal W
By R, the register 211 stores the SACCH data in the format shown in FIG. 3A, and the register 221 stores the SACCH data in the format shown in FIG. 3B. .

Here, in the transmission SACCH data set determination circuit 202, at the same time that the transmission slot timing SST is enabled, the storage state of each register is inspected to determine whether or not the transmission SACCH data is set, and the determination result is set in parallel / parallel. Notify the serial conversion control circuit 203. When notified that the setting of the transmission SACCH data is completed, the parallel / serial conversion control circuit 203 first synchronizes the data of the register 211 with the parallel / serial conversion circuit 2 in synchronization with the transmission timing STM and the clock signal CK.
Then, the data is sent to 12 and converted into serial data and sent to the output coupling circuit 206. Then, the data in the register 221 is sent to the parallel / serial conversion circuit 222, converted into serial data, and sent to the output coupling circuit 206.

When the output coupling circuit 206 receives these serial data, it assembles them into a predetermined format shown in FIG. That is, the SACCH data from the parallel / serial conversion circuit 212 shown in FIG.
When the SACCH data from the parallel / serial conversion circuit 222 shown in (b) is input, 14 of FIG.
Bit layer 2 field data is set to the bit position of the layer 2 field shown in FIG. 9, and the bit position (least significant bit) following this layer 2 field is set to the bit position of FIG.
The highest bit of the layer 3 information in (b) is set. Then, as SACCH data transmitted as the first burst, a 1-bit slot order bit (significant bit) having a value of “0” is added to the 14-bit layer 2 field data and 1-bit layer 3 information. Then, the data is transmitted to the transmission data concatenation unit 32 as the transmission data b1.

As the SACCH data transmitted as the second burst, the remaining 15-bit information of the 16-bit layer 3 information shown in FIG. 3B is a 1-bit value "1". A slot order bit is added and transmitted to the transmission data concatenation unit 32. As a result, this transmission data b1 is wirelessly transmitted as SACCH data from the wireless unit to the partner device side. In this way, the output coupling circuit 20
6, SACCH data is assembled into a predetermined format and transmitted, so that the load on the CPU when transmitting SACCH data can be reduced.

By the way, in the case of a communication physical slot, such SACCH data is always transmitted at every transmission of each burst. Therefore, when such data is not set from the CPU side, the SACCH idle data generation circuit 204 generates idle data and sends it to the output coupling circuit 206. That is,
In the SACCH idle data generation circuit 204, the transmission S
When the output of the ACCH data set determination circuit 202 indicates that data setting has not been completed, the SACCH idle data is sent to the output coupling circuit 206 in synchronization with the transmission timing STM and the clock signal CK. In this case, when the SACCH idle data is input to the output combining circuit 206, the SACCH idle data is added to the 1-bit slot order bit and sent to the transmission data concatenation unit 32. As described above, since the SACCH idle data generation circuit 204 is provided so that the idle data can be transmitted, the CP
The load on the CPU can be reduced as compared with the conventional method in which U generates and transmits idle data.

The status generation circuit 205 outputs the register status ST4 to notify the CPU based on the judgment output result of the transmission SACCH data set judgment circuit 202 and the SACCH data transmission request RQ from the CPU side. Therefore, when the CPU wants to transmit SACCH data, it outputs the transmission request RQ and outputs the status generation circuit 2
The register status ST4 output from 05 is detected, and the data is written in the registers 211 and 221. With this configuration, it is possible to further reduce the transmission processing of the CPU when transmitting SACCH data. Further, each of the registers 211 and 222 has a double buffer structure like the registers of the data receiving unit 30, so that the device can store up to 4 bursts of SACCH data. As a result, the transmission processing of the CPU is further reduced.

[0042]

As described above, according to the present invention, S
When a significant slot of SACCH is detected from the ACCH data, 14-bit layer 2 data and 1-bit layer 3 data following this slot order bit are accumulated in the first reception register, while the next received burst signal 15-bit layer 3 data is stored in the second receiving register, and the output control circuit stores the 14-bit layer 2 data and 16-bit layer 3 data in the first and second receiving registers. Since the output is divided into and output, the SA sent by the output control circuit
Since the CCH data is converted into a form that can be easily processed by the CPU and given, the reception processing of the CPU can be reduced. In addition, for example, 14-bit layer 2 data that is output from the CPU and that forms the SACCH data is stored in the first transmission register, while the SACCH data is formed 16
The bit-layer 3 data is stored in the second transmission register, and the output coupling circuit stores the 14-bit layer 2 data and 1-bit data stored in the first and second transmission registers according to the transmission timing output of the timing generation unit. As a layer 3 data of bits, a slot order bit "0" is added and added to the burst signal, and at the time of transmission of the next burst signal, a slot order bit "1" is added to the remaining 15 bits of layer 3 data and output. By doing so, the SACCH data is output in a predetermined format by the output coupling circuit, and the load on the CPU at the time of transmitting the SACCH data can be reduced.

Further, by providing the base station and the mobile station with the data receiving section and the data transmitting section configured as described above, the SACCH data transmission / reception processing executed by the CPU of each station can be greatly reduced. When layer 2 data and layer 3 data are not transmitted, SAC
Since the idle data is generated and transmitted as the CH data, the load of the CPU when transmitting the SACCH data can be further reduced. Moreover, since the first and second reception registers and the first and second transmission registers are each configured by two registers, the SAC of the CPU
The load during the CH data transmission / reception processing can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a data receiving unit showing an embodiment of a digital wireless telephone device to which the present invention is applied.

FIG. 2 is a block diagram of a data transmission unit that constitutes the above apparatus.

FIG. 3 is a data format of SACCH data transmitted and received between a CPU and a data receiving unit and a data transmitting unit in the device.

FIG. 4 is a block diagram of a mobile station that constitutes the above apparatus.

FIG. 5 is a block diagram of a base station that constitutes the above apparatus.

FIG. 6 is a system configuration diagram of the device.

FIG. 7 is a diagram showing communication timing of the device.

FIG. 8 is a diagram showing a format of data transmitted and received via a communication physical slot of the device.

FIG. 9 is a diagram showing a reception timing of SACCH data transmitted and received via the communication physical slot.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Base station, 2a-2b ... Mobile station, 26 ... Timing generation part, 30 ... Data receiving part, 31 ... Data transmitting part, 10
2 ... Significant slot check circuit, 111, 121 ... Serial / parallel conversion circuit, 106 ... Output control circuit, 112,
122, 211, 221 ... Register, 202 ... Transmission SA
CCH data set determination circuit, 204 ... SACCH idle data generation circuit, 206 ... Output coupling circuit, 212,
222 ... Parallel / serial conversion circuit.

Claims (7)

[Claims] 1. A base station accommodating a wired line and performing wireless communication by time division multiple access through a plurality of transmission and reception time slots, and each of the plurality of transmission and reception wirelessly connected to the base station. Of the time slots, it comprises a mobile station that wirelessly communicates with a base station via any one of the transmission time slot and the reception time slot. When transmitting and receiving control data, the transmission / reception time slot is used as a control physical slot. When transmitting and receiving audio data, the transmission and reception time slots are used as communication physical slots, and each of the data is converted into a burst signal based on a clock signal of a predetermined frequency and an output of a timing generation unit that generates a timing signal from the clock signal. In a digital wireless telephone device for transmission / reception, transmission to the base station and mobile station SA in the data through the communication physical slot in the burst signal to be
A data receiving unit for receiving CCH data is provided, and in the data receiving unit, a significant slot check circuit for detecting a significant bit in the SACCH data, 14-bit layer 2 data and 1 bit following the detected significant bit A first receive register for accumulating layer 3 data of the
The second receiving register for accumulating 15-bit layer 3 data from the burst signal to be transmitted next after the data is accumulated in the receiving register and the data accumulated in the first and second receiving registers An SACCH data transmission / reception circuit for a digital wireless telephone device, comprising an output control circuit for dividing and outputting 14-bit layer 2 data and 16-bit layer 3 data. 2. A base station that accommodates a wired line and performs wireless communication by time division multiple access through a plurality of transmission and reception time slots; and each of the plurality of transmissions and receptions wirelessly connected to the base station. Of the time slots, it comprises a mobile station that wirelessly communicates with a base station via any one of the transmission time slot and the reception time slot. When transmitting and receiving control data, the transmission / reception time slot is used as a control physical slot. When transmitting and receiving audio data, the transmission and reception time slots are used as communication physical slots, and each of the data is converted into a burst signal based on a clock signal of a predetermined frequency and an output of a timing generation unit that generates a timing signal from the clock signal. In a digital wireless telephone device for transmission / reception, transmission to the base station and mobile station SA in the data through the communication physical slot in the burst signal to be
A first transmission register for providing a data transmission unit for transmitting CCH data, and accumulating 14-bit layer 2 data constituting the SACCH data in the data transmission unit;
16-bit layer 3 forming the SACCH data
A second transmission register for accumulating data, and first and second
The data accumulated in the transmission register of 14-bit layer 2 according to the transmission timing output of the timing generation unit.
As the data and the 1-bit layer 3 data, the slot order bit “0” is added and added to the burst signal to be transmitted, and when the next burst signal is transmitted, the slot order bit “0” is added to the remaining 15-bit layer 3 data. An SACCH data transmission / reception circuit for a digital wireless telephone device, which is provided with an output coupling circuit for adding and outputting "1". 3. A base station accommodating a wired line and performing wireless communication by time division multiple access through a plurality of transmission and reception time slots, and each of the plurality of transmission and reception wirelessly connected to the base station. Of the time slots, it comprises a mobile station that wirelessly communicates with a base station via any one of the transmission time slot and the reception time slot. When transmitting and receiving control data, the transmission / reception time slot is used as a control physical slot. When transmitting and receiving audio data, the transmission and reception time slots are used as communication physical slots, and each of the data is converted into a burst signal based on a clock signal of a predetermined frequency and an output of a timing generation unit that generates a timing signal from the clock signal. A digital wireless telephone device that sends and receives data to and from the base station and mobile station. A data receiver for receiving the SACCH data in the data via the communication physical slot in the burst signal that is provided with a data transmitter for transmitting SACCH data, to the data receiving section, S
A significant slot check circuit for detecting a significant bit in the ACCH data, a first reception register for accumulating 14-bit layer 2 data and 1-bit layer 3 data following the detected significant bit, and a first reception A second reception register that stores 15-bit layer 3 data from the burst signal that is transmitted next after the data is stored in the register, and 14-bit data stored in the first and second reception registers An output control circuit for dividing and outputting the layer 2 data and the 16-bit layer 3 data, and accumulating 14-bit layer 2 data constituting the SACCH data in the data transmitting unit.
Of the SACCH data and the transmission register of 1
A second transmission register for accumulating 6-bit layer 3 data, and 1 for the data accumulated in the first and second transmission registers according to the transmission timing output of the timing generation unit.
The 4-bit layer 2 data and the 1-bit layer 3 data are extracted and added to the burst signal to be transmitted by adding the slot order bit "0", and the remaining 15-bit layer 3 data is transmitted when the next burst signal is transmitted. An SACCH data transmission / reception circuit for a digital radiotelephone device, which is provided with an output coupling circuit for adding a slot order bit "1" to and outputting it. 4. The SACCH data transmission / reception circuit of the digital wireless telephone device according to claim 2, wherein layer 2 data and layer 3 data are accumulated in the first and second transmission registers of the data transmission unit. When not in use, an idle data generation circuit for generating idle data as the SACCH data and outputting it to the output coupling circuit is provided.
ACCH data transceiver circuit. 5. The SACCH data transmission / reception circuit for a digital wireless telephone device according to claim 1, wherein each of the first and second reception registers comprises two registers. circuit. 6. The SACCH data transmission / reception circuit for a digital wireless telephone device according to claim 2, wherein each of the first and second transmission registers is composed of two registers. circuit. 7. The SACCH data transmission / reception circuit for a digital wireless telephone device according to claim 3, wherein each of the first reception register, the second reception register, the first transmission register, and the second transmission register is two registers. A SACCH data transmission / reception circuit for a digital wireless telephone device.