SU1104674A1 - Clock synchronizing device - Google Patents

Abstract

A COLLECTION SYNCHRONIZATION DEVICE, containing successively soy ;; inates first reversible counter, first trigger, first element I, block, control, controlled frequency divider, frequency divider, first delay element, integrator and first decoder, the outputs of which are controlled by control of a frequency divider to the second input of the control unit, a second reversible counter connected in series, a second decoder, a switch, to the other inputs of which are connected the outputs of the corresponding bits of the first reversible the counter, the second trigger and the second element And, the output of which is connected to the third input of the control unit, the master oscillator, the output of which is connected to the clock input of the controlled frequency divider, the first output of which is connected to the clock input of the phase discriminator, the second output to the first input of the third trigger , to the second input of which are connected the outputs of the first and second elements AND via the OR element, and the output of the third trigger is connected to the control inputs of the first and second elements AND, controls the output of the integrato and connected to the reset input of the second decoder and through the second delay element to the reset input of the second reversible counter, the first output of the phase discriminator connected to the combined first inputs of the first and second reversing counters and to the second input of the first element I, and the second output to the combined BTopuiM inputs of the first and second reversible counters and the second element AND, the other output of the switch is connected to the corresponding input of the first trigger, and the other output of the first reversible counter is connected to to the corresponding input of the second trigger, the output of the divider hour (Ltot is connected to the reset input of the first Decoder, as well as the third AND element and the front edge generator of pulses, distinguished so that, in order to improve the synchronization accuracy by reducing the effect of false corrections, impulses, an inequality element, a regeneration block, and additional first and second delay elements are introduced, with a clock and stro35. - the second output of the controlled frequency divider and the output of the master oscillator are connected respectively to the inputs of the regeneration unit, and the signal input of the regeneration unit is connected to the first input of the third element unit I through the first input of the regeneration unit through the element of unequal ambiguity, to the other input of which the output of the second additional delay element is connected, the input of which

Description

combined with the output of the regeneration unit and with the input of the front-edge pulse generator, the output of which is connected to the corresponding input of the integrator, and the output of the third element AND is connected to the signal input of the phase discriminator, with the outputs of the controlled frequency divider and the regeneration unit being the outputs of the device.

The invention relates to the transmission of discrete messages and can be used to provide clock synchronization of the receiving part of the hardware. A known clock synchronization device contains sequentially connected control unit, the first control frequency divider and phase discriminator, the outputs of which are connected to the summing and subtracting inputs of the first reversible counter, as well as the timing generator, the integrator and the first trigger and the first element sequentially connected. This output of the master oscillator is connected to the second input of the first controlled frequency divider, the second controlled frequency divider connected in series, the first the second delay element, the second reversible counter, the first decoder and switch, as well as the front-edge driver, the frequency divider, the second delay element, the second and third decoders, and the second trigger and the second element And, to the second input, as well as the second to the input of the first element I, the subtractive and the control inputs of the second reversible counter, the corresponding outputs of the phase discriminator are connected, and the outputs of the first and second elements I are connected respectively to the summing and calculating to the input of the control unit, to the clock input of which the second output of the first controlled frequency divider is connected, to the control inputs of which the outputs of the second decoder are connected, to the inputs of which and the inputs of the third decoder the outputs of the front edge generator are connected to the inputs of the third decoder whose pulse input is combined with the information input of the phase discriminator, and to the integrator reset input through the second delay element and to the control inputs of the second and third decoders directly connected to the output of the frequency divider, the first output of the first controlled frequency divider is connected to the counting input of which and the counting input of the second controlled frequency splitter, while the outputs of the third decipher are connected to the inputs of the settings of the initial state of the second controlled frequency splitter whose output is connected to the control input of the first decoder, and the outputs of the first reversible counter are connected to the setup inputs of the first and second triggers, the output inputs of which are connected to The switch s, to the second inputs of which are connected the second codes of the first revolution counter L. The drawbacks of the device are low noise immunity and phasing accuracy, as well as complex implementation. The closest technical solution to the present invention is a clock synchronization device comprising a first reversible counter connected in series, a first trigger, a first AND element, a control unit, a controlled frequency divider, a frequency divider, a first delay element, an integrator, and a first decoder, whose outputs Its frequency divider is connected to the second input of the control unit, a second reversible counter connected in series, a second decoder, a switch, to the other inputs of which under The outputs of the corresponding bits of the first reversible counter, the second trigger and the second element I, the output of which is connected to the “ch to G)) (; 11. the input of Olok ynpaijjieNICH, -LL.CHK GSNeraTschr, OYKh (Ch1, (zgo 11odk: tk) At the clock input of the pram frequency splitter, the first KOTopoio input is connected to the clock input of the phase discriminator, the second output is connected to the first input of the third trigger, and the output of the first and second elements is connected to the second input of the NLP, and the third trigger is connected to the control output the inputs of the first and second element And, the integrator control output is connected to the reset input of the second decoder and through the second delay element to the reset input of the second reversible counter, while the first output of the phase indicator of the ohonator is connected to the combined first

the inputs of the first and second reversible counters and to the second input of the first element And, and the second output to the combined second inputs of the first and second reversible counters and the second element And, another output of the switch is connected to the corresponding input of the first trigger, and another output of the first reversible counter is connected to the corresponding input of the second three hera, the output of the frequency divider is connected to the reset input of the first decoder, as well as the third element And the driver of the leading edge of the pulses, the output of which through the third el The AND input is connected to the combined inputs of the integrator and the fourth trigger, to another input of which the output of the frequency divider is connected, and the output of the fourth trigger is connected to another input of the third element I, and the input of the front edge pulse generator is combined with the corresponding input of the phase discriminator 21.

A disadvantage of the known clock synchronization device is the low synchronization accuracy due to ali NIN spurious correction pulses.

The purpose of the invention is to improve the accuracy of synchro-reduction by reducing the effect of false correction pulses.

To achieve this goal, a clock synchronization device containing the first reversible counter, the first trigger, the first AND element, the control unit, the controlled frequency divider, the frequency divider, the first delay element, the integrator, and the first

a decoder whose outputs through a controlled shared frequency connect 1s to the second input of the control unit, a second reversible counter, a second decoder, a switch, whose outputs of the corresponding bits of the first reversible counter 1ka, the second trigger and the second element I are connected to the other inputs The output of which is connected to the third input of the control unit, the master oscillator, the output of which is connected to the clock input of the controlled frequency divider whose first output is connected to the clock input of the phases second discriminator, the second output to the first input of the third trigger, the second input of which is connected to the outputs of the first and second elements AND via the OR element, and the output of the third trigger is connected to the control inputs of the first and second elements AND, the control output of the integrator is connected to the reset input second decipher and through the second e. delay time - to the reset input of the second reversible counter; in this case, the nepBbtfi output of the phase discriminator is connected to the combined first inputs of the first and second reversible meters and to the second input of the first element H, and the second output to the combined second inputs of the first and second reversible counters and the second element I , another switch output is connected to the corresponding input of the first trigger, and another output of the first reversible counter is connected to the corresponding input of the second trigger, the output of the frequency divider chen to reset input lane. the third decoder and the front edge pulse generator, an inequality element, a regeneration block and an additional first and second delay elements are introduced, while the second output of the controlled frequency divider and the output of the master oscillator are connected to the clock and strobe inputs of the regeneration unit, and the signal input of the regeneration unit through the first additional delay element is connected to the first input of the block of the third element, And to the second input of which the output of the registration block is connected via the inequality element, to the other input of which the output of the second additional delay element is connected, the input of which is combined with the output of the regeneration unit and the input of the front-of-pulse generator, the output of which is connected to the corresponding input of the integrator, and the output of the third element I The discriminator, the outputs of the controlled frequency divider and the regeneration unit are the outputs of the device.  FIG.  Figure 1 shows the structural electrical circuit of the clock synchronization device; . in fig.  2 time diagrams for his work.  The clock synchronization device contains the first and second reversible counter.  1 and 2, the first and second decoders 3 and 4, the front-of-pulse driver 5, the switch 6, the phase discriminator 7, the integrator 8, the control block 9, the driving oscillator 10, the frequency divider 11, the controlled frequency divider 12, first, second and the third ISIS triggers, the OR element 16, the first, second and third elements AND 17-29, the first and second delay elements 20 and 21, the first and second additional delay elements 22 and 23, the equivalence element 24 and the regeneration unit 25 Clock synchronization device works as follows.  The sequence of high-frequency pulses from the output of the master oscillator 10 is fed to the clock input of the controlled divider 12, as a result of which clock pulses are formed at its first and second outputs (at the first output - clock mander, at the second - narrow pulses), the next with frequency, close to the rate of discrete modulation (wiring speed) of received message elements, (Fig.  2a) arriving at the signal input of the regeneration unit 25 and the input of the first additional delay element 22.  The regeneration unit 25 performs the integration of the received message elements, with the result that a regenerated one is generated at its output (t. e.  the reconstructed, or in other words, cleaned-out) sequence of input pulses (FIG.  26), which is separated in time from the message elements coming from the communication channel for the duration of one message element.  At the output of the first additional delay element 22 (FIG.  2c) with a time delay equal to the duration of one message element, received (not recovered from interference) elements of the message are received from the communication channel.  The regenerated sequence of input pulses from the output of the regeneration unit 25 is fed to the input of the driver 5 of the leading edge of the pulse, to the second input of the element 24. inequalities and the input of the second additional element 23 of the delay.  From the output of the second additional delay element 23, the regenerated sequence of input pulses (FIG.  2e), delayed by a time equal to the duration of one message element, arrives at the first input of inequality element 24.  Since a single voltage level at the output of the unequal element 24 can only be formed if different logical signals (zero and one or one and zero) arrive at its inputs, and the second additional delay element 23 delays the regenerated input sequence for the duration of one element message, then at the stroke of element 24 of inequality (FIG.  2e) single signals are generated only in the case of a change of the logic level (zero and one) of the regenerated sequence of input pulses.  In other words, the zero voltage level at the output of the unequal element 24 is formed only in the case of the appearance of double, triple, and so on in the input sequence. d. .  parcels of one character (non-single zero or single elements of the message), with the zero voltage level corresponding in time to a certain part of the group of regenerated feeds of the same character (second half for double feed, second and third parts for triple feed, and so on. d. ).  The voltage levels from the output of the inequality element 24 (Fig. 2e) arrive at the second input of the third element I 19, to the first input of which the delayed one is received for the duration of one element of the message input (t. e.  unresponsive) sequence of received message elements (FIG.  2c). As a result, only the elementary dressings of the message and the first parts of the double, triple, etc. are fed to the second input of the phase discriminator 7. d.  on syrup (fig.  2g).  For this reason, the interference distortion in the communication channel of the remaining parts (except for the first) is double, triple, and so on. d.  The parcels do not affect the operation of the phase discriminator 7.  The phase discriminator 7 compares the phase of the thirds-passed element AND 19 received message elements (essentially their fronts) with the phase of the device’s output clock pulses and if they do not match (delay or advance), one of its outputs produces the corresponding correction pulse of addition or subtraction (one correction impulse on each of the edges of the input signal-), arriving at the corresponding inputs (first or second), or in other words, summing or subtracting the first and second reversible counters 1 and 2.  The first reversible counter 1, which partially protects against false frequency tuning in case of random distortions of received message elements (single sprinkling or the first parts of repeated repeated scattering of the same character), averages the input values.  If the number of pulses arriving at one of the inputs (for example, the first, t. e.  summing) the first reversible counter 1, exceeds the number of pulses received at its other input (second, t. e.  subtracting), by an amount equal to the recalculation coefficient of the first reversible counter 1, at one of the outputs of its last bits (in this case, at the first output, t. e.  at the output of the last bit of addition) a pulse is formed, which sets the corresponding first trigger 13 to one state, preparing for operation the first AND element (in this case, the first AND 17 element) at the second input. The first trigger 13 is reset to the zero state in order to protect against random distortion of the received message elements via the 6 sig switch. cash from the output of the intermediate bit subtracting the first reversible counter 1, m. e.  partially averaged signal.  Similarly, the second trigger is set to a single state by the maximum averaged signal from the second output (the last bit subtracted output) of the first reversible counter 1, and its reset to the zero state by a partially averaged signal from the second output of the switch 6 (t. e.  a signal from the output of the intermediate bit for adding the first reversible counter 1).  To ensure fast response and phasing accuracy in strong interference conditions x, the partial averaging factor of the fault signals is variable, t. e.  the switch 6 switches the drain inputs of the first and second triggers 13 and 14 with the outputs of certain bits of the subtraction and addition of the first reversible counter 1, depending on which of the second inputs of the switch 6 forms the voltage level of the logical unit (m). e.  depending on the code of the number on the outputs of the second decoder 4).  The signal at a certain output of the second decoder 4 is generated depending on the code of the number recorded in the second reversible counter 2, t. e.  depending on the ratio of the number of pulses of addition and subtraction (in other words, on the device's operation mode: synchronization is stable, synchronization entry mode, stable Mismatch of the frequencies that specify the generator. ditch of the receiving and transmitting parts of the transmission system, etc. d. ), received from the outputs of the phase discriminator 7 during the time interval between two pulses at the first output (output of the intermediate bit) of the integrator 8, which allows to take into account the structure of the received messages and to ensure high accuracy and speed of the device.  It should be noted that the integrator 8 (at the second input) is charged (FIG.  2d) the leading edges (from the output of the forefront of the pulse generator 5) of the regenerated sequence of received message elements (Fig. 42b) t. e.  fragmentation of received message elements (FIG.  2a) do not affect the operation of the integrator 8.  The input of information into the second decoder 4 is performed by a signal from the first output of the integrator 8.  The same signal, delayed in the second delay element 21 (for a time sufficient for 91 to enter information into the second decoder 4), resets the second reversing counter 2 (on the third input) to the zero state.  The capacity of the second reversible counter 2 is chosen to be sufficient so that during the time between the two discharge pulses it does not overflow.  The pulses following the wiring frequency from the second output of the controlled frequency divider 12 periodically set the third trigger 15 into a single state, the unit voltage level from the output of which prepares for operation the third inputs of the first and second elements 17 and 18.  As follows from the above process of controlling the first and second triggers 13 and 14, they can simultaneously be in the logical zero state, but only one of these triggers can be in the single state (first trigger 13 or second trigger 14).  In the event that the first 13 and third triggers 15 are both in the same state, the first corrective addition pulse (formed at the first output of the phase discriminator 7) passes through the first AND 17 element to the first (t. e.  a summing) input of the control unit 9.  Simultaneously, the pulse from the output of the first element And 17 through the element OR 16 is fed to the fault input of the third trigger 15, transferring it to the zero state and prohibiting (through the third input) the passage of pulses through the first element I.  Due to the fact that the installation of a third trigger 1 5 in a single state is performed with a wiring frequency, for a time equal to the duration of one message element to the input of control unit 9 more than one corrective pulse (true, due to the front of the received message, or false, due to for example, crushing), which increases the noise immunity of the device and the accuracy of the phasing (since true correction pulses are generated only on the edges of the received element of the coupling).  Similarly, the third trigger 15, controlled by the second element, And 18, reduces the number of false correctional subtracting pulses passing to the second (t. e.  Excluded) input unit 9 control. .  Thus, the signals from the outputs of the first and second elements And 17 and 18 are fed to the summing and eliminating inputs of the control unit 9.  As a result, the number of high-frequency pulses (coming from the output of the master oscillator 10), subjected to division in the controlled frequency divider 12, t. e. .  the frequency and phase of the clock at the output of the device (the first output of the controlled frequency divider 12) is adjusted.  Adjustment step (t. e.  sampling adjustment of the frequency and phase of the output clock, t. e.  the offset value of the clock pulse at the output of the device from its basic position, which is added to one added or exclusive pulse, which is divided in the controlled frequency divider 12, is set depending on which of the outputs of the first decoder 3 has the voltage level of the logical unit .  The voltage level is logical.  the unit at a certain output of the first decoder 3 is set depending on the readings of the integrator 8.  Entering the readings of the integrator 8 into the first decoder 3 takes place after a period of time equal to the period of the pulses at the output of the divider 11 and determining the number of elements of the received message, analysis. which characterizes the average frequency of alternation of single and zero parcels and their groups in the received message, t. e.  their statistical characteristic (the structure of the received capacity of the integrator 8 is chosen to be sufficient so that during the time between two to five discharge pulses coming from the output of the frequency divider 11 through the second additional delay element 21 it does not overflow. The charge of the integrator 8 is performed by the leading fronts (FIG.  2d) received jneMeHTOB messages that sent the front-edge generator 5 of the pulse from the regenerated by regeneration unit 25 (Fig.  2b) a sequence of input pulses of the device (FIG.  2a), which ensures high accuracy of the selected fronts.  The more often single and zero elements alternate or their groups are included in received messages (t. e.  the more often the phase discriminator compares the phase of the input and clock pulses and generates correction pulses corresponding to the mismatch sign), the higher the integrator 8 readings and the smaller frequency step of controlled frequency divider 12 set by the first decoder 3 (by turning on control unit 9 between the corresponding the bits of the controlled splitter 12 frequency).  Similarly, the more often the single and zero elements of a message are interleaved at the device input, the shorter the period of the signals at the first output of the integrator 8, t. e.  the shorter the time period during which the reversible counter 2 determines the ratio of the number of addition and input pulses generated by the phase discriminator 7 (t. e.  the less time analysis of the operating mode of the proposed device).  The implementation of the charge of the integrator 8 by pulses formed from the regeneration fronts (cleared from interference) by the regeneration unit 25 of the elements of received messages completely eliminates its charge by spurious pulses caused by fragmentation of the message elements (comparing Figs.  2d and fig.  2l)  As a result, the level of interference in the communication channel does not affect the accuracy of setting the sampling step of the frequency control, as well as the accuracy of setting the time intervals for analyzing the device operation mode (since the average frequency of the alternation of zero and 1412 message units and their groups it is determined correctly), which is unattainable in a known device.  The implementation of the prohibition of passage to the input of the phase discriminator 7 of the subsequent (except for the first) parts (elements) of double, triple, etc. d.  the parcels make it possible to eliminate the formation at the outputs of the phase discriminator of the main part of false correction pulses (a comparison of FIG. 2k and FIG.  2i), as a result, the synchronization accuracy is higher (the OR element and the third trigger limit, as in the known device, the number of spurious pulses transmitted to the output of the phase discriminator 7, due to the interference of single message elements and the first double elements, triple elements, etc. d.  parcels).  Since the probability of occurrence is double, triple, and so on. P.  messages in a message is approximately 0.5, then only this factor provides an increase in the accuracy of synchronization in terms of interference in comparison with the known one almost twice.  Taking into account the existing protection of the integrator against interference, the achieved gain in synchronization accuracy in terms of interference in comparison with the known one will be much higher.  In addition, the implementation of protection against integrator interference leads to a decrease in the capacity of the integrator and reversible meters, and thus simplify the decoders. In addition, a decrease in their capacity, and hence inertia, allows for a faster response to changes in the phase of the input pulses and mode of operation. devices, t. e.  improve synchronization speed, and therefore synchronization accuracy.

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Claims (1)

A TACT SYNCHRONIZATION DEVICE containing a first reversible counter, a first trigger, a first AND element, a control block, a controlled frequency divider, a frequency divider, a first delay element, an integrator and a first decoder, the outputs of which are connected to the second input of the control unit through a controlled frequency divider connected in series to a second reversible counter, a second decoder, a switch, to which other inputs are connected the outputs of the corresponding bits of the first reversible counter chika, the second trigger and the second element And, the output of which is connected to the third input of the control unit, the master oscillator, the output of which is connected to the clock input of a controlled frequency divider, the first output of which is connected to the clock input of the phase discriminator, the second output - to the first input of the third trigger, to the second input of which the outputs of the first and second elements AND are connected through the OR element, and the output of the third trigger is connected to the control inputs of the first and second elements AND, the control output of the integrator is connected to the reset input of the second decoder and through the second delay element to the reset input of the second reversible counter, while the first output of the phase discriminator is connected to the combined first inputs of the first and second reversible counters and to the second input of the first element And, and the second output to the combined second inputs the first and second reversible counters and the second element I. the other output of the switch is connected to the corresponding input of the first trigger, and the other output of the first reversible counter is connected to the corresponding input to the second trigger, the output of the frequency divider is connected to the reset input of the first decoder, as well as the third element And and the front edge of the pulse generator, characterized in that, in order to increase the accuracy of synchronization by reducing the influence of false correction pulses, an ambiguity element, a regeneration unit, and additional the first and second delay elements, while the second output of the controlled frequency divider and the output of the master gene are connected respectively to the clock and building inputs of the regeneration unit a radiator, and the signal input of the regeneration unit through the first additional delay element is connected to the first input of the block of the third AND element, to the second input of which the output of the regeneration unit is connected via an unequal element, the output of the second additional delay element, the input of which is combined with the output of the block, is connected to the other input regeneration · and with the input of the leading edge of the pulse generator, the output of which is connected to the corresponding input> of the integrator, and the output of the third element And is connected to the signal the course of the phase discriminator, and the frequency divider output is controlled and the regeneration unit are the outputs of the device.