SU1022325A2 - Device for group clock synchronization - Google Patents

Abstract

DEVICE GROUP CLOCK SYNCHRONIZATION on author. St. No. 646453, characterized in that, in order to reduce the time to synchronization and eliminate spurious phasing at low frequency mismatches, serially connected switch vj divider rows, phase zone signalization unit, counter block, counter state analyzer and distributor are introduced into it The outputs of which are connected to the corresponding additional inputs of the channel dividers, the outputs of which are connected to the inputs of the switch of the dividers, the additional input of which is connected to the output op An alternator, the second output of which is connected to the auxiliary input of the meter state analyzer, and the input of the communication interruption detector is combined with the corresponding inputs of the phase zone forming unit, the counter block, the distributor and the correction pulse switch. (LU IND conded

Description

The invention relates to discrete communication systems and can be used for clock synchronization of a group of signal converter equipment used in the technique of transmitting discrete signals.

According to the main author. St. No. 646453, a device for group clock synchronization is known, comprising a series-connected signal switch, a phase discriminator, a correction pulse switch, p channel divisors and a clock switch, the output of which is connected to the second input of the phase discriminator, to the third input of which the output of the interruption detector is connected, the input which is connected to the output of the switch signals, the second output of which is combined with the second input of the switch of the correction pulses, the secondary input switch of clock pulses and the output of the reference) generator, the other output of which is connected to the corresponding inputs of the channel channelJ.

A disadvantage of the known device is that it does not eliminate the false phasing mode, which prevents reliable reception of information. In addition, a characteristic feature of this device is the delayed exit from the false phasing mode to the hold mode with a slight detuning of the transmitter and receiver frequencies.

The purpose of the invention is to reduce the time to synchronization and eliminate false phasing at low frequency detuning.

To achieve this goal, a group clock synchronization device containing serially connected signal switches, a phase discriminator, a correction pulse switch, p channel dividers and a clock switch, the output of which is connected to the second input of the phase discriminator, to the third input of which the output of the link break detector is connected the input of which is connected to the output of the signal switch, the second output of which is combined with the second input of the correction pulse switch, to The additional input of the clock switch and the output of the reference generator, the other output of which is connected to the corresponding inputs of the channel dividers, are connected in series to the switch of the dividers, the phase zone forming unit, the counter state analyzer, and the distributor whose outputs are connected to the corresponding additional inputs of p-channel dividers, the inputs of which are connected to the inputs of the switch of the dividers, an additional input of which is connected k output of the reference oscillator.

the second output of which is connected to the auxiliary input of the meter state analyzer, and the input of the communication interruption detector is combined with the corresponding inputs of the phase zone signal generator unit, the counter unit, the distributor, and the correction pulse switch.

The drawing shows a block diagram of the device group clock synchronization.

The group clock synchronization device contains a switch 1 of signals, a phase discriminator 2, a switch of 3 clock pulses, a detector of 4 communication interruptions, a reference generator 5, a switch 6 of correction pulses, p channel dividers 7, a switch 8 of divider bits, block 9 of generation of signals of phase zrn, a block 10 of counters, a state analyzer of counters 11 and a distributor 12. The device operates as follows,

The first input of the phase discriminator 2 through the switch 1 signals receives the received discrete signal from the output of one of the discrete channels. To the second input of the phase discriminator 2

through the switch of clock pulses 3 through. clock pulses from the output of the higher bit of the channel divider 7 of that channel, whose input signal at this moment of time goes to the first input of the phase discriminator 2, enter.

The first inputs of all p channel dividers 7 from the second output of the reference generator 5 receive a reference high frequency. Depending on the phase mismatch of the input discrete signal and the clock frequency pulses, the phase discriminator 2 generates phase correction (addition or exclusion) pulses fed to the first input of the switch 6 correction pulses, one of the outputs of which is connected to the second input of the corresponding channel divider 7. Simultaneously signals c the outputs of the bits of the same channel divider 7 through the switch 8 of the bits of the dividers arrive at the second group of inputs of the block 9 of the formation of the phase zone signals. The first input of the signal-phase shaping unit 9 from the output of the signal switch 1 receives the received discrete signal, at the moment of the front arrival of which the phase-shaping unit 9 in accordance with

With the state at this moment in time, the controlled channel divider 7 generates a signal at its corresponding output, which is fed to the first input of one of the counters of the meter block 10, thereby increasing its state by one. With

In this case, the UL counter is filled when the significant moment of recovery (MIT) hits the first, the counter 10.2 - into the second, the counter 10.3 - into the third, the counter 10.4 -

fourth phase zone. The first phase zone corresponds to the state of the n channel dividers from O to (-1); second - from to

(Z 1); from 4 to (: | -N - 1); from 3 / 4N to (N - 1), where N is the division ratio of the dividers of n channel dividers 7.

After a certain period of time, approximately equal to the time allotted for phasing, the signal from the third output of the reference generator 5 to the second input of the state analyzer of counters 11 is used to analyze the state of the block of counters 10.1-10.4, the outputs of which bits are connected to the first group inputs of the state analyzer of counters 11. The objectives of the analysis will be that the states of the counters 10.2 and 10.3 of the block 10 of the counters significantly exceed the states of the counters 10.1 and 10.4 (which corresponds to the false phase OCT), the state analyzer of counters 11 generates at its output a signal that is fed through distributor 12 to the third input of the corresponding channel divider 7 and changes its state to -th, which corresponds to a 180 ° phase change of clock pulses.

After a specified synchronization time (the time is determined theoretically) using switching pulses from the first output of the reference generator 5 to the second inputs of the switch 1 signals, switch b correction signals, switch 3 clock pulses, switch 8 divider bits, distributor 12 and block 10 counters synchronously connect with the HHMaieMoro discrete signal and the next-channel clock pulses to the corresponding inputs of the phase discriminator 2, as well as correction signals from the output f azov discriminator 2 to the second input of the corresponding channel divider 7,

5 CONCLUSION of all bits of the same channel divider 7 to the first group of inputs of the phase zone forming unit 9, connecting the output of the analyzer 11 of the counter states to the third input of the corresponding channel divider 7, as well as resetting all the counters of the block of 10 counters. The implementation of these operations determines the phase adjustment of the clock pulses on the received discrete information.

5 By the described method, the phase adjustment of the clock pulses from the outputs of all channel dividers is carried out.

When a break occurs (the disappearance of a received discrete signal), the communication breaker 4 disconnects the first input of the phase discriminator 2 from the discrete channel, thereby excluding the change in phase of the clock oscillation under the influence of noise in the communication channel.

Thus, the use of the proposed group clock synchronization device In group signal converting devices makes it possible to completely eliminate false phasing by changing the phase of the clock frequency by 180 ° even if the frequencies of the transmitter signals are equal

 and receiver, thereby ensuring reliable reception of information.

In addition, the time taken to enter the hold mode is reduced, which makes it possible to increase the amount of well received information for a certain period of time.

Claims (1)

DEVICE OF GROUP TACT SYNCHRONIZATION by ed. St. No. 646453, characterized in that, in order to reduce the time of synchronization and eliminate false phasing for small frequency mismatches, it is connected to a series-connected switch of the divider bits, a block for generating phase zone signals, a block of counters, a state analyzer of counters and a distributor, the outputs of which are connected to the corresponding additional inputs of the channel dividers, the outputs of which are connected to the inputs of the switch of the divider bits, the additional input of which is connected to the reference output of the generator, a second output is connected to an additional input of counter states analyzer and the input of the detector integrated communication interruption to the corresponding inputs of the phase zones forming unit signals unit counters and switch the distributor correction pulses. Yu Yu GO Yu Xia>