SU856028A2 - Device for synchronizing with discrete control - Google Patents

Description

(54) SYNCHRONIZATION DEVICE WITH DISCRETE CONTROL

one

The invention relates to a technique for the transmission of messages by discrete signals and can be used in transmission systems for codograms and telecontrol commands, in particular, via short-wave radio channels.

A discrete-control synchronization device is known, comprising a pulse edge selector, a false synchronization discriminator, a phase discriminator, an averaging unit, a frequency divider, a master oscillator, three OR elements, and a key 1.

However, this device has insufficient synchronization accuracy.

According to the main author. St. No. 758547, a discrete-control synchronization device is known, comprising a pulse edge selector, the output of which is connected to the inputs of the false synchronization discriminator and the phase discriminator, the outputs of which are connected to one of the inputs of a frequency divider through another averaging unit, and the output of the master oscillator is connected to another input the output of the frequency divider is connected to the control inputs of the phase discriminator: the minator and the discriminator of false synchronization, which also contains three elements OR or a switch, while the output of the phases The new discriminator through the first element OR is connected to one of the key inputs, to the other input of which the output of the discriminator of the false synchronization is connected, and the output of the key is connected to the auxiliary input of the frequency divider via the second element, OR, to the second input of which the second output of the averaging unit is connected, the first and second outputs of which through the third element OR are connected to the input of the Prohibition key. To increase accuracy

15 synchronization in the device entered the decoder and the delay unit, and the additional output of the frequency divider is connected to the input of the decoder connected between the output of the divider

20 of the frequency and the control input of the discriminator of the false synchronization, the output of which through the delay unit is connected to another input of the key, the input of which is connected to the other input of the delay 2. ...

However, this device is large, the time of entry into synchronism, the purpose of the invention is to reduce the time of entry into synchronism.

To achieve this goal, a discrete-control synchronization device contains a pulse edge selector whose output is connected to the inputs of a false synchronization discriminator and a phase discriminator whose outputs are connected via one averaging unit to one of the inputs of a frequency divider, to the other input of which a master oscillator output is connected , and the output of the frequency divider is connected to the control inputs of the phase discriminator and the false synchronization discriminator, which also contains three OR elements and a switch, the outputs of the phase discriminator through the first element OR are connected to one of the inputs of the key, to the other input of which the output of the discriminator of false synchronization is connected, and the output of the key is connected to the additional input of the frequency divider via the second element OR, to the second input of which the second output of the averaging block, the first and second outputs of which through the third element OR are connected to the input of the key lock, which also contains the decoder and. delay unit, the additional output of the frequency divider connected to the input a decoder connected between the output of the frequency divider and the control input of the discriminator of false synchronization, the output of which through the delay unit is connected to another input of the key, the input of which is connected to another input of the delay unit, is entered a pulse counter whose input is respectively connected to the output of the delay unit and the output element OR, and the output of the pulse counter is connected to the auxiliary input of the third element OR.

The drawing shows a structural electrical circuit of a synchronization device with discrete control.

The device contains a pulse edge selector 1, a master oscillator 2, a frequency divider 3, a phase discriminator 4, an averaging unit 5, a first element OR b, a second element OR 7, a third element OR 8, a decoder 9, a discriminator 10 false, synchronization, block 11 delay, key 12 and counter 13 pulses.

The device works as follows.

During the reception of information, the signals corresponding to 11p1M moments from the output of the pulse selector 1 arrive at the phase discriminator 4 and the discriminator 10 false synchronization. In the absence of false synchronization, the phase discriminator 4 determines the sign of the phase mismatch, depending on which the addition pulses are issued, or subtraction to the averaging unit 5. Signals

at the output, the average cadmium of block 5 appears only if the number of addition pulses (subtracting) coming from the output of phase discriminator 4 steadily prevails over the number of subtraction pulses (addition) during the averaging period. The capacity of the averaging unit 5 for session communication via HF radio channels is selected based on the expected value of fragmentation of the received signal ZTo (for a given signal-to-noise ratio) and lies in predetermined 2-3, the signal from the output of the averaging unit 5 goes to the divider 3 frequencies, changing the phase of clock pulses.

If a false synchronization occurs (the probability of such an event is rather high during a session communication via HF radio channels and depends on the expected value of the predominance of P

Aomewx tj2

tn absolute value

where is that

prevailing, and also depends on the session communication frequency) the discriminator 10 false synchronization through the time determined by the delay block 11., simultaneously the control signal to the key 12 and to the enable input of the counter 13 pulses. The key 12 is opened, and the addition and subtraction pulses, alternately coming from the outputs of phase discriminator 4, as well as the pulses from the output of the master oscillator 2 (the tracking frequency is K) through the first element 6 OR, the public key 12 and the second element 7 OR are fed to the auxiliary input divider 3 frequency and at the same time these pulses arrive at the reading input of the counter 13 pulses, which starts counting them.

At the same time, due to the alternate arrival of the addition and subtraction pulses from both outputs of phase discriminator 4, the averaging unit 5 does not send control signals to frequency divider 3, and the phase of clock pulses is changed only by signals from key 12.

The timing of fe synchronization, i.e., the rate of output of the system from the false synchronization zone, is determined by the number of control signals from the output of the master oscillator 2 and from the output of the phase discriminator 4. Since the key 12 was opened, i.e. since the occurrence of spurious synchronization, it is known that the clock phase is lagging (leading) by

angle H o-So12g the key 12 must open

on time T $

It's time

determines the counter of 13 pulses with mutual reset (K / 2-2) of the discharge, where K / 2 is the number of pulses,

Claims (1)

^! Claim Discrete-controlled synchronization device St. »758547, characterized in that, in order to reduce the time of entering synchronism, a pulse counter is introduced, the inputs of which are respectively connected to the output of the delay block and the output of the first element _t OR, and the output of the pulse counter is connected to the additional input of the third element OR. Sources of information taken into account during the examination USSR certificate 04 L 7/02, 1974.