RU2099868C1 - Device for automatic search for radio stations - Google Patents

Abstract

FIELD: radio engineering, radio dispatching points that monitor and analyze signal situation. SUBSTANCE: device for automatic search for radio stations has former 1 of controlling signals, generator 2 of reference frequencies, receiver 3 and signal detector 4 which includes former 5 of clock frequency, unit 6 extracting signal of cyclic frequency, unit 7 storing signals of clock and cyclic frequencies , comparator 8 and indicator 9. Realization of invention leads to enhanced probability of detection of working communication channel in case of frequent changes of working frequencies of watched radio station since decision on belonging of signal on i-th fixed frequency of radio station of interest is made in case of agreement of stored pulses in time and frequency to corresponding starting clock and cyclic frequencies of received signal on each i-th fixed frequency. EFFECT: enhanced probability of detection of working communication channel. 11 dwg

Description

 The invention relates to the field of radio engineering and can be used in radio dispatch monitoring points for the analysis of the signal situation in the region, for the automatic search and detection of radio stations that constantly change operating frequencies.

 A device for isolating pulse signals against a background of noise and impulse noise (see USSR author's certificate 1638795, class K 5/26, 1988), containing two pulse shapers of standard duration, a delay line, a memory unit, two elements And, a selector radio pulses, amplitude detector, threshold element, pulse counter, reference pulse generator, comparison unit.

 A device for receiving tonal frequencies (see USSR author's certificate 1720171, class H 04 Q 1/46, 1989), comprising a matching unit, a pulse shaper, a trigger pulse shaper, a clock pulse generator, two counters, two counters, And two permanent storage units, two counters, an OR element, a register, a comparison unit.

 Such analogue circuits provide a search for radio signals, but have a low probability of detecting the desired signal with frequent changes by the transmitter of operating frequencies.

 It is also known storage device for automatic search for radio channels according to the copyright certificate of the USSR 1515373, cl. B 1/10 1989. This device contains: a block of reference frequencies, a receiver, a signal converter, a register, a driver of control signals, a demultiplexer, K additional registers, a multiplexer, an indicator, a distributor, a comparison unit, an initial installation unit. Thanks to this scheme, the device provides a search for radio channels with a minimum level of interference. In addition, the device can search for working radio stations by measuring the energy of the received signals. However, this device has a drawback. With frequent changes of operating frequencies by radio stations, the device does not provide the required probability of detecting a working communication channel.

 The closest in technical essence to the claimed device (prototype) is a known device according to international application WO / 92/22147, class. H 04 B 1/40, comprising a receiver with automatic search for radio frequencies, a signal detector, a reference frequency generator, a driver of the control signal. However, the prototype device also has a drawback. When conducting radio monitoring of the signal situation under heavy bandwidth, especially when several identical radio stations are operating simultaneously, the device does not provide the required probability of detecting a working communication channel with frequent changes of the operating frequency observed by the radio station.

 The aim of the invention is to develop a device for the automatic search for radio stations, which provides a higher probability of detecting communication channels with frequent changes of operating frequencies by the observed radio stations.

 This goal is achieved by the fact that in the known device for the automatic search for radio stations containing a receiver, a signal detector is connected to the output of the demodulated signal, the output of which is connected to the input of the driver of the control signals, the output of the signal of the fixed frequency code of which is connected to the control input of the reference frequency generator connected to heterodyne input of the receiver, communications are additionally introduced. The output of monitoring the presence of the signal of the receiver is connected to the second input of the driver of the control signals, the output of the signal "initial setting" which is connected to the input of the initial installation of the signal detector. The output of the fixed frequency code signal is additionally connected to the indication input of the signal detector. Moreover, the signal detector consists of a waiting driver of a clock frequency, a block for extracting a signal of a cyclic frequency, a block for storing signals of a clock and cycle frequencies, a comparison unit, an indicator. The first indicator input is the signal detector indication input, and the output of the comparison unit is connected to the second indicator input, which, in turn, is the signal detector output. The information input of the standby clock driver is connected to the information input of the cycle frequency signal isolation unit and is the information input of the signal detector. The second input of the standby clock driver is the input "initial setting" of the signal detector. The output of the standby clock driver is connected to the inputs of the clock frequency of the loop signal allocation block, the clock and loop frequency signal storage unit, and the comparison unit. The output of the loop frequency signal isolation block is connected to the loop frequency inputs of the clock and loop frequency signal storage unit and the comparison unit. The signal output of the reference clock frequency and the signal output of the reference cycle frequency of the memory unit of the clock and cycle frequencies are connected to the corresponding inputs of the comparison unit.

 The introduction of new connections and the specific implementation of the signal detector allows you to identify the observed radio station when it is scanned by the N applied fixed frequencies by storing the initial clock and loop frequencies of the received signal and then comparing them with the clock and loop frequencies of the signal at each i-th frequency. The decision on whether the signal belongs to the i-th fixed frequency of the radio station of interest is made when the frequency and time of the pulses of all four compared frequencies coincide.

 In FIG. 1 shows a General structural diagram of the claimed device; in FIG. 2 circuit driver control signals; figure 3 diagram of the waiting driver of the clock frequency; in Fig.4 block diagram of the signal allocation of the clock frequency; 5 is a diagram of a block for storing signals of clock and cycle frequencies; in FIG. 6 circuit block comparison; 7 is a drawing explaining the formula (1); on Fig a graph of the probability of frequency-time coincidence of the tuning frequency of the receiver with the frequency of the detected radio station from the recognition time; Fig. 9 is a drawing explaining the principle of identification of a desired radio station; 10 is a drawing explaining the formula (2); 11 is a graph of the probability of detection of a radio station from the recognition time.

 The claimed device, the structural diagram of which is shown in Fig. 1, consists of a driver of control signals (FSF) 1, a generator of reference frequencies (GOCH) 2, receiver 3, detector 4.

 The signal detector 4 combines a standby clock frequency shaper (LFTC) 5, a block for extracting a cycle frequency signal (BCSC) 6, a block for storing signals of clock and cycle frequencies (BSCCH) 7, a comparison unit (BS) 8, indicator 9.

 The output 1.1 of the FSF 1 is n-bit and is connected by an n-bit bus to the input of the reference frequency generator 2 and the input 9.1 of the indicator 9. Output 1.4 of the FSF 1 is connected to the input 5.2 of the LFCC 5. The output of the reference frequency generator 2 is connected to the heterodyne input of the receiver 3. Output 3.1 the receiver 3 is connected to the input 5.1 of the HFCC 5 and to the input 6.1 of the HSCF 6, and the output 3.2 with the input 1.2 of the FSF 1. The output of the HFCC is connected to the input 6.2 of the HFMS 6, with the input 7.1 of the HFMS 7 and with the input of 8.1 BS 8. The output of the HFSC 6 is connected to input 7.2 БЗСТЦЧ 7 and input 8.4 BS 8. Output 7.3 БЗСТЦЧ 7 is connected to input 8.2 BS 8, and output 7.4 to input 8.3 BS 8. Output BS 8 is connected to input 9.2 house LED 9 and to the input 1 1.3 SCF.

The following names correspond to the input / output numbers of some blocks:
the first output 1.1 of the shaper control signals 1 output signal code of a fixed frequency;
the second output 1.4 of the shaper control signals 1 output signal "initial setting";
the first output 3.1 of the receiver 3 output demodulated signal;
the second output 3.2 of the receiver 3 output control signal availability;
the first input 5.1 of the standby driver 5 clock information input;
the second input 5.2 of the standby driver of the clock frequency 5 input signal "initial setting";
the first input 6.1 of the block selection signal cyclic frequency 6 - information input;
the second input 6.2 of the block selection signal cyclic frequency 6 input signal of the clock frequency;
the first input 7.1 of the unit for storing signals of clock and cycle frequencies 7
clock signal input;
the second input 7.2 of the unit for storing signals of clock and cycle frequencies 7
cyclic frequency input;
the first output 7.3 of the unit for storing signals of clock and cycle frequencies; 7 output of a signal of a reference clock frequency;
the second output 7.4 of the unit for storing signals of clock and cycle frequencies; 7 the output of the signal of the reference cycle frequency.

 The reference frequency generator 2 and receiver 3 are similar to those in the channel search device according to the copyright certificate of the USSR 151373, cl. H 04 B 1/10, 1989. In addition, as a reference frequency generator and receiver, you can use the commercially available R-399A Katran radio receiver, where these units are technically implemented. As indicator 9, any commercially available digital indicator can be used.

 Shaper control signals 1 can be implemented according to the circuit shown in figure 2. In particular, the circuit includes a generator 101, two logical elements AND 102 and 103, a logical element OR 104, a counter 105, a programmable memory (EPROM) 106. The output of the generator 101 is connected to the first inputs of the elements And 102 and 103. The second input of the element And 102 is the input 1.3 of the FCS 1, and the second input of the AND element 103 with the input 1.2 of the FCS 1. The outputs of the AND 103 elements are connected to the inputs of the OR element 104, the output of which is connected to the input 105.1 of the counter 105. In addition, the output of the OR element 104 is the output 1.4 of the FCS 1. The counter output is m-bit and connected to the m-bit input of the software Memory 106. The Mth output of the counter 106, in addition, is connected to the input 105.2. The output of the EPROM is n-bit and is the output 1.1 of the FSF 1. As a generator 101, any quartz generator of rectangular pulses of the required frequency can be used. EPROM 106 can be implemented on 573 series microcircuits, and logic elements 102, 103, 104 and counter 105 on 133, 134, 155, 155, 555, 176, 561, 564 microcircuits.

 The standby clock driver can be implemented according to the circuit shown in FIG. 3. In particular, the circuit includes a generator 501, two frequency dividers 502 and 506, a logical element And 503, three triggers 504, 505, 507, a logical element "Addition modulo 2" 508.

 The output of the generator 501 is connected to the input 502.1 of the frequency divider 502 and the first input of the And 503 element. The second input of the And 503 element is the input 5.1 of the LFCC 5. The output of the frequency divider 502 is the output of the LFCC 5, in addition, it is connected to the input 505.2 of the trigger 505. The output of the element And 503 is connected to input 504.1 of trigger 504, with input 506.1 of frequency divider 506, input 505.1 of trigger 505, and input 507.1 of trigger 507. The output of frequency divider 506 is connected to input 507.2 of trigger 507. The outputs of triggers 505 and 507 are connected to the corresponding inputs of the “Addition by module 2 "508, the third input of which stick to the body. The output of the element 508 is connected to the input 504.2 of the trigger 504 and the input 506.2 of the frequency divider 506, which, in turn, is the input 5.2 of the LFCC 5.

 As the generator 501, any quartz square wave generator of the desired frequency can be used. All other elements can be implemented on the chips of the series 133, 134, 155, 555, 176, 561, 564.

 Block selection signal cyclic frequency 6 can be implemented according to the scheme shown in figure 4. In particular, the circuit includes a parallel-parallel register 601 and a read-only memory 602. The clock input 601.1 of register 601 is input 6.2, and the information input 601.2 of register 601 is input 6.1 of MSC 6. The register output is k-bit and connected to a k-bit address input of constant storage device 602. The output of the ROM 602 is the output of the MSSC.

 Register 601 can be implemented on the chips of the series 133, 134, 155, 555, 176, 561, 564. The ROM 602 can be implemented on the chips of the series 556, 573.

 The unit for storing signals of clock and cycle frequencies 7 can be implemented according to the scheme shown in Fig.5. In particular, the circuit includes two flip-flops 701 and 702, an oscillator 703, a frequency divider 704. An input 701.1 of a flip-flop 701 is an input 7.1 of the CLCF 7, and an input 702.1 of a flip-flop 702 is an input of 7.2 a CLCF 7. The output of the flip-flop 701 is connected to the input of the generator 703, the output of which is connected with the input 704.1 of the frequency divider 704. In addition, the output of the generator 703 is the output 7.3 of the frequency converter 7. The output of the trigger 702 is connected to the input 704.2 of the frequency divider 704. The output of the frequency divider 704 is the output 7.4 of the frequency converter 7. Inputs 701.2 and 702.2 of the corresponding triggers 701 and 702 are connected through the button to the power and housing.

 As a generator, any quartz rectangular pulse generator can be used, similar to that used in the standby clock frequency shaper, but with a frequency sixteen times lower. All other elements can be implemented on the chips of the series 133, 134, 155, 555, 176, 561, 564.

 The comparison unit 8 can be implemented according to the circuit shown in Fig.6. In particular, the circuit includes four registers 801, 802, 803, 804, two logic elements “Modulo 2 Addition” 805 and 806, AND gate 807. The inputs 801.1 and 801.2 of register 801 and the input 802.1 of register 802 are interconnected and are the input 8.2 comparison unit 8. Input 802.2 of register 802 is input 8.1 of comparison unit 8. Inputs 803.1 and 803.2 of register 803 and input 804.1 of register 804 are interconnected and are input 8.3 of comparison unit 8. Input 804.2 of register 804 is input 8.4 of comparison unit 8. Outputs registers 801 and 802 are connected to the corresponding inputs of the element "Adding mod Ulu 2 "805, the third input of which is supplied with voltage. The outputs of the registers 803 and 804 are connected to the corresponding inputs of the element "Addition modulo 2" 806, the third input of which is also supplied with a supply voltage. The outputs of the logical elements "Addition modulo 2" are connected to the corresponding inputs of the logical element And 807, the output of which is the output of the comparison unit 8.

 All elements of the comparison unit can be implemented on the chips of the series 133, 134, 155, 555, 176, 561, 564.

 The claimed device operates as follows.

The reference frequency generator 2 provides the formation of highly stable oscillations for receiving signals at fixed frequencies. The input of the generator 2 is digital. This input receives code combinations of fixed frequencies from the first output of the shaper control signals 1. The output receives highly stable oscillations to ensure reception at fixed frequencies. From the output of the reference frequency generator 2, highly stable oscillations corresponding to the ith fixed frequency are fed to the heterodyne input of the receiver 3. Receiver 3 provides the reception of signals at fixed frequencies. From the output of the demodulated signal of the receiver 3, the sequence of information packets arrives at the input of the waiting driver of the clock frequency 5, which ensures the formation of pulses of the clock frequency and its adjustment according to the input signal, and to the information input of the block selection signal of the cycle frequency 6, which provides the formation of a sequence of pulses of the cycle frequency and its synchronization with a sequence of informational messages. The pulse frequency clock signal 6 is supplied to the input of the clock frequency signal of the cycle signal separation unit 6 from the output of the standby clock frequency shaper 5. The output of the standby clock frequency shaper 5 is also connected to the first input of the clock and cycle frequency signal storage unit 7, which ensures the preservation of the clock and cyclic synchronization when the information sequence of the packages disappears when the transmitter changes the operating frequency, and to the first input of the comparison unit 8, which provides a comparison of the initial oic cycle and frequency and with a clock cycle frequency of the received signal at the new fixed frequency. The output of the block of selection of the signal of the cyclic frequency 6 is similarly connected to the second input of the unit for maintaining the phase and clock frequency 7 and to the fourth input of the comparison unit. When the receiver 3 is tuned to a new fixed frequency, the clock and cycle synchronization pulses from the outputs of the clock and cycle frequency memory unit 7 and the clock synchronization pulses from the output of the standby clock frequency shaper 5, the cycle synchronization pulses from the output of the cycle frequency signal isolation unit 6 are supplied to the corresponding inputs block comparison, providing the formation of a zero level with the coincidence of the clock and loop frequencies, coming from the outputs of the block memory signals of clock and cyclic frequencies 7 with clock and loop frequencies coming from the outputs of the standby clock shaper 5 and the loop signal isolation block 6. The output of the comparison unit 8 and the first output of the shaper control signals 1 are connected to the corresponding inputs of the indicator 9, which provides displaying the nominal frequency and signaling about her belonging to a controlled transmitter. The output of the comparison unit 8 is connected to the first input of the driver of the control signals, which in the presence of a unit level from the output of the comparison unit 8 produces a code combination of the next fixed frequency. The receiver 3 measures the level of the received signal. In the event of a signal loss at the input of the receiver P _with <P _Tr , the receiver generates a single level, which from the second output of the receiver 3 goes to the second input of the driver of the control signals, which, in turn, generates a code combination of the next fixed frequency. When generating a code combination of a new fixed frequency, the driver of the control signals generates a single pulse, which from the second output of the FSF 1 is fed to the second input of the waiting driver of the clock frequency 5 and brings it to its initial state.

 Shaper control signals 1 operates as follows. The generator 101 generates a sequence of pulses with a frequency f equal to the analysis time of one fixed frequency. The output of the generator 101 is connected to the first inputs of the elements AND 102 and 103. At the second inputs of the elements AND, respectively, the zero or unit levels are output from the output of the comparison unit 8 and the second output of the receiver 3. The outputs of the elements AND are connected to the inputs of the OR element 104. When elements appear at the inputs And a unit level from the comparison unit 8 or receiver 3, an impulse is generated at the output of the OR element, which is fed to the counting input of the counter 105 and to the second input of the standby frequency shaper 5. The counter 105 is m-bit depending on the number of fixed fixed frequencies. The outputs of the counter are connected to the address inputs of the reprogrammable read-only memory 106. The ROM 106 is n-bit. The number of bits n is determined by the length of the code combination of fixed frequencies. The ROM is programmed in such a way that each i-th address corresponds to a code combination of the i-th fixed frequency. The number of EPROM addresses used is equal to the number of fixed frequencies being analyzed. From the outputs of the counter 105 in parallel code, the information defining the address is supplied to the address inputs of the ROM. At the output of the EPROM, a fixed-frequency code combination is generated corresponding to the i-th address, and fed to the input of the reference frequency generator 2 and indicator 9 via an n-bit bus.

 The standby driver 5 clock works as follows. The generator 501 generates a sequence of rectangular pulses with a frequency that is 16 times the manipulation frequency of the observed transmission, which are fed to the counting input of the frequency divider 502 and to the first input of the And 103 element. The sequence of information packets from the output of the demodulated signal of the receiver 3 is fed to the second input of the And 503 element. If the leading edge of the information package coincides with the pulse of the sequence generated by the generator 501, an pulse appears at the output of the AND element, which is fed to the S-input of the trigger a 504. At the output of the trigger 504, a single level appears that allows the frequency divider 502 to work, from the 16th discharge of which a sequence of clock pulses is taken, which is then fed to the corresponding inputs of the loop signal allocation block 6, the clock and loop frequency memory block 7, comparison unit 8. When the receiver is tuned to a new fixed frequency, a single impulse arrives from the second output of the control signal generator 1, which resets the trigger 504, thereby bringing the trigger roystvo to its original state. In order to determine the correspondence of the manipulation speeds of the required signal and the signal observed at the i-th fixed frequency, the pulse from the output of the And 503 element is supplied to the S-inputs of the triggers 505 and 507, which form unit levels, which, in turn, enter the corresponding inputs of the element " Addition modulo 2 ″ 508. In addition, the output of the And 503 element is connected to the counting input of the frequency divider 506, which, when a 16th pulse is received at its input, generates a reset reset trigger 507. A trigger 505 is reset when an impulse arrives at it pulse from the output of the frequency divider 502. If the pulses generated by the triggers 505 and 507 do not coincide, a single level will be formed at the output of the “Modulo 2” module 508, which will reset the trigger 504 to the zero state, which will lead to the installation of the device to its original state and subsequent rebuilding receiver to a new fixed frequency.

 The block selection signal cyclic frequency 6 operates as follows. The clock input of the serial-parallel register 601 receives pulses of the clock frequency from the output of the waiting driver 5, and the information input of the register 601 is a sequence of information packets from the output of the demodulated signal of the receiver 3. The output of the register 601 is k-bit. The number of digits is determined by the length of the cyclic (phasing) combination of the observed transmission or the transmission period by which the phase can be uniquely determined in the absence of cyclic combinations. From the output of register 601, information packets in parallel code are sent to the k-bit address input of read-only memory 602. The ROM is programmed in such a way that a single level at the output of the ROM corresponds only to the address that determines the code combination of the cycle, or if there are no allowed addresses in the transmission of cyclic combinations corresponding to the unambiguous setting of the transmission phase in the text. Upon receipt at the address inputs of the ROM 602 combination of parcels corresponding to the permitted address, the ROM output generates a single pulse. The sequence of these pulses will correspond to the cyclic frequency of the observed transmission.

The unit for storing signals of clock and cycle frequencies 7 operates as follows. The sequence of pulses of the clock frequency from the output of the waiting driver of the clock frequency 5 is fed to the input of the trigger 701 and sets it to a single state. A single level from the output of the trigger 701 starts the generator 703 by supplying power to it. The generator 703 generates a sequence of clock pulses in phase with the waiting driver 5. The output of the generator 703 pulses of clock frequency to the counting input of the frequency divider 704 and to the second input of the comparison unit 8. The output of the signal allocation unit of the cyclic frequency 6 is connected to the S input of the trigger 702. At the R inputs of the triggers 701 and 702, a zero level is applied. In the event that a sequence of pulses of a cyclic frequency is received at the S input of the trigger 702, a single level is formed at the output of the trigger, which is fed to the control input of the frequency divider 707, thereby enabling the recording of clock pulses. Since the clock frequency and cycle pulse edges coincide and period length of frame rate T _i is equal to N clock periods _T F, i.e., T _c N • F _t , then F _c F _t / N. Therefore, the dividing factor of the divider 704 is selected N and the output sequence of the cyclic frequency is removed from the n-th digit of the divider 704, which is connected to the third input of the comparison unit 8. The triggers 701 and 702 are set to zero when a positive pulse is applied to the input R by closing the button "Installation", corresponding to the training of the system in the initial phase of the signal, when tuning to the frequency of another transmitter.

 Block comparison 8 operates as follows. The clock inputs of the registers 801 and 802 are supplied with clock pulses, and the clock inputs of the registers 803 and 804 have cycle pulses from the memory unit of the clock and cycle frequencies 7. Registers 801 804 provide a combination in time of the edges of the pulses from the outputs of the standby clock 5, a block for extracting a signal of a cyclic frequency 6 and a block for storing signals of a clock and cycle frequencies 7. At the information input of a register 802, clock pulses are fed from the output of a waiting clock former 5, the pulses of the clock frequency from the memory unit for clock and cycle frequencies 7 are transmitted to the information input of the register 801. Similarly, the pulses of the clock frequency from the memory unit for clock and cycle signals 7 and the block for extracting the signal of cyclic frequency 6 are fed to the information inputs of registers 803 and 804. pulses of clock frequency from the output of the register 802 is supplied to the first input of the element 805, from the output of the register 801 to the second input of the element 805. A single level is applied to the third input of the element 805. Similarly, the inputs of the element 806 are fed by a sequence of pulses of cyclic frequency from the registers 803 and 804. If the pulses coincide at the inputs of each element, “Modulo 2 addition”, a unit level is formed at the output of the element. The outputs of the elements 805 and 806 are connected to the inputs of the element And 807. If there are unit levels at both inputs of the element And, a zero level is formed at the output, which is fed to indicator 9 and the driver of control signals 1.

 Justification of the positive effect of the proposed device is as follows.

 An indicator of the effectiveness of systems for automatically searching for radio channels is the probability of detecting signals when searching for a new operating frequency (communication channel) of a monitored radio station if, as a result of an interference complex, the communication system is often forced to change operating frequencies to achieve the required communication quality.

 The challenge is to achieve the maximum probability of signal detection at the shortest possible analysis time.

 The probability of detecting a signal at the ith fixed frequency will depend on the probability of a frequency-time coincidence of the receiver tuning frequency with the current operating frequency of the radio station and the probability of identification of the analyzed signal in a time-frequency coincidence.

When the transmitter is tuned to N fixed frequencies, the probability of detecting this transmitter will correspond to the probability of the time-frequency coincidence of the receiver tuning frequency with the current frequency of the desired signal. If we assume that the duration of the channel survey is constant t _c = const, then the period of adjustment for fixed frequencies will be equal to:
TN • t _c ,
where t _{c is the} time during which the i-th fixed frequency is polled;
N is the number of fixed frequencies (Fig. 7).

The receiver tuning speed within the entire search range will be equal to:
γ = Ф _o / T = Ф _o / Nt _c ,
where Ф _{0 is a} band occupied by N frequencies.

где Δt_p время регистрации сигнала, необходимое для его обнаружения;
Δf полоса частот передачи;
τ_c const длительность сигнала, излучаемого на каждой фиксированной частоте.To assess the probability of a frequency-time coincidence of the tuning frequency of the receiver with the current operating frequency of the transmitter, we use the relation (1):

where Δt _{p the} time of registration of the signal necessary for its detection;
Δf transmission frequency band;
τ _c const is the duration of the signal emitted at each fixed frequency.

Так как Δf/γ = t_c время просмотра элементарного участка диапазона (время опроса канала)

Если принять, что время просмотра элементарного участка диапазона равно времени, необходимому для распознавания сигнала t_c= Δt_p, то

где 1≅τ_p/Δt_p< N+1.
Очевидно, что P_совп 0, при τ_c/Δt_p≅ 1, и P_совп 1, если τ_c/Δt_p> N+1 Также очевидно, что вероятность частотно-временного совпадения будет выше при уменьшении времени распознавания. График зависимости P_совп= F(Δt_p) приведен на фиг.8.Given that: Ф _o = γ • Nt _c

Since Δf / γ = t _{c is the} time of viewing the elementary part of the range (channel polling time)

If we assume that the viewing time of the elementary part of the range is equal to the time required for signal recognition t _c = Δt _p , then

where 1≅τ _p / Δt _p <N + 1.
Obviously, P _coincides 0 for τ _c / Δt _p ≅ 1, and P _coincides 1 if τ _c / Δt _p > N + 1. It is also obvious that the probability of time-frequency coincidence will be higher with a decrease in recognition time. The plot of P _coinc = F (Δt _p ) is shown in Fig. 8.

 The recognition time can be reduced and the probability of detection can be increased by introducing into the search process an algorithm for comparing the clock and cycle frequencies of the received signal at the i-th frequency with the initial clock and cycle frequencies of the observed signal.

The signal at each i-th fixed frequency has a clock frequency f _ti and cyclic f _tsi . The desired signal will be the one whose pulses of the clock and cycle frequencies coincide in frequency and time with the reference sequences of pulses of the clock and cycle frequencies (the initial clock and cycle frequencies of the observed signal) (Fig. 9).

Here: f _{t et} stream of pulses of the clock frequency of the reference signal; f _{c et the} pulse stream of the cyclic frequency of the reference signal; f _ti and f _qi pulse flows, respectively, of the clock and cycle frequencies of the signal at the i-th frequency.

где σ заданная длительность перекрытия импульсов;
T_s период следования импульсов s-го потока (фиг.10);
t_s- длительность импульсов s-го потока.The probability of coincidence of n pulsed deterministic flows on the period T ¹ is determined by the formula (2):

where σ is the specified duration of the pulse overlap;
T _s the pulse repetition period of the s-th stream (figure 10);
t _s is the pulse duration of the s-th stream.

Вероятность совпадения эталонных потоков с потоками импульсов на любой из N последовательно анализируемых частот равна сумме вероятностей совпадения эталонных потоков с потоками на каждой i-й фиксированной частоте.When searching for the required signal, four pulse flows are compared. These are the pulse flows of the clock and loop frequencies of the signal at the i-th frequency and the reference flows of pulses of the clock and loop frequencies of the observed signal. Taking into account that the pulse durations of all flows are the same, we can write:

The probability of the coincidence of the reference flows with the flows of pulses at any of the N sequentially analyzed frequencies is equal to the sum of the probabilities of the coincidence of the reference flows with the flows at each ith fixed frequency.

Так как период анализа T¹, длительность импульсов τ_s и длительность перекрытия σ постоянны, то можно записать:

Данное выражение определяет вероятность совпадения одного импульса всех четырех потоков на интервале времени T¹. Вероятность совпадения k следующих подряд импульсов будет соответствовать произведению k вероятностей совпадения одного импульса на периоде T_{s эт} эталонного потока, что можно записать в виде:

где k T¹/T_{s эт} количество сравниваемых импульсов за период анализа. В связи с тем, что сравнение потоков происходит попарно (двух потоков тактовой частоты и двух потоков цикловой частоты) имеем два периода эталонных потоков:
T_{s эт.т} период импульсной последовательности тактовой частоты;
T_{s эт.ц} период импульсной последовательности цикловой частоты.

Since the analysis period T ¹ , the pulse duration τ _s and the overlap duration σ are constant, we can write:

This expression determines the probability of coincidence of one pulse of all four streams in the time interval T ¹ . The probability of coincidence of k consecutive pulses will correspond to the product of k probabilities of coincidence of one pulse on the period T _{s et} reference flow, which can be written as:

wherein k T ¹ / T _{s et} number of compared pulses during the analysis period. Due to the fact that the flows are compared in pairs (two clock frequencies and two cycles), we have two periods of reference flows:
T _{s et.t} period of the pulse sequence of the clock frequency;
T _{s etc} period of the pulse sequence of the cyclic frequency.

Отсюда вытекает, что при совпадении всех импульсов на анализируемом периоде всех четырех потоков на какой-то i-й фиксированной частоте вероятность идентификации требуемого сигнала будет равна: P_ид 1 P_n, или

Полная вероятность обнаружения требуемого сигнала при смене рабочей частоты будет равна произведению вероятностей частотно-временного совпадения частоты настройки приемника с текущей рабочей частотой искомого передатчика P_совп и вероятности идентификации искомого сигнала P_ид.Then the probability of coincidence of all pulses of the four analyzed flows on the period T ¹ takes the form:

It follows that if all the pulses coincide in the analyzed period of all four streams at some i-th fixed frequency, the probability of identifying the desired signal will be: P _id 1 P _n , or

The total probability of detecting the required signal when changing the operating frequency will be equal to the product of the probabilities of the time-frequency coincidence of the receiver tuning frequency with the current operating frequency of the desired transmitter P _coinc and the probability of identification of the desired signal P _id .

При условии, что частотно-временное совпадение произошло при заданных значениях длительности импульсов τ_s и длительности перекрытия σ, вероятность обнаружения искомого сигнала будет зависеть от времени распознавания, количества сравниваемых потоков, числа подлежащих совпадению импульсов. На (фиг. 11) представлены графики зависимостей вероятности обнаружения от времени распознавания для следующих случаев:
1 обнаружение производится при совпадении одного импульса четырех потоков;
2 обнаружение производится при совпадении k импульсов двух потоков тактовой частоты;
3 обнаружение производится при совпадении k импульсов всех четырех потоков.

Provided that the time-frequency coincidence occurred at the given values of the pulse duration τ _s and the overlap duration σ, the probability of detecting the desired signal will depend on the recognition time, the number of compared streams, and the number of pulses to be matched. On (Fig. 11) presents graphs of the dependencies of the probability of detection on the recognition time for the following cases:
1 detection is performed when one pulse of four streams coincides;
2, detection is performed when k pulses coincide with two clock frequencies;
3, detection is performed when k pulses of all four streams coincide.

When calculating the probability of detection, we assume that the pulse repetition period of signals on any i-th reference frequency and the same T _s T _{s IT et.t, its} T _s T _s and T _{et.ts with et.ts} 7T _{s et.t.} For simplicity of calculations, it is assumed that at a transmission rate of 100 Baud T _{s et.t.} 10 ms, t _s - σ = 1 ms.
It can be seen from the graphs that the maximum probability of detecting the desired signal will be when all of the following pulses of four streams coincide over the entire time the signal is emitted at the ith fixed frequency. In this case, the probability of detection is close to unity (P _obn 1).

The shortest possible recognition time corresponds to the repetition period of the clock pulses of the reference stream, but in this case the detection process will be carried out by comparing the two streams of clock pulses. The probability of detection in this case will be quite high, but lower than in the case of a comparison of four streams. Therefore, the recognition time T ¹ Δt _p can take values:
T _{s et.t} ≅ Δt _p <τ _c ,
where T _{s et.t} the pulse repetition period of the clock frequency of the reference stream;
τ _{c is} the signal emission time at the ith fixed frequency.

The optimal recognition time should be taken as the repetition period of the pulses of the cyclic frequency of the reference stream. Δt _p T _{s et.c} , but depending on the tasks to be solved, the recognition time can be selected based on the priority of the maximum probability of detection over the recognition time or vice versa.

 A comparative analysis of the known device and the proposed technical solution shows that the probability of detection increases from 0.5 to 0.99 for typical operating conditions. This confirms the significant positive effect of the introduction of the new device.

References:
1. Martynov V. A. Selikhov Yu. I. Panoramic receivers and spectrum analyzers. M. Sovetskoe Radio, 1964.

 2. Sedyakin N.M. Elements of the theory of random pulsed flows. M. Soviet Radio, 1964.

Claims (1)

 A device for automatically searching for radio stations containing a receiver, the signal detector is connected to the output of the demodulated signal, the output of which is connected to the input of the driver of the control signals, the output of the signal of the fixed frequency code of which is connected to the control input of the reference frequency generator connected to the heterodyne input of the receiver, characterized in that the output signal for monitoring the presence of the receiver signal is connected to the second input of the driver of the control signals, the signal output is "initial setting" ohm is connected to the input of the initial installation of the signal detector, and the output of the fixed-frequency code signal is additionally connected to the indication input of the signal detector, the signal detector consisting of a standby driver of a clock frequency, a block for extracting a signal of a cycle frequency, a block for storing signals of a clock and cycle frequencies, a comparison unit, an indicator, the first input of which is an indication input of the signal detector, and the output of the comparison unit is connected to the second input of the indicator, which in turn is I am the output of the signal detector, in addition, the information input of the standby clock driver is connected to the information input of the loop signal allocation unit and is the information input of the signal detector, the second input of the standby clock driver is the input "Initial setting" of the signal detector, the output of the standby clock driver connected to the inputs of the clock frequency signal of the unit for extracting the signal of the cyclic frequency, the unit for storing signals of the clock and cycle frequencies and the unit alignment, and the output signal selection block cyclic frequency is connected to the inputs of the cyclic frequency clock signal storing unit and the cyclic frequency and the comparator, in addition, the output signal of the reference frequency cycle and memory clock signals of cyclic frequency unit connected to the respective inputs of the comparator.

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