RU2422982C2 - Signal search device - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: signal search device includes control unit, reference frequency unit, receiver of radio signals, indication unit, triggered shaper of clock frequency, clock frequency memory unit, logic EXCLUSIVE OR element, phase difference shaper, comparing unit and shaper of threshold levels.

EFFECT: reducing the time for detection of communication channels at frequent frequency changes with radio stations in complicated interference conditions.

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Description

The invention relates to the field of radio engineering and can be used in radio dispatch monitoring points for the analysis of the signal situation in the region and for the automatic search and detection of signals from radio stations that constantly change operating frequencies.

A device for the automatic search of radio channels containing a reference frequency block, a radio signal receiver, a signal converter, registers, a driver of a control signal, a multiplexer, a demultiplexer, several registers, a pulse distributor, a comparison unit, an initial installation unit and an indicator [USSR copyright certificate No. 1515373, IPC H04B 1/10, 1989].

The disadvantage of this device is the relatively long duration of the frequency search process, and with frequent changes by radio stations of operating frequencies, this device does not provide an acceptable delay in detecting a working communication channel.

The closest in technical essence, adopted as a prototype, is a device for automatic search for radio stations [Arkhipenko A.A., Gorin D.G. and other device for the automatic search for signals of radio stations. RF patent No. 2132111, IPC H04B 1/10 dated 06/20/99, bull. No. 17, 1999]. This device contains a control unit, the code output of which is connected to the code input of the display unit and is connected to the local oscillator input of the receiver through the reference frequency unit. The information input of the waiting clock driver is connected to the output of the demodulated signal of this receiver, the pulse output of which is connected to the input of the clock memory. An output for monitoring the presence of a receiver signal is connected to the first input of the control unit and connected to the control inputs of the phase difference former and the comparison unit. The first input of the comparison unit is connected to the output of the phase difference former, and the second and third inputs of the comparison unit are connected to two outputs of the threshold level former. The locking output of the comparison unit is connected to the control input of the display unit and the second input of the control unit, and the command output of the comparison unit is connected to the third input of the control unit, the installation output of which is connected to the installation inputs of the standby clock frequency shaper, phase difference shaper and threshold level shaper. As part of the phase difference shaper and threshold level shaper, summing pulse counters and digital-to-analog converters were used, and analog comparators were used in the circuit of the comparison unit.

This device provides a search for signals of radio stations, often changing operating frequencies, by storing the clock frequency of the received signal and its subsequent comparison with the clock frequency of the signal at each k-th frequency. The decision on whether the signal belongs to the kth fixed frequency of the radio station of interest is made when the frequency and time of arrival of the pulse fronts of the compared frequencies coincide, which increases the probability of detecting the signal of the desired radio station.

However, this prototype device has the following disadvantages.

When searching for the clock frequency of the desired radio station in a known device, the phase difference between the reference and received sequences of clock pulses is allocated, which is compared with an acceptable level. When conducting radio monitoring in a complex jamming environment, there may be a fluctuation of the fronts of the clock pulses. In this case, the coincidence of the edges of the compared pulses may not occur, although in reality they belong to the same signal, and this leads to a decrease in the probability of detecting the signal of the desired radio station. In addition, the separation and comparison of the phases of the pulse sequences is performed in analog form using digital-to-analog converters and analog comparators, which complicates the structure of the device and does not allow it to be implemented on modern reprogrammable digital microcircuits.

The technical result to which the invention is directed is to reduce the detection time of communication channels with frequent changes of operating frequencies by the observed radio stations in a difficult jamming environment and simplify the structure of the device.

To achieve this technical result, a known device for automatically searching for radio station signals, comprising a control unit, the code output of which is connected to the code input of the display unit and connected through a reference frequency unit to the heterodyne input of the radio signal receiver, to the output of the demodulated signal of which the information input of the standby clock frequency driver is connected the pulse output of which is connected to the input of the clock memory unit, and the output of the control of the presence of the signal of the radio receiver the signals are connected to the first input of the control unit and to the control inputs of the phase difference generator and the comparison unit, the first input of which is connected to the output of the phase difference generator, the second and third inputs of the comparison unit are connected to two outputs of the threshold level driver, the fixing output of the comparison unit is connected to the control input the display unit and the second input of the control unit, the command output of the comparison unit is connected to the counting input of the threshold level former and to the third input of the control unit, setting the output of which is connected to the installation inputs of the standby frequency driver, phase difference driver and threshold level driver, an exclusive OR gate has been introduced. In this case, the first and second inputs of the exclusive OR logic element are connected, respectively, to the input and output of the clock memory, and the output of the exclusive OR logic element is connected to the information input of the phase difference driver, the phase sign of which is connected to the control output of the standby shaper clock frequency. The counting input of the phase difference former is connected to the gate output of the waiting clock frequency former.

As a phase difference shaper, a reversible pulse counter and a memory register were used, and digital comparators were used in the comparison unit, the first outputs of which are connected to two inputs of the 2I logic element, the output of which is the fixing output of the comparison unit, and the second outputs of the comparators are connected to the inputs of the 2 OR element, the output of which is the command output of the comparison unit.

The analysis of the prior art made it possible to establish that analogues, characterized by a combination of features, are identical to all the features of the claimed technical solution, are absent, which indicates compliance of the claimed device with the patentability condition of "novelty". Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the impact provided by the essential features of the claimed invention, the transformations on the achievement of the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed invention is illustrated by the following figures:

figure 1 is a structural diagram of a device for searching for signals;

figure 2 is a structural diagram of a control unit;

figure 3 is a structural diagram of a waiting driver of the clock frequency;

4 is a structural diagram of a memory block clock frequency;

5 is a structural diagram of a phase difference shaper;

6 is a structural diagram of a comparison unit;

7 is a structural diagram of a threshold level generator.

The signal search device, the structural diagram of which is shown in FIG. 1, contains a control unit 1, a reference frequency unit 2, a radio signal receiver 3, an indication unit 4, a standby frequency former 5, a memory unit 6, an exclusive OR logic element 7 , a phase difference shaper 8, a comparison unit 9, and threshold level shaper 10.

The code output 1.5 of the control unit 1 is connected to the code input of the display unit 4 and through the reference frequency unit 2 to the heterodyne input of the radio signal receiver 3. The output of the demodulated signal 3.1 of the radio signal receiver 3 is connected to the information input of the standby clock shaper (LFTC) 5, pulse output 5.1 which is connected to the input of the memory block clock frequency (BZTCH) 6 and the first input of the logic element "Exclusive OR" 7. The second input of the logic element "Exclusive OR" 7 is connected to the output of the BZTC 6. Output 7.1 logic of the exclusive "OR" element 7 is connected to the information input of the phase difference former 8, the input of the phase sign of which is connected to the control output 5.2 of the VFTC 5, and the counting input of the phase difference generator 8 is connected to the pulse output 5.1 of the VFTC 5. In addition, the control output 8.1 of the shaper the phase difference 8 is connected to the first control input of the comparison unit 9, and the output for monitoring the presence of the signal 3.2 of the radio signal receiver 3 is connected to the first input 1.1 of the control unit 1, the control input of the phase difference shaper 8 and the second control input comparison unit 9. The installation inputs of the phase difference driver 8 and the high-frequency converter 5 are combined with the installation input of the threshold level driver 10 and connected to the installation output 1.4 of the control unit 1. The fixing output 9.1 of the comparison unit 9 is connected to the control input of the display unit 4 and the second input 1.2 of the control unit 1, the third input 1.3 of which is connected to the counting input of the threshold level generator 10 and connected to the command output 9.2 of the comparison unit 9. Digital codes at the outputs 10.1 and 10.2 of the threshold level generator 10 are set lower s and upper threshold levels of the phase difference between the pulses in the reference block 9.

A device for searching for signals of radio stations works as follows.

To identify the signal of the desired radio transmitter when it changes the operating frequency, the values of the clock synchronization of the received signal are stored in the BZTCH 6 by forming the pulses of the initial clock frequency in the LFCH 5 and its subsequent comparison with the pulses of the clock frequency of the signal turned on at the new frequency is performed. The decision on whether the signal belongs to the new transmitter at the new fixed frequency is made when the edges and slices of the pulses of the sequences being compared in sequence coincide in the time domain. When conducting a radio reception in real conditions, due to the influence of the noise environment, instability of the clock synchronization generators at the transmitting and receiving ends, the coincidence of the edges of the compared pulses may not occur, since the time shift of the edges and slices of the pulses relative to each other by Δt _FR or Δt _SR respectively.

In the claimed device, the decision-making process on the coincidence of pulses is reduced to the constant measurement of the difference in the values of Δt _FR or Δt _CP (the difference in time intervals between the edges and slices of the compared pulses) and its subsequent comparison by digital comparators of the comparison unit 9 with threshold code values specified in the threshold level generator 10. Based on the results of this comparison, commands are sent to the control unit 1 from the comparison unit 9, either to fix the frequency in the block of reference frequencies (for a small duration difference Δt = Δt _FR -Δt _SR ≤t _ADD ), or to switch the frequency (at Δt = Δt _FR -Δt _SR > t _ADD ).

The block of reference frequencies 2 provides the formation of highly stable oscillations for receiving signals at fixed frequencies and has a digital input to which the output combinations of control unit 1 receive code combinations of fixed frequencies. Highly stable oscillations corresponding to the k-th fixed radio frequency are received from the output of the reference frequency block 2 to the heterodyne input of the radio signal receiver 3. The receiver of radio signals 3 provides the reception of signals at fixed frequencies. From the output of the demodulated signal 3.1 of the receiver of the radio signals 3, the sequence of information packets arrives at the input of the ZHFCH 5, which ensures the formation of a sequence of pulses of the clock frequency and its adjustment according to the input signal. Pulses of the clock frequency from the output 5.1 of the LFCC 5 are fed to the input of the BZTC 6, which generates a similar sequence of pulses of the clock frequency in phase with the pulses generated by the LFCC 5, and ensures its conservation in the event of a disappearance of the signal at the output 3.1 of the radio signal receiver 3. In addition, the radio signal receiver 3 controls the level of the received signal, and in the event of the disappearance of the radio signal at the output 3.2 of the receiver of radio signals 3, a high logic level is formed, which is fed to the input 1.1 of the control unit 1. and the output 1.5 the new code to set the next fixed frequency control unit 1 is formed in the reference frequency block 2.

When a new code appears, the control unit 1 generates a single impulse, which from the output 1.4 enters the inputs of the ZHFCH 5 installation, a phase difference shaper 8, threshold level shaper 10 and brings the device data to its initial state. If there is a signal at the newly tuned frequency, the output of the radio signal receiver 3 generates a low logic level, which allows the operation of the phase difference driver 8 and the comparison unit 9. At the same time, the ZHFCH 5 generates clock pulses for a new sequence of information packets that arrives at the first input of the logical XOR element 7, and a sequence of gating pulses with a frequency of 32 times the clock frequency, which from the output 5.2 of the LFCC 5 goes to the input of the phase difference shaper 8.

The second input of the exclusive-OR logic element 7 receives pulses of the reference clock frequency from the output of 6.1 BZTCH 6. Moreover, at the output of the exclusive-OR element 7 pulses are generated with a frequency twice the clock frequency, the duration of which corresponds to the difference of time intervals between fronts Δt _FR and slices Δt _{CP of} each pair of compared pulses. In the phase difference shaper 8, a digital measurement of the durations Δt _ФР and Δt _{СР of the} output pulses of the Exclusive OR element 7 is performed using a reversible counter, which sums the strobe pulses coming from the output 5.2 of the LPFCH 5 during the time interval Δt _ФР and performs subtraction of the strobe pulses during the time interval Δt _SR . The command to change the operating mode of the phase difference shaper 8 (performing the summation or subtraction of the strobe pulses) is issued from the output 5.1 of the LPFCH 5. After the end of each pulse with a duration Δt _CP , a difference code ΔN = (Δt _ФР -Δt _СР ) · f _С , which is stored in the memory register of the phase difference shaper 8 and compared in the comparison unit 9 with the threshold values of the code N ₁ and N ₂ , which are supplied from the outputs 10.1 and 10.2 of the shaper of threshold levels 10. In case the code N ₂ <ΔN <N ₁ then the comparison unit 9 pr decides on the coincidence of the compared pulses and generates a single level at the output 9.1, which is fed to the control input of display unit 4, which displays the nominal frequency of the fixed frequency and signals its ownership to the desired transmitter, and to input 1.2 of control unit 1, providing fixation of the receiver settings at this frequency . If the code N ₂ >ΔN> N ₁ , then the comparison unit 9 generates a single signal level at the output 9.2, indicating the mismatch of the compared pulses, and hence the non-belonging of the observed signal to the desired transmitter, which is fed to the counting input of the threshold level generator 10 and to the command input 1.3 of the control unit 1, which generates a new code for tuning the radio signal receiver 3 to a new fixed frequency.

The circuit of the control unit 1, shown in figure 2, contains a pulse generator 11, a majority element 12, a pulse counter 13, reprogrammable read-only memory (PROM) 14 and works as follows. The generator 11 generates pulses with a frequency y opposite to the analysis time of one fixed radio frequency of the radio signal receiver 3. The output of the generator 11 through the majority element 12 is connected to the counting input of the counter 13, and the second 1.1 and third 1.3 inputs of the majority element 12 receive pulses from the output 3.2 of the radio signal 3 and from the output 9.2 of the comparison unit 9, respectively. When a single signal level appears at the output 9.2 of the comparison unit 9 or at the output 3.2 of the radio signal receiver 3, a pulse is generated at the output of the majority element 12, which is fed to the counting input of the counter 13 and to the output 1.4 of the control unit 1. The outputs of the counter 13 are connected to the address inputs of the EPROM 14 having n bits, the number of which is determined by the length of the code combination of fixed frequencies. The ROM is programmed in such a way that each k-th address corresponds to a code combination of the k-th fixed frequency. The number of addresses used in EEPROM 14 is equal to the number of analyzed fixed frequencies. From the outputs of counter 13, information in a parallel code is supplied to the address inputs of EEPROM 14. At the output of EEPROM, a fixed-frequency code combination is generated corresponding to the k-th address, which in parallel code from outputs 1.5 is fed via an n-bit bus to the inputs of the reference frequency unit 2 and display unit 4. The output of the mth discharge of the counter 13 is connected to its reset input to set the counter to its initial state after analysis of the mth frequency. A counter signal 13 receives a single signal level from the output 9.1 to the P-input of the resolution of the counting of the counter when a decision is made on the coincidence of pulses by the comparison unit 9, which prohibits the operation of the counter 13 and thereby fixes the tuning of the radio signal receiver 3 at the kth fixed frequency.

The standby frequency driver 5 (FIG. 3) comprises a high-frequency pulse generator 51, triggers 52, 53, a frequency divider 54, and operates as follows. The generator 51 generates pulses with a frequency 64 times higher than the frequency of manipulation of the observed transmission, which are received at the C-input of trigger 52. Information packets from the output 3.1 of the radio signal receiver 3 are fed to the D-input of this trigger 52. When a single level of information packet appears trigger 52 triggered by the front of the pulse generated by the generator 51, and its output signal is fed to the S-input of the second trigger 53. At the output of the trigger 53 appears a single signal level, which allows the work of the frequency divider 54. On the counting -input of the frequency divider 54, high-frequency pulses from the generator 51 are supplied. From the sixth digit of the frequency divider 54, a sequence of clock pulses is taken, which is fed to output 5.1 and then fed to the memory block clock frequency 6 and to one input of the exclusive OR logic element 7. From the first discharge of the frequency divider 54, the output 5.2 receives gating pulses with a frequency 32 times the clock frequency, which are then fed to the input of the phase difference former 8. When the radio signal receiver 3 is tuned to oic fixed frequency output 1.4 the control unit 1 receives a single pulse on the R-inputs of zero-setting flip-flops 52 and 53, which resets them, thereby causing the device to its original state.

The memory unit clock frequency 6 (figure 4) contains a high-frequency pulse generator 61, a frequency divider 62, a trigger 63, an operating mode switch 64 and operates as follows. The high-frequency pulse generator 61 generates pulses with a frequency 64 times the clock frequency, similar to the high-frequency pulse generator 51 of the ZHFTC 5, which are fed to the counting C-input of the frequency divider 62. From the output 5.1 of the ZHFCH 5, the clock pulses are fed to the R-input of the trigger 63 , to the S-input of which a zero voltage level is supplied through the switch 64. When a clock pulse arrives at the R-input of the trigger 63, a zero level is formed at its output, which is fed to the R-input of the frequency divider 62, allowing its operation . The pulse sequence of the reference clock frequency is removed from the sixth bit of the frequency divider 62 and fed to the second input of the exclusive-OR element 7, the output of which is connected to the input of the phase difference driver 8. The trigger 63 is set to a single state when a positive pulse is applied to its S-input switch 64, which corresponds to the training system initial clock frequency, in particular when tuning the receiver to the frequency of another radio transmitter.

The phase difference generator 8 (Fig. 5) contains a reversible pulse counter 81 and a memory register 82 and works in conjunction with the exclusive OR gate 7 as follows. From the output 5.2 of the GFCF 5, the gate pulses with a frequency of f _C , 32 times the clock frequency, are fed to the counting C-input of the reversible counter 81. To the first input of the exclusive OR gate 7, to the reverse input (± 1) of the reversible pulse counter 81 and the C-input of the memory register 82 receives pulses of the clock frequency from the output 5.1 of the LFTC 5. The second input of the logic element "Exclusive OR" 7 receives the pulses of the reference clock frequency from the output of 6.1 BZTC 6. At the same time, the output 7.1 of the logic element "Exclusive OR" 7 pulses appear, for a long time five of which corresponds to the difference of time intervals between edges Δt Δt slices _DF and _SR pulses coming from the outputs of 5.1 and 6.1 respectively. These pulses from the output of the 7.1 exclusive-OR logic element 7 are fed to the P-input of the counter enable counter of the pulse counter 81. If there is a pulse at the reverse input ± 1 of the reverse pulse counter 81 operates in the mode of summing the counter pulses of frequency f _C for a time Δt _FR , and the output of the reversible pulse counter 81 produces a binary code corresponding to the number of strobe pulses between the edges of the compared pulses: N _FR = Δt _FR · f _C. In the pauses between pulses at the reverse input ± 1, the reversible pulse counter 81 operates in the mode of subtracting the counting pulses of frequency f _C for the time Δt _СР , and at the end of the time Δt _СР forms the difference code ΔN = (Δt _ФР -Δt _СР ) · f _С. Therefore, the difference code ΔN = (Δt _ФР -Δt _СР ) · f _С is generated at the outputs of the reversible counter 81 for two clocks of digital measurement; it is written into the memory register 82 along the edge of each pulse on output 5.1 of the LPTC 5. From the outputs of the memory register 82, the code ΔN arrives the output 8.1 of the phase difference shaper for subsequent comparison in the comparison unit 9 with the threshold values of codes N ₁ and N ₂ coming from the shaper of threshold levels 10.

The operation of the reversible pulse counter 81 is allowed at a single signal level at the output of the 7.1 exclusive-OR logic element 7. The zeroing of the reverse pulse counter 81 and the initialization of the phase difference 8 to the initial state are carried out when a single pulse from the output is received at the R-input of the reverse pulse counter 81 1.4 control unit 1.

The comparison unit 9 (Fig.6) contains digital comparators 91, 92, logic element 2 OR 93, logic element 2I 94 and works as follows. From the output 8.1 of the phase difference generator 8, a difference code ΔN is received, which is compared by digital comparators 91 and 92 with the threshold values of codes N ₁ and N ₂ supplied from the outputs 10.1 and 10.2 of the threshold level generator 10. The outputs of the digital comparator 91 and 92 are connected in pairs to the inputs logic element 2 OR 93 and logic element 2I 94. From the output 10.1 of the threshold level generator 10, the lower threshold level code N ₁ is supplied to the inputs “A” of the digital comparator 91. The digital comparator 91 compares the codes ΔN and N ₁ . If the inequality ΔN> N ₁ is fulfilled, then the digital comparator 91 generates a single signal level, which passes through the logic element 93 of type 2 OR, and from the output 9.2 of the comparison unit 9 goes to the input 1.3 of the shaper of control signals 1, giving a command to the control unit 1 to generate a new code fixed frequency. If the reverse inequality ΔN <N ₁ is fulfilled, then a single signal level appears at the second output of the digital comparator 91, which is connected to the input of the logic element 94 of type 2I. Similarly, the second digital comparator 92 compares the code N ₂ coming from the output 10.2 of the threshold level generator 10 with the code ΔN. If the code ΔN is less than the code N ₁ and more than the code N ₂ , then at both inputs of the logic element 94 of type 2I there will be high levels of logic signals. At the same time, at output 9.1, a single level appears, which goes to the control input of display unit 4, signaling that the signal belongs to the k-th fixed frequency to the desired transmitter, and to input 1.2 of control unit 1, fixing the tuning of the radio signal receiver 3 to this frequency. When the signal disappears at the input of the receiver of radio signals 3, a single level appears at the output of the control signal 3.2, which is fed to the control inputs of the digital comparators 91, 92, bringing the comparison unit 9 to its initial state.

The threshold level generator 10 (Fig. 7) contains a digital pulse counter 101, reprogrammable read-only memory devices 102, 103 and operates as follows. From the output 9.2 of the comparison unit 9, the pulses are fed to the C-input of a digital pulse counter 101, which counts the number of these pulses. The number of binary bits in the digital pulse counter 101 is selected based on the analysis period (the number of compared clock pulses, according to which a decision is made on their coincidence). The code from the output of the digital pulse counter 101 is fed to the address inputs of the EEPROM 102 and 103. The lower threshold values of the code N _{1 are} programmed in the memory of the EEPR 102, and the values of the upper threshold level N ₂ are stored in the EEPROM 103. The number of bits of the output code in both EPROMs is the same as that of the memory register 82 of the phase difference shaper 8, and is determined by the maximum number of strobe pulses corresponding to the value by which a decision is made on the coincidence of the clock pulses. From the outputs of the EEPROM 102 and 103, the code combinations of the lower N ₁ and upper N ₂ threshold levels corresponding to each clock pulse are fed via n-bit buses 10.1 and 10.2 to the inputs of the digital comparators 91 and 92 of the comparison unit 9. Resetting the digital pulse counter 101 and bringing the threshold level generator 10 to the initial state is carried out upon receipt of a unit level digital pulse counter 101 at the R-input from output 1.4 of control unit 1.

Practically, as the main functional units of the device, you can use standard digital microcircuits of the K564, K561 series.

In the control unit 1, the quartz pulse generator 11 can be implemented on the chip K564AG1 [Shilo V.L. Popular CMOS chips. - M .: Jaguar, 1993. - P.62], the majority element 12 is on the K561LP13 chip, counter 13 is on the K561IE14 chip, PRZU 14 is on the 573 series chips [Digital and analog integrated circuits: Reference / Ed. S.V.Yakubovsky. - M.: Radio and Communications, 1990 p. 298-314].

As a block of reference frequencies 2 and receiver 3, you can use a commercially available radio receiver P-399A "Katran", where these blocks are technically implemented. As indicator 4, any commercially available digital indicator can be used.

In the standby frequency driver 5, the generator 51 is similar in structure to the generator 11, and K561TM2 type microcircuits can be used as triggers 52, 53, and the K561IE16 microcircuit can be used as a frequency divider [Shilo V.L. Popular CMOS chips. - M .: Jaguar, 1993. - S.25, 34, 62].

In the memory block of the clock frequency 6, the K561TM2 chip can be used as a trigger 63, and the K561IE16 chip is used as the frequency divider 62, the K564AG1 chip is used in the generator 61, and the switch 64 is implemented on the K561KP1 chip [Shilo V.L. Popular CMOS chips. - M .: Jaguar, 1993. - S.25, 34, 23]. Element 7 "Exclusive OR" can be implemented on the chip K561LP2 [Shilo V.L. Popular CMOS chips. - M .: Jaguar, 1993. - P.18].

In the phase difference shaper 8, the reverse counter 81 can be assembled on the K561IE11 chip, and the register 82 - on the K561IR9 chips [Shilo V.L. Popular CMOS chips. - M .: Jaguar, 1993. - S. 32, 41].

In the comparison unit 9, it is possible to implement comparators 91, 92 on the K561CA1 microcircuit, element 2I 94 on the K561LA7 microcircuit, element 2OR 93 on the K561LE5 microcircuit [Shilo V.L. Popular CMOS chips. - M .: Jaguar, 1993. - S.18-21]. In the threshold level shaper 10, it is possible to make a pulse counter 101 on the K561IE11 chip and implement the ROMs 102 and 103 on the 537 series chips. In addition, all of the listed units 5-10 of the device can be implemented programmatically on foreign electrically programmable logic matrices of Analog Devises.

The positive effect in the proposed device can be justified as follows.

An indicator of the effectiveness of systems with automatic search for radio channels is the probability of detecting signals when searching for a new operating frequency (communication channel) of the observed radio station if, as a result of interference, the communication system is often forced to change the operating frequencies to achieve the desired communication quality.

The challenge is to increase the probability of signal detection at the shortest possible time of RF analysis.

In case of discrete tuning of the radio transmitter with N fixed frequencies, the probability of its detection depends on the time-frequency coincidence of the receiver tuning frequency with the current frequency of the desired signal. With a constant polling duration of each channel t _K = const, the tuning period for fixed frequencies T = N · t _K depends on the polling time interval t _{K for} each fixed frequency and the total number N of such frequencies.

The recognition time can be reduced and the probability of detection can be increased by comparing the pulses of the initial clock frequency of the received signal with the sequences of clock pulses of the signals at each fixed frequency. If there is a frequency-time coincidence of the tuning frequency of the receiver with the operating frequency of the transmitter, the probability of correct detection of the communication channel depends on the analysis period, the number of compared pulses and the specified values of the pulse duration and duration of their overlap. In the proposed device, the durations are monitored not only between the fronts Δt _{FR of the} compared pulses (as in the prototype), but also between the slices Δt _{CP of} these pulses, which, with the same probability of detecting the desired radio channel, can halve the search time for the desired frequency.

It is possible to increase the probability of detection to a level of P _OBN ≈0.99 with an analysis time equal to two repetition periods of the clock pulses (during the transmission time of two chips), but provided that the signal is qualitatively received when its temporal distortions do not exceed 10% of duration of the elementary premise. If the reception quality in the prototype device is poor, it is necessary to increase the analysis period to 7 chips to ensure that the desired communication channel is detected to a level of P _OBN > 0.95 when evaluating the duration of time intervals between the edges of the compared pulses.

In the proposed device, a similar probability of detecting the desired communication channel is provided for a maximum of 4 elementary parcels even in difficult interference conditions in the communication channel.

Therefore, the claimed device allows for the timely search for signals of radio stations, often changing operating frequencies, with a rather high probability of detection in a short analysis time. Depending on the tasks to be solved, the recognition time can be selected based on the priority of the maximum probability of detection over the recognition time or vice versa. This confirms the significant positive effect of the use of the proposed device.

In addition, the implementation of the main functional units of the device only on digital microcircuits allows to simplify its complexity, for example, through the use of modern electrically reprogrammable logic matrices, which provides an additional opportunity to increase reliability, reduce overall dimensions and power consumption of the device.

Claims (3)

1. A signal search device comprising a control unit, the code output of which is connected to the code input of the display unit and connected through the reference frequency unit to the heterodyne input of the radio signal receiver, to the output of the demodulated signal of which is connected the information input of the waiting clock driver, the pulse output of which is connected to the input a clock frequency storage unit, and the output of the presence of a receiver signal is connected to the first input of the control unit and to the control inputs of the difference shaper fa h and the comparison unit, the first input of which is connected to the output of the phase difference former, the second and third inputs of the comparison unit are connected to two outputs of the threshold level former, the fixing output of the comparison unit is connected to the control input of the display unit and the second input of the control unit, the command output of the comparison unit is connected to the counting input of the threshold level driver and the third input of the control unit, the installation output of which is connected to the installation inputs of the waiting clock driver, phase difference shaper and threshold level shaper, characterized in that an exclusive OR gate is added to it, the first input of which is connected to the input of the phase sign of the phase difference shaper and connected to the input of the clock storage unit, the output of which is connected to the second input of the element An exclusive OR, the output of which is connected to the information input of the phase difference former, and the counting input of the phase difference former is connected to the gate output of the waiting clock former. 2. The signal search device according to claim 1, characterized in that a reverse pulse counter with a memory register is used as a phase difference shaper. 3. The signal search device according to claim 1, characterized in that the digital comparators are used in the comparison unit, the first outputs of which are connected to two inputs of the logic element 2I, the output of which is the fixing output of the comparison unit, and the second outputs of the comparators are connected to the inputs of the 2OR element, the output of which is the command output of the comparison unit.

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