RU2476923C1 - Apparatus for majority signal selection - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: apparatus for majority signal selection has: a majority element (1), n counters-latches (2₁-2_n), an adder (3), n comparators (4₁-4_n), a control unit (5), n demultiplexers (6₁-6_n), a clock-pulse generator (7), decision device (8), n comparator circuits (9₁-9_n), (n+1) comparators (10), a converter (11), n arithmetic logic units (12₁-12_n).

EFFECT: high noise-immunity due to minimisation of the effect of interference on communication equipment, a component part of which is the present apparatus, and high reliability of receiving information.

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Description

The invention relates to the field of radio engineering and can find application in radio means of special radio communication for highly reliable data transmission over a radio channel under the influence of a complex of interference.

A device is known, described in [1], in which, due to the inclusion of logical elements in the majority election circuit, the device will continue to function normally and give a signal to the actuator in case of failure of any one functional element.

A device is described in [2], in which the reliability of operation is improved by reducing hardware costs.

The disadvantages of the above devices are implementation complexity and low reliability.

The closest in technical essence to the proposed is the device described in [3], taken as a prototype.

The functional diagram of the prototype device is shown in figure 1, where the following notation:

1 - majority element;

7 - clock generator (GTI);

13 - reverse counter;

14 - the first element And;

15 - the second element And;

16 - the first element AND NOT;

17 - the second element AND NOT;

18 - the first D-trigger;

19 - second D-trigger;

20 - the third D-trigger;

21 - fourth D-trigger;

22 - fifth D-trigger;

23 - input bus;

24 - output bus;

25 - the first channel;

26 - the second channel;

27 - n-th channel.

The prototype device contains the outputs of the first 16 and second 17 AND-NOT elements connected to the first inputs of the first 14 and second 15 AND elements, respectively, the outputs of which are connected respectively to the summing and subtracting inputs of the reversible counter 13. The first inputs of the first 16 and second 17 AND elements - NOT connected to the direct and inverse outputs of the (m-1) th discharge of the reversible counter 13, and the second inputs of these elements AND NOT connected respectively to the inverse and direct output of the m-th discharge of the reversible counter 13. Output of the reverse counter 13 nen to a first input of a majority of the element 1 and respective inputs of the majority element of other channels. The second 19, third 20, fourth 21 and fifth 22 D-flip-flops are connected in series, the second input of the second element And 15 is connected to the output of the first D-flip-flop 18, the input D of which is connected to the input bus 23, and the input C of the first D-flip-flop 18 is connected with direct output of the GTI 7 and input C of the fourth D-flip-flop 21, the inverse output of the GTI 7 is connected to the input C of the third 20 and fifth 22 D-flip-flops, the output of which is connected to the input R of the second D-flip-flop 19, the input D of which is connected to its high potential power bus U, input C of the second D-flip-flop 19 is connected to the output of the majority ment 1 and the output of the second D-flip-flop 19 is connected to output channel bus 24, the output of the third D-flip-flop 20 is connected to the second input 14.

The prototype device operates as follows.

The input signals X ₁ , X ₂ , X _P go to the inputs 23 (inputs D of the first D-trigger 18) of the respective channels of the device. For clarity, we assume that n = 3 and all reversible counters are in the zero state, and a high signal level corresponds to a logical unit. In this case, the zero levels from the direct outputs of the (m-1) -th and mth digits of the reverse counter 13 are supplied to the first input of the first AND-NOT 16 element and the second input of the second AND-NOT 17 element, respectively. As a result, their outputs will have a high level, which will go to the first inputs of the first 14 and second 15 elements I. An input pulse, for example X ₁ , appears at the output of the D-trigger 18 along the leading edge of the pulse from the direct output of the GTI 7 (pulse repetition period GTI T _T 7 is chosen less than the duration T _I X ₁₎ of the input pulse. The pulse from the output of the D-flip-flop 18 enters the second input of the second element And 15 and forms a high level at its output, which, entering the subtracting input of the reversible counter 13, puts it in the “minus one” state (in all bits of the unit). As a result, a high level from its direct output of the senior discharge m will go to the first input of the majority device 1 of the first channel 25 and the corresponding inputs of the remaining channels.

Next, the zero levels of signals from the inverse outputs of the (m-1) -th and mth bits of the reverse counter 13 are fed to the first input of the first AND-NOT 16 element and the second input of the second AND-NOT 17 element, as a result of which their outputs will remain high level. After the pulse X ₂ arrives at any other input of the device, for example, at the second, it will also be picked up by the reverse counter of the second channel 16. As a result, a high signal level from the direct output of its senior discharge goes to the input of the majority device 1 of its channel and the corresponding inputs majority device of other channels. If there are two high levels at the inputs of the majority element 1 of all channels, a high level will appear at its output, which goes to the input From the second D-trigger 19 of all channels. At the input D of this trigger, a high level U is constantly present, as a result of which the D-trigger 19 is set to a single state along the leading edge of the output pulse of the majority element 1.

The output signal of the second D-flip-flop 19 of all channels is fed to the output bus 24 and the input D of the third D-flip-flop 20. Next, the third D-flip-flop 20 will be sequentially set to a single state along the leading edge of the pulse from the inverse output of the GTI 7, the fourth D-flip-flop 21 on the leading edge of the pulse from the direct output of the GTI 7, the fifth D-trigger 22 on the leading edge of the pulse from the inverse output of the GTI 7. The output pulse of the third D-trigger 20 of all channels is supplied to the second input of the first element And 14 and forms a high level at its output, which by turns off on the summing input of the reversing counter 13. As a result, the state of all reversing counters will increase by one - the reversing counter 13 of the first channel 25 and the reversing counter 13 of the second channel 26 will be reset, and the reversing counter 13 of the third channel 27 will go into the state "+1" (unit in the junior category). If further, an impulse X ₃ arrives at the input of the third channel 27, then, in accordance with the above description, this pulse passes to the subtracting input of the reverse counter 13 of its channel and transfers the reverse counter 13 of the third channel 27 to the zero state.

After the fifth D-flip-flop 22 is set to a single state, its output signal sets the second D-flip-flop 19 to the zero state, after which the third 20, the fourth 21 and the fifth 22 D-flip-flops are subsequently zeroed and the circuit returns to its initial state.

Thus, the device selects an average sequence of pulses and all output signals of the device are generated synchronously.

The disadvantage of the prototype device is the impossibility of its use in communication networks using the structural protection of the transmitted information (for example, using radio lines with pseudo-random tuning of the operating frequency). In such communication networks, synchronization of the communication line is especially relevant due to periodically sent sync packets from the transmitter to the receiver with repeats. The structure of the prototype device is designed to receive a signal with a high probability of error of the first kind: despite the absence of a signal, under the influence of noise emissions, an incorrect decision is made about the presence of a signal. As a result of this, an erroneous decision made by the prototype device about the presence in the noise, for example, of sync bits, can lead to a set of undesirable consequences for the communication network as a whole.

In this regard, to improve the quality of work of the majority criterion, preliminary processing of the received information is necessary in order to minimize the majority choice errors.

Thus, the objective of the proposed device is the introduction of adaptation of the receiver to changes in the jamming environment and reduce information loss.

The technical result achieved in this case is an increase in noise immunity by minimizing the effect of noise emissions on communication equipment, of which this device is an integral part, and increasing the reliability of information reception.

To implement this technical result, according to the invention, n latch counters, n demultiplexers, n arithmetic logic devices, (n + 1) comparators, n comparison circuits, a resolving device, are introduced into a device containing a clock pulse generator (GTI) and a majority element, according to the invention, a converter, an adder and a control unit, the deciding device, the input of which is the input of the device, is connected in series with the converter and the 1st - nth counter-latch, and the first outputs of the 1st - nth counter-latches are connected to serially connected by an adder, a first comparator and a control unit, the l-th-n-th outputs of which are connected respectively to the second inputs of the 1st-nth demultiplexers; the second outputs of the 1st - nth counter-latches are connected respectively to the first inputs of the 1st - nth demultiplexers, the first outputs of which are connected to a majority element, the output of which is the output of the device; the second outputs of the 1st - nth demultiplexers are connected respectively with the 1st - nth comparison circuits, the outputs of which are connected respectively with the 1st - nth arithmetic logic devices, the outputs of which are connected respectively with the 2nd - ( n + 1) -th comparators, the outputs of which are connected respectively to the 2nd - (n + 1) -th inputs of the control unit; sync inputs of the 1st - nth counter-latches, 1st - nth demultiplexers, 1st - nth arithmetic logic devices, 1st - (n + 1) -th comparators, 1st - The nth comparison circuit, the majority element, the solver, the converter, the adder and the control unit are connected to the GTI output.

Functional diagram of the proposed device for majority selection of signals is shown in figure 2, where the following notation:

1 - majority element;

2 ₁ -2 _n - 1st - n-th counter-latches (СЗ1-СЗn);

3 - adder;

4 ₁ -4 _n - 1st - n-th comparators;

5 - control unit (CU);

6 ₁ -6 _n - 1st - n-th demultiplexers (Dm1-Dmn);

7 - clock generator (GTI);

8 - a decisive device (RU);

9 ₁ -9 _n - 1st - n-th comparison schemes (CC1-CCn);

10 - (n + 1) -th comparator;

11 - converter;

12 ₁ -12 _n - 1st - n-th arithmetic-logic devices (ALU1-ALUn).

The inventive device contains a serially connected solver 8, the input of which is the input of the device, the converter 11 and the 1st — n-th counter-latches 2 ₁ -2 _n , and the first outputs of the 1st — n-th counter-latches 2 ₁ - 2 _{n are} connected to series-connected adder 3, the (n + 1) th comparator 10 and the control unit 5, the 1st - n-th outputs of which are connected respectively to the second inputs of the 1st - n-th demultiplexers 6 ₁ -6 _n .

The second outputs of the 1st - nth counter-latches 2 ₁ -2 _{n are} connected respectively to the first inputs of the 1st - nth demultiplexers 6 ₁ -6 _n , the first outputs of which are connected to the majority element 1, the output of which is the output of the device .

The second outputs of the 1st - nth demultiplexers 6 ₁ -6 _{n are} connected respectively to the 1st - n-th comparison circuits 9 ₁ -9 _n , the outputs of which are connected respectively to the 1st-n-th arithmetic-logic devices 12 ₁ -12 _n , the outputs of which are connected respectively with the 1st - nth comparators 4 ₁ -4 _{n the} outputs of which are connected respectively with the 2nd - (n + 1) -th inputs of the control unit 5.

Sync inputs of the 1st - nth counter-latches 2 ₁ -2 _n , 1st - nth demultiplexers 6 ₁ -6 _n , 1st - nth arithmetic logic devices 12 ₁ -12 _n , 1- th - (n + 1) th comparators 10, 4 ₁ -4 _n , 1st - n-th comparison circuits 9 ₁ -9 _n , majority element 1, solving device 8, converter 11, adder 3 and control unit 5 connected to the GTI outlet.

The device operates as follows.

Continuous radio-frequency oscillation, transferred to the video frequency region, enters RU 8. In RU 8, based on the sampling of the signal by time and amplitude, a decision is made on the length of the vector being studied. To increase the accuracy of subsequent measurements, the sampling results in block 11 are transferred from the form of a fixed-point number to the form of a floating-point number.

The variable-length vectors obtained in blocks 8 and 11 are loaded sequentially into blocks 2 ₁ -2 _n according to the following principle (where β is the serial number of the vector received in block 11):

For β <n:

- on receiving the β-th vector post only in blocks 2 _γ, where γ∈ [1, β], and for a given interval 2 _γ -th block is written (| γ-β-1 |) -th vector.

When β≥n:

- upon receipt of the β-th vector, the (β-n + 1) th vector is written to the 2 _n- th block.

After writing to each of the blocks 2 ₁ -2 _n, their length value goes to the adder 3, from where the calculated value of the sum goes to block 10, where there is a comparison with the first control value (KZ1). KZ1 corresponds to a number equal to the sum of the lengths of the vectors contained in blocks 2 ₁ -2 _n , provided that their lengths are equal.

The comparison results in block 10 are sent to control unit 5. On condition that the control value is reached in control unit 10, control unit 5 generates control signals for the address inputs of demultiplexers 6 ₁ -6 _n , according to which the input signal from the corresponding block 6 _j (where j∈ [1, n]) of block 2 _j enters block 9 _j, respectively.

Comparison schemes are blocks of storage of a reference signal. And at the outputs of blocks 9 ₁ -9 _n , the result of comparison with the reference signal obtained in blocks 8 and 11 of the vectors is formed. These results from blocks 9 ₁ -9 _n are received respectively in ALU 12 ₁ -12 _n , where on the basis of some criteria (determined from the conditions of the optimal ratio of the probabilities of false alarms and the correct reception), the final deviation of the vector from the reference distribution is determined.

The obtained deviation values from the ALU 12 ₁ -12 _n go respectively to blocks 4 ₁ -4 _n , where they are compared with the existing second control value (KZ2).

The comparison results in blocks 4 ₁ -4 _n go to control unit 5. On their basis (for those of blocks 4 ₁ -4 _n , where short circuit 2 has been exceeded), control unit 5 generates control signals for the address inputs of the corresponding demultiplexers 6 ₁ -6 _n , according to by which the input signal from the corresponding blocks 2 ₁ -2 _n enters block 1, where, on the basis of the majority criteria, the bits are finally determined in the received vectors.

From the output of the GTI 7, clock pulses are sent to all blocks of this device, which determine the beginning of each microoperation, as a result of which the operation of the device as a whole is synchronized.

RU can be implemented based on the schemes described in [4]. Latch registers can be implemented physically based on the elements described in [5]. SS 9 ₁ -9 _n can be implemented as discrete matched filters. Block 1 can be made in the form of logical elements [6].

The device as a whole can be implemented as a reprogrammable digital device, for example XC3S400-4PQ208I [7].

Thus, the introduction of new blocks and communications in the proposed device allows to increase the reliability of information reception due to adaptation to changes in the interference environment, which allows it to be used in special communications under the influence of an interference complex.

Information sources

1. RF patent for the invention No. 2298823 "Majority backup device (options)". // Rabinovich M.D., Nikiforov B.D., Abramov V.M., 2005.

2. RF patent for the invention No. 2110835 "Device for majority selection of signals." // Ledenev G.Ya., Lavrishchev A.B., 1998.

3. RF patent for the invention No. 2396591 "Device for majority selection of signals." // Ledenev G.Ya., Sukhov B.M., Efimov S.N., 2008.

4. Noise-like signals in information transmission systems. // Ed. prof. Pestryakova V.B. - M .: Owls. radio, 1973.

5. The art of circuitry. Horowitz P., Hill W. - M .: Mir, 1998, p. 8.24.

6. Microcircuitry: Textbook for universities. Ed. 2nd, rev. and add. // Alekseenko A.G., Shakulin I.I. - M .: Radio and communications, 1990.

7.http: //www.plis.ru/index.php

Claims (1)

A device for majority selection of signals, containing a clock generator (GTI) and a majority element, characterized in that n latch counters, n demultiplexers, n arithmetic logic devices, (n + 1) comparators, n comparison circuits, a resolver are introduced, a converter, an adder and a control unit, wherein a deciding device, the input of which is the input of the device, is connected in series with the converter and the 1st - nth counter-latches, and the first outputs of the 1st - nth counter-latches are connected to the no connected adder, the first comparator and control unit, the 1st - n-th outputs of which are connected respectively to the second inputs of the 1st - n-th demultiplexers; the second outputs of the 1st - nth counter-latches are connected respectively to the first inputs of the 1st - nth demultiplexers, the first outputs of which are connected to a majority element, the output of which is the output of the device; the second outputs of the 1st - nth demultiplexers are connected respectively with the 1st - nth comparison circuits, the outputs of which are connected respectively with the 1st - nth arithmetic logic devices, the outputs of which are connected respectively with the 2nd - ( n + 1) -th comparators, the outputs of which are connected respectively with the 2nd - (n + 1) -th inputs of the control units; sync inputs of the 1st - nth counter-latches, 1st - nth demultiplexers, 1st - nth arithmetic logic devices, 1st - (n + 1) -th comparators, 1st - The nth comparison circuit, the majority element, the solver, the converter, the adder and the control unit are connected to the GTI output.

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