RU2279762C2 - Satellite communication system - Google Patents

Abstract

FIELD: radio engineering, possible use in duplex communication systems with multiple access and frequency division, processing and commutation of signals of correspondents onboard the satellite communication relay.

SUBSTANCE: satellite communication system consists of N>2 ground-based satellite communication stations and a satellite relay station. Each ground station of satellite communication contains antenna-feeder route, power amplifier, duplexer, input block, excitation device, frequency division block, receiver, block for dividing and combining, modulus two adder, delay line, block for controlling aforementioned excitation device, block for forming information-testing signals and satellite relay station with capacity for onboard processing of signals.

EFFECT: increased protection of signals with low level from interference due to prevention of their suppression by useful signals with high level at input of satellite relay.

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Description

The invention relates to the field of radio engineering and can be used in duplex communication systems with multiple access with frequency division, processing and switching of signals of correspondents on board a satellite relay.

A known satellite communication system (see Juan R. and Houten F. Repeater satellite communications system with signal processing on board, TIIER, N2, 1971, p.139-155), which consists of a satellite relay with signal processing on board, containing the receiving an antenna, a preamplifier, a decryption and separation unit, a code generator, N narrow-band filters, N demodulators, an adder, a power amplifier, a transmitting antenna, and N earth terminal stations.

The disadvantage of this satellite communication system is the low noise immunity from information signals with an increased signal level due to the inability to equalize signal levels having allowed code combinations.

Also known is a satellite communication system (see Ignatov V.V., Chistyakov A.P. Justification of the main technical parameters of a promising multi-channel radio communication technique. - L .: VAS, 1988, p.29-35), which consists of a satellite relay with processing signals on board, containing the receiving and transmitting antenna systems, a low-noise power amplifier, a mixer, N individual paths, each of which consists of an intermediate-frequency amplifier, a band-pass filter, a demodulator. Common to the N paths are temporary combining equipment, a modulator and a power amplifier. Each satellite communications earth station contains an antenna-feeder path, a duplexer, an input device, a frequency separation device, a receiver, separation and integration equipment, a pathogen, and a power amplifier.

The disadvantage of this satellite communication system is the relatively low noise immunity, because there is no possibility of automatically adjusting the power of satellite earth stations for transmission to ensure the same level of information signal at the input of a low-noise power amplifier of a satellite repeater.

Closest to the technical nature of the claimed satellite communications system is a satellite communications system according to the patent of the Russian Federation No. 2090003, publ. 09/10/97, Bull. N25.

Satellite communication system - the prototype consists of N satellite earth stations, each of which contains an antenna-feeder path, a power amplifier, a duplexer, an input device, a driver, a frequency separation device, a receiver, separation and integration equipment, a delay line, an adder modulo two and a satellite repeater with signal processing on board, which contains a receiving antenna system, low noise power amplifier, mixer, N intermediate frequency amplifiers, N bandpass filters, N demodulators, com utator, K adders modulo two, the apparatus temporarily combining, a modulator, a power amplifier, a transmit antenna system, a local oscillator.

Moreover, in each satellite earth station, an antenna-feeder path is connected in series, the output of which is connected to the first input of the duplexer, the output of which is connected to the input of the input device, the output of which is connected to the input of the frequency separation device, the output of which is connected to the input of the receiver, the output of which is connected to the first input of the separation and combining equipment, the second output of which is connected to the second input of the adder modulo two, the first output of the separation and combining equipment is simultaneously connected is connected to the input of the delay line and to the input of the exciter, the output of which is connected to the input of the power amplifier, the output of which is connected to the second input of the duplexer, the delay output is connected to the first input of the adder modulo two, to the output of which the subscribers of the earth station of satellite communications are connected, the subscriber input of the earth the satellite communications station is connected to the second input of the separation and combining equipment, in the satellite repeater a receiving antenna system, a low-noise amplifier, a mixer, the output of which simultaneously connected to the inputs of N intermediate frequency amplifiers, the output of each of which is connected to the inputs of the corresponding bandpass filters, the output of each of which is connected to the inputs of the corresponding demodulators, the outputs of which are connected to the corresponding inputs of the switch, the outputs of which are connected to the corresponding first and second inputs of the adders modulo two, the outputs of which are connected to the corresponding inputs of the temporary association equipment, the output of which is connected to the first input of the modulator, the output of which is for prison to the input of the power amplifier, the output of which is connected to the transmitting antenna system to the second inputs of the mixer and the modulator local oscillator connected to respective outputs.

The advantages of the considered satellite communication system in comparison with analogs are the provision of higher efficiency in establishing connections between satellite earth stations and the reduction of the speed and frequency band of the radio link satellite relay - earth satellite communication station while maintaining bandwidth.

The disadvantage of the prototype is the relatively low noise immunity due to the effect of suppressing information signals with a low level of information signals with a high level at the input of a satellite repeater, which is caused by the lack of objective quality control of the information communication channel due to the transmission of test information through official communication channels.

The aim of the invention is to develop a satellite communications system that provides higher noise immunity of signals with a low level by eliminating their suppression by high-level information signals at the input of a satellite repeater.

To achieve the stated goal in a known satellite communication system, including N≥2 satellite earth stations and a satellite repeater that contains a receiving antenna, the output of which is connected to the input of a low-noise power amplifier, the output of which is connected to the signal input of the mixer, N selective paths, each of which consists of a series-connected intermediate-frequency amplifier, a band-pass filter, a demodulator, and the input of the intermediate-frequency amplifier and the output of the demodulator are respectively The input and output of the electoral path, the inputs of the electoral paths are combined and connected to the signal output of the mixer, the heterodyne input of which is connected to the output of the local oscillator, the output of the i-th selective path, where i = 1,2, ... N, is connected to the i-th switch input, N / 2 adders modulo two, j-th output, where j = 1,2, ... N / 2, modulo two adders connected to j-th input of temporary combining unit, the output of which is connected to the signal input modulator, and the local oscillator input to the local oscillator output, the modulator output is connected to the input of the amplifier the output of which is connected to the input of the transmitting antenna, and each satellite earth station includes a duplexer, the transceiver input-output of which is connected to the antenna-feeder path, the signal input of the duplexer is connected to the output of the power amplifier, the input of which is connected to the output of the exciter, the signal output of the duplexer connected to the input of the input unit, the output of which is connected to the input of the frequency separation unit, the output of which is connected to the input of the receiver, the output of which is connected to the signal input of the separation unit and combining, a delay line, the output of which is connected to the information input of the adder modulo two, the signal input of which is connected to the signal output of the separation and combining unit, and the information output of which is connected to the input of the delay line, and the information input of the separation and combining unit and the output of the adder module two, respectively, are the information input and output of the satellite earth station, N / 2 test signal switches, i-th and i + 1-th outputs are additionally introduced to the satellite repeater The switch s are connected respectively to the information and signal inputs of the [j = (i + 1) / 2] -th test signal switch, and the information and signal outputs of the j-test switch signal are connected to the information and signal inputs of the j-th adder modulo two. An exciter control unit and an information-test signal generation unit are additionally introduced at each satellite communications earth station, the control and information outputs of which are connected respectively to the control input of the exciter control unit and to the information input of the exciter. The information and signal inputs of the information-test signal generation unit are connected to the inputs of the delay line and adder, respectively, modulo two. The output of the pathogen control unit is connected to the control input of the pathogen.

The test signal switch consists of a timer trigger signal generator, a timer, an even-cycle counter, an odd-cycle counter, a single-vibrator, the first and second logical elements AND, and the first and second logical elements OR. The output of the timer trigger signal generator is connected to the timer input, the first, second, and third outputs of which are connected to the inputs of the even-cycle counter, one-shot, and odd-cycle counter, respectively. The outputs of the even-cycle counter and the odd-cycle counter are connected to the first inputs of the logical elements AND, respectively, and the output of the single-vibrator is connected to the second inputs of the logical elements I. The outputs of the logical elements AND are connected to the second inputs, respectively, of the logical elements OR, and the first outputs of the logical elements OR are connected respectively to the first and second inputs of the driver of the start timer signal and are the first and second inputs of the test signal switch. The outputs of the OR gates are respectively the first and second outputs of the test signal switch.

The information-test signals generation unit consists of the first logical element NOT, the output of which is connected to the second input of the first logical element AND, the first input of which is connected to the timer input and is the first input of the information-test signals generation unit. The output of the first AND gate is connected to the first input of the OR gate, the second input of which is connected to the output of the third logic gate I. The output of the OR gate is the second output of the information-test signal generation block. The input of the first logical element is NOT connected to the first input of the third logical element And, the input of the shaper of the test sequence, the output of the one-shot, the second input of the fifth logical element And and the input of the first delay line. The second input of the third logical element AND is connected to the output of the test sequence generator and the input of the second logical element NOT, the output of which is connected to the first input of the fifth logical element And, the output of which is connected to the input of the second delay line, the output of which is connected to the second input of the adder modulo two, the first input of which is the second input of the information-test signal generation block. The timer output is connected to the input of a single vibrator. The output of the first delay line is connected to the first input of the fourth logical element And, the second input of which is connected to the output of the adder modulo two, and the output of the fourth logical element And is the first output of the unit for generating information-test signals.

The pathogen control unit consists of a permission element, the information input of which is connected to the output of the second one-shot, and synchronizing to the clock input of the input element, whose signal input is connected to the output of the first one-shot, the control input of the error analyzer and the control input of the synchronization element. The information input of the synchronization element is connected to the output of the clock generator and the synchronizing input of the input element. The output of the permission element is connected to the input of the first one-shot. The output of the input element is connected to the information input of the error analyzer, the signal input of which is connected to the output of the second one-shot. The output of the error analyzer is connected to the information input of the memory element, the synchronizing and signal inputs of which are connected respectively to the synchronizing and signal outputs of the synchronization element. The control input of the memory element is connected to the output of the initial state setting element and the control input of the switch and the control input of the code generator. The output of the memory element is connected to the information input of the state assessment element, the control input of which is connected to the output of the quality assessment threshold generator. The output of the state assessment element is connected to the information input of the switch, the signal input of which is connected to the signal input of the memory element and the input of the second one-shot. The signal output of the initial state setting element is connected to the signal input of the code generator, the synchronizing and shifting inputs of which are connected respectively to the synchronizing and shifting outputs of the switch. The installation input of the code generator is connected to the output of the initial generator, and the information input of the input element and the information output of the code generator are respectively the input and output of the pathogen control unit.

Thanks to a new set of essential features due to the introduction of a test signal to the satellite relay of the switch and providing alternate switching of information and test signals on it, and to each satellite earth station, the pathogen control unit and the information-test signal generation unit, which make it possible to generate a test signal and its transmission to a satellite repeater, reception, processing and generation of a control signal for the causative agents of satellite earth stations oic connection provides automatic determination of the channel quality satellite communication meaningfully test signal error rate, in accordance with control signals which are generated and produced exciter signal level control than immunity achieved satellite links.

The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features that are identical to all the features of the claimed technical solution are absent, which indicates the compliance of the claimed device with the patentability condition "novelty". Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the fame provided for by the essential features of the claimed invention, the transformations to achieve the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed device is illustrated by drawings:

Figure 1 - Satellite communication system.

Figure 2 - Functional diagram of a satellite communications system.

Figure 3 - Functional diagram of the switch test signal.

Figure 4 - Functional diagram of the shaper of the start timer signal.

Figure 5 - Functional block diagram of the formation of information-test signals.

6 is a Functional diagram of a control unit of the pathogen.

7 is a Functional diagram of a permission element.

Fig. 8 is a functional diagram of an input element.

Figure 9 - Functional diagram of the error analyzer.

Figure 10 - Functional diagram of the synchronization unit.

11 - Functional diagram of a memory element.

Fig - Functional diagram of the element of the state assessment.

Fig - Functional diagram of the driver of the thresholds for assessing quality.

Fig. 14 is a functional diagram of an initial state setting element.

Fig - Functional diagram of the switch.

Fig. 16 is a functional diagram of a code generator.

Fig - Functional diagram of the shaper of the initial code.

Fig. 18 - Plots of voltages, the functioning of the elements of the switch test signal.

Fig - Plots of stresses, the functioning of the elements of the unit for the formation of information-test signals.

The satellite communications system shown in FIG. 1 consists of N> 2 earth stations of satellite communications 1 ... N and a satellite repeater. Each satellite earth station 1 shown in Fig. 2 contains an antenna feeder path 1.2, a power amplifier 1.3, a duplexer 1.1, an input unit 1.5, a driver 1.4, a frequency separation unit 1.6, a receiver 1.7, a separation and combining unit 1.8, an adder modulo two 1.9, delay line 1.10, driver control unit 1.12, information-test signal generation unit 1.11 and satellite relay 2 with signal processing on board, which contains a receiving antenna 2.1, a low-noise power amplifier 2.2, a mixer 2.3, N selective paths 2.4 ₁ ... 2.4 _N , N intermediate frequency amplifiers 2.4.1 ₁ ... 2.4.1 _N , N bandpass filters 2.4.2 ₁ ... 2.4.2 _N , N demodulators 2.4.3 ₁ ... 2.4.3 _N , local oscillator 2.5, switch 2.6, N / 2 test signal switches 2.7 ₁ ... 2.7 _{N / 2} and adders modulo two 2.8 ₁ ... 2.8 _{N / 2} , temporary combining equipment 2.9, modulator 2.10, power amplifier 2.11 transmitting antenna 2.12.

Moreover, in each earth station satellite communications 1 ... N (see figure 2), the transceiver input-output of duplexer 1.1 is connected to the antenna-feeder path 1.2. The signal input of duplexer 1.1 is connected to the output of the power amplifier 1.3, the input of which is connected to the output of the exciter 1.4. The signal output of the duplexer is connected to the input of the input unit 1.5, the output of which is connected to the input of the frequency separation unit 1.6, the output of which is connected to the input of the receiver 1.7, the output of which is connected to the signal input of the separation and combining unit 1.8. The output of the delay line 1.10 is connected to the information input of the adder modulo two 1.9, the signal input of which is connected to the signal output of the separation and combining unit 1.8, and its information output is connected to the input of the delay line 1.10, the information input of the separation and combining unit 1.8 and the output of the adder two 1.9 are respectively the input and output of the satellite earth station 1. In satellite repeater 2, the output of the receiving antenna 2.1 is connected to the input of the low-noise power amplifier 2.2, the output of which is connected chan to the signal input of the mixer 2.3. Each of the N selective paths 2.4 consists of a series-connected intermediate frequency amplifier 2.4.1, a band-pass filter 2.4.2, a demodulator 2.4.3, and the input of the intermediate frequency amplifier 2.4.1 and the output of the demodulator 2.4.3 are respectively the input and output of the selective path 2.4 . The inputs of the electoral paths 2.4 are combined and connected to the signal output of the mixer 2.3, the heterodyne input of which is connected to the output of the local oscillator 2.5. The output of the i-th election path 2.4 _i , where i = 1, 2, ..., N, is connected to the i-th input of the switch 2.6, the i-th and (i + 1) -th outputs of which, where i is odd, connected respectively to the information and signal inputs of the [j = (i + 1) / 2] -th switch of the test signal 2.7 _j . The output of the jth N / 2 adder modulo two 2.8, where j = 1, 2, ..., N / 2, is connected to the jth input of the temporary combining equipment 2.9, the output of which is connected to the signal input of the modulator 2.10, and the local oscillator input - to the output of the local oscillator. The output of modulator 2.10 is connected to the input of the power amplifier 2.11, the output of which is connected to the input of the transmitting antenna system 2.12.

The constituent parts of the claimed device are typical and implemented in existing satellite communications systems, and their description is contained in the following sources of information. Duplexer 1.1 earth station satellite communications 1 figure 2 is intended for decoupling the frequency of the transmission and reception paths, since the antenna-feeder path is common to them. As a duplexer, a transmission and reception separation filter can be used, the schemes of such filters are known and described, for example, in the book: G. B. Askinazi, V. L. Bykov, G. V. Vodopyanov and others. Satellite communications and broadcasting handbook . Ed. L.Ya. Kantora. - M.: Radio and Communications, 1983, p.13. fig. 1.4. Antenna-feeder path 1.2 of figure 2 is designed to receive signals emitted by the satellite relay 2 of figure 2. Schemes of such antenna-feeder paths are known and described in the same book on p.176-196. The power amplifier 1.3 of figure 2 is designed to amplify the required power level of the microwave radio signal coming from the pathogen 1.4. The power amplifier circuit is known and described, for example, in the book: V. A. Bukovsky, V. V. Ignatov, A. P. Rodimov and others. Military space communications systems. Ed. A.P. Rodimova. - L .: YOU, 1984, p. 181-183, Fig. 8.5. The causative agent 1.4 of figure 2 is intended for the formation of high-frequency oscillations in the range of the station and modulation by a group signal. The pathogen scheme is known and described in the same book on pp. 175-181, Fig. 8.1. The input unit 1.5 of figure 2 is designed to maximize its sensitivity. Input block circuits are known and described, for example, in the book: Satellite Communications and Broadcasting Handbook. Ed. L.Ya. Kantora. - M .: Radio and communications, 1983, p.146-154. The frequency separation unit 1.6 and the receiver 1.7 of FIG. 2 are intended to isolate from the wide band of the barrel any narrow band in which the correspondent signal is located, and its amplification, filtering and demodulation. Schemes of frequency separation blocks and receivers are known and similar to those described, for example, in the book: Handbook of radio relay communication. Under. ed. S.V. Borodich. - M .: Radio and communications, 1981, p.115-152. The separation and combining unit 1.8 of FIG. 2 is intended for combining individual subscriber signals into a single group pulse sequence during transmission and separation of group signals into subscriber signals at reception. The schemes of such separation and association units are known and described, for example, in the book: V.A. Bukovsky, V.V. Ignatov, A.P. Rodimov and other Military space communications systems. Ed. A.P. Rodimova. - L .: YOU, 1984, pp. 192-207, Fig. 9.7., 9.8. The adder modulo two 1.9 of FIG. 2 is designed to subtract from the received signal its signal delayed in the delay line by the signal propagation time in the sections of the line of the satellite earth station — satellite relay — satellite earth station, and extracting only the correspondent signal at its output. As an adder modulo two, an adder described in the book can be used: V.A.Bushuev, V.N. Veniaminov, V.G. Kovalev, etc. Microcircuits and their application. - M .: Energy, 1978, p.178-180. The delay line 1.10 of FIG. 2 is designed to delay the input signal for a time comparable to the propagation time of the signal on the line of the satellite communications earth station — satellite relay — satellite communications earth station. The delay line can be implemented by applying the binary-discrete delay line described in the book: Antennas. Sat articles. Vol. 26. / Ed. A.A. Pistolkors. - M .: Communication, 1978, p.120-170.

The information-test signal generation block 1.11 shown in FIG. 5 is intended to generate test signals on the satellite earth station 1 of FIG. 2, to include the data of the test signals in the sequence of information signals in regulated time intervals and consists of the first logical element NOT 1.11. 1, the first logical element AND 1.11.2, the logical element OR 1.11.3, the third logical element AND 1.11.4, the fourth logical element AND 1.11.5, the adder modulo two 1.11.6, the first delay line 1.11.7, the second 1st delay line 1.11.8, the second logical element NOT 1.11.9, the fifth logical element AND 1.11.10, the shaper of the test sequence 1.11.11, the one-shot 1.11.12, the timer 1.11.13.

The output of the first logical element NOT 1.11.1 is connected to the second input of the first logical element AND 1.11.2, the first input of which is connected to the input of the timer 1.11.13 and is the first input of the information-test signal generation block 1.11. The output of the first logical element AND 1.11.2 is connected to the first input of the logical element OR 1.11.3, the second input of which is connected to the output of the third logical element AND 1.11.4. The output of the OR gate 1.11.3 is the second output of the information-test signal generation block 1.11. The input of the first logical element NOT 1.11.1 is connected to the first input of the third logical element And 1.11.4, the input of the shaper of the test sequence 1.11.11, the output of the one-shot 1.11.12, the second input of the fifth logical element And 1.11.10 and the input of the first delay line 1.11. 7. The second input of the third logical element AND 1.11.4 is connected to the output of the shaper of the test sequence 1.11.11 and the input of the second logical element NOT 1.11.9, the output of which is connected to the first input of the fifth logical element AND 1.11.10, the output of which is connected to the input of the second delay line 1,11.8, the output of which is connected to the second input of the adder modulo two 1.11.6, the first input of which is the second input of the information-test signal generation block 1.11. The output of the timer 1.11.13 is connected to the input of the one-shot 1.11.12. The output of the first delay line 1.11.7 is connected to the first input of the fourth logical element And 1.11.5, the second input of which is connected to the output of the adder modulo two 1.11.6, and the output of the fourth logical element And 1.11.5 is the first output of the information-test formation block signals 1.11.

Included in the general structure of the information-test signal generation block 1.11 shown in FIG. 5, the elements are typical and can be technically implemented at the present time using a modern element base. The adder modulo two 1.11.6 of figure 5 is intended to highlight the error signal relative to the transmitted test signal and received from the satellite relay 2. figure 2. As an adder modulo two, an adder described in the book can be used: V.A.Bushuev, V.N. Veniaminov, V.G. Kovalev, etc. Microcircuits and their application. - M .: Energy, 1978, p.178-180. The first delay line 1.11.7 of FIG. 5 is intended to permit the allocation of an error signal generated in the adder modulo two 1.11.6 of FIG. 4. The second delay line 1.11.8 of FIG. 5 is designed to synchronize the processing of information and test signals transmitted by the satellite earth station 1 and received from the satellite relay 2 of FIG. 2. Shaper test sequence 1.11.11 figure 5 is intended to form a test sequence. The pulse generator described in the book: IP Shelestov can be used as a test sequence generator. Hams: useful circuits. Book 2. - M .: Solon, 1998, p.27, fig. 1.30.a. The one-shot 1.11.12 figure 5 is intended for the formation of a single pulse of duration corresponding to the test signal in the structure of the information-test signal. Standing multivibrators that can be used, for example, in the book: V.A. Batushev, V.N. Veniaminov, V.G. Kovaleva, etc. Microcircuits and their application can be used as a single-vibrator on November 1, 12. - M .: Energy, 1978, p.193 or V.L. Shilo. Linear integrated circuits in electronic equipment. - M .: Soviet Radio, 1979, p. 210-214. The timer 1.11.13 of FIG. 5 is intended to generate start pulses of the single-shot 1.1.12 of FIG. 5 with respect to the signal frame structure at time instants corresponding to passing the test sequence of even or odd cycles. Schemes of such timers are known and are given, for example, in the book: A.A. Bokunyaev, N.M. Borisov, E.B. Gumelya and others. A reference book of a radio amateur designer. Book 1. / Ed. N.I. Chistyakova. - M.: Radio and Communications, 1993, p. 314, Fig. 8.123. The first and second delay lines can be implemented by applying a binary-discrete delay line described in the book: Antennas. Sat articles. Vol. 26. / Ed. A.A. Pistolkors. - M .: Communication, 1978, p.120-170. Schemes of logical elements NOT, AND, OR are known and described, for example, in the book: A. A. Bokunyaev, N. M. Borisov, E. B. Gumelya and others. A reference book of a radio amateur constructor. Book 1. / Ed. N.I. Chistyakova. - M .: Radio and communications, 1993, p. 304, fig. 8.92. V., fig. 8.92.6. and fig.8.92.a. respectively.

The pathogen control unit 1.12, shown in Fig.6, is designed to adjust the gain of the output signal of the pathogen 1.4 of Fig.2 depending on the quality of the information channel and consists of a resolution element 1.12.1, a clock 1.12.2, a first one-shot 1.12.3, input element 1.12.4, error analyzer 1.12.5, synchronization element 1.12.6, second one-shot 1.12.7, memory element 1.12.8, element for assessing the state 1.12.9, threshold driver for assessing the quality 1.12.10, element for setting the initial state 1.12 .11, switch 1.12.12, ormirovatelya code 1.12.13, 1.12.14 driver entry code.

The control input of the permission element 1.12.1 is connected to the output of the second one-shot 1.12.7, and the clock input is connected to the clock input of the input 1.12.4, the signal input of which is connected to the output of the first one-shot 1.12.3, the control input of the error analyzer 1.12.5 and the control the input of the synchronization element 1.12.6. The clock input of the synchronization element 1.12.6 is connected to the output of the clock generator 1.12.2 and the clock input of the input element 1.12.4. The output of the resolution element 1.12.1 is connected to the input of the first one-shot 1.12.3. The output of the input element 1.12.4 is connected to the information input of the error analyzer 1.12.5, the zeroing input of which is connected to the output of the second one-shot 1.12.7. The output of the error analyzer 1.12.5 is connected to the information input of the memory element 1.12.8, the clock and enable inputs of which are connected respectively to the clock and enable outputs of the synchronization element 1.12.6. The control input of the memory element 1.12.8 is connected to the control output of the initial state setting element 1.12.11, the control input of the switch 1.12.12 and the control input of the code generator 1.12.13. The output of the memory element 1.12.8 is connected to the information input of the state assessment element 1.12.9, the installation input of which is connected to the output of the threshold generator of the quality assessment 1.12.10. The output of the state assessment element 1.12.9 is connected to the information input of the switch 1.12.12, the enable input of which is connected to the enable input of the memory element 1.12.8 and the input of the second one-shot 1.12.7. The enable output of the initial state setting element 1.12.11 is connected to the enable input of the code generator 1.12.13, the information and switching inputs of which are connected respectively to the information and switching outputs of the switch 1.12.12. The installation input of the code shaper 1.12.13 is connected to the output of the initial code shaper 1.12.14, and the information input of the input element 1.12.4 and the output of the code shaper 1.12.13 are the input and output of the pathogen control unit 1.12, respectively.

двоичного счетчика соответствуют информационному и обнуляющему входам анализатора ошибок 1.12.5. Q-выходы двоичного счетчика соответствуют выходу анализатора ошибок 1.12.5, который представляет собой четырехразрядную шину. Блок синхронизации 1.12.6, изображенный на фиг.10, предназначен для записи и считывания информации в блок памяти 1.12.8, а также для управления коммутатором 1.12.12. Блок синхронизации может быть реализован на логических элементах И, И-НЕ, описанных, например, в справочнике: Цифровые интегральные микросхемы. - М.: Радио и связь, 1994, с.234-237. Первый вход логического элемента И 1.12.6.1, соединенный с входом логического элемента И-НЕ 1.12.6.2, является управляющим входом элемента синхронизации 1.12.6. Второй вход логического элемента И 1.12.6.1 является тактовым входом элемента синхронизации 1.12.6. Выходы логических элементов И 1.12.6.1 и И-НЕ 1.12.6.2 являются соответственно первым и вторым выходами элемента синхронизации 1.12.6. Второй одновибратор 1.12.7 предназначен для формирования сигналов длительностью, соответствующей времени регулирования мощности передачи. В качестве первого и второго одновибраторов могут быть использованы ждущие мультивибраторы, описанные, например, в книге: В.А.Батушев, В.Н.Вениаминов, В.Г.Ковалева и др. Микросхемы и их применение. - М.: Энергия, 1978, с.193 или В.Л.Шило. Линейные интегральные схемы в радиоэлектронной аппаратуре. - М.: Советское радио, 1979, с.210-214. Элемент памяти 1.12.8 предназначен для хранения результатов вычисления анализатора ошибок 1.12.5 на время регулирования уровня выходного сигнала возбудителя 1.4 фиг.2 на каждом интервале измерения t_измер. В частности, он может быть реализован на регистре сдвига 1.12.8.1 и четырех логических элементах И 1.12.8.2-1.12.8.5 (фиг.11). Схемы таких регистров известны и описаны, например, в справочнике: Цифровые интегральные микросхемы. - М.: Радио и связь, 1994, с.62, рис.2.49.а. Схемы логических элементов И 1.12.8.2-1.12.8.5 также известны и описаны, например, в справочнике: Цифровые интегральные микросхемы. - М.: Радио и связь. 1994, с.234-237. Вторые входы логических элементов И 1.12.8.2-1.12.8.5 соединены и являются разрешающим входом элемента памяти 1.12.8. Вход синхронизации С и информационные входы D₁-D₄ регистра сдвига 1.12.8.1 являются соответственно тактовым и информационным входами элемента памяти 1.12.8. Установочный вход регистра сдвига 1.12.8.1 является управляющим входом элемента памяти 1.12.8. Выходы Q₁-Q₄ регистра сдвига 1.12.8.1 соответственно соединены с первыми входами логических элементов И 1.12.8.2-1.12.8.5, выходы которых являются выходом элемента памяти 1.12.8. Информационный вход и выход элемента памяти 1.12.8 представляют собой четырехразрядную шину. Элемент оценки состояния 1.12.9, изображенный на фиг.12, предназначен для сравнения k_тек с k_min и k_max. В частности, он может быть реализован на компараторах, выполненных на интегральных микросхемах, описанных, например, в книге: Б. В. Тарабрин, Л.Ф.Лунин, Ю.Н.Смирнов и др. Интегральные микросхемы: Справочник. - 2-е изд., исп, - М,: Энергоатомиздат, 1985, с.285. Входы А₀-А₃ компаратора 1.12.9.1, соединенные соответственно с одноименными входами компаратора 1.12.9.2, являются информационным входом элемента оценки состояния 1.12.9. Входы В₀-В₃ компараторов 1.12.9.1 и 1.12.9.2 являются установочным входом элемента оценки состояния 1.12.9. Третий и первый выходы компараторов 1.12.9.1 и 1.12.9.2 являются выходом блока оценки состояния 1.12.9, представляющего собой двухразрядную шину. Формирователь порогов оценки качества 1.12.10 предназначен для установки значений k_min и k_max. В частности, в качестве формирователя порогов оценки качества 1.12.10 (фиг.13) могут быть использованы резистивные матрицы на интегральных микросхемах, описанные, например, в книге: Б.В.Тарабрин, Л.Ф.Лунин, Ю.Н.Смирнов и др. Интегральные микросхемы. Справочник. - 2-е изд., исп. - М.: Энергоатомиздат, 1985, с.190. Выходы резистивных матриц составляют выход формирователя порога, представляющий собой восьмиразрядную шину. Элемент установки начального состояния 1.12.11, изображенный на фиг.14, предназначен для приведения в исходное состояние анализатора ошибок 1.12.5, элемента памяти 1.12.8, формирователя кода 1.12.13 и первоначального запуска первого одновибратора 1.12.3. В частности, он может быть реализован с использованием резистивных элементов, описанных, например, в книге: Б.В.Тарабрин, Л.Ф.Лунин, Ю.Н.Смирнов и др. Интегральные микросхемы. Справочник. - 2-е изд., исп. - М.: Энергоатомиздат, 1985, с.190. Коммутатор 1.12.12, изображенный на фиг.15, предназначен для подачи информационных и переключающих сигналов на формирователь кода 1.12. Он может быть реализован на логических элементах ИЛИ, И, И-НЕ, описанных, например, в справочнике: Цифровые интегральные микросхемы. - М.: Радио и связь, 1994, с.234-237, и одновибраторе, в качестве которого могут быть использованы ждущие мультивибраторы, описанные в книге: В.А.Батушев, В.И.Вениаминов, В.Г.Ковалева и др. Микросхемы и их применение. - М.: Энергия, 1978, с. 193 или В.Л.Шило. Линейные интегральные схемы в радиоэлектронной аппаратуре. - М.: Советское радио, 1979, с.210-214. Первый и второй входы логического элемента ИЛИ 1.12.12.1, соединенные соответственно с входом логического элемента И-НЕ 1.12.12.2 и вторым входом логического элемента 1.12.12.3, соответствуют информационному входу коммутатора 1.12.12. Выход логического элемента И-НЕ 1.12.12.2 соединен с первым входом логического элемента И 1.12.12.3, выход которого является первым выходом коммутатора 1.12.12. Выход логического элемента ИЛИ 1.12.12.1 соединен со вторым входом логического элемента И 1.12.12.4, первый вход которого соответствует разрешающему входу коммутатора 1.12.12. Выход логического элемента И 1.12.12.4 соединен с вторым входом логического элемента ИЛИ 1.12.12.5, выход которого является информационным выходом коммутатора 1.12.12. Первый вход логического элемента ИЛИ 1.12.12.5 соединен с выходом одновибратора 1.12.12.6, вход которого является управляющим входом коммутатора 1.12.12. Формирователь кода 1.12.13, изображенный на фиг.16, предназначен для выработки управляющего сигнала на регулирование уровня выходного сигнала возбудителя 1.4 фиг.2. Он может быть реализован на двоичных счетчиках, построенных с использованием интегральных микросхем, описанных, например, в справочнике: Цифровые интегральные микросхемы, - М.: Радио и связь, 1994, с.143, рис.3.78.а. Входы D₁-D₈ двоичного счетчика являются установочным входом формирователя кода 1.12.13. Входы сложения/вычитания±1 и синхронизации С двоичного счетчика являются соответственно информационным и переключающим входами формирователя кода 1.12.13. Установочный R и разрешающий Е входы являются соответственно управляющим и разрешающим входами формирователя кода 1.12.13. Выходы счетчика являются выходом формирователя кода 1.12.13. Установочные вход и выход формирователя кода 1.12.13 представляют собой четырехразрядную шину. Формирователь начального кода 1.12.14 (фиг.17) предназначен для формирования сигнала, соответствующего коду первоначального значения выходного уровня сигнала возбудителя 1.4 фиг.2 U₀. Он может быть реализован с использованием резистивных матриц, описанных, например, в книге: Б.В.Тарабрин, Л.Ф.Лунин, Ю.Н.Смирнов и др. Интегральные микросхемы. Справочник. - 2-е изд., исп. - М.: Энергоатомиздат, 1985, с.190.The elements included in the general structure of the pathogen control unit are typical and can be technically implemented at the present time using a modern element base. The permission element 1.12.1 (Fig. 7) is designed to run the first one-shot 1.12.3 and can be implemented on the logical elements NAND, AND, described, for example, in the reference book: Digital integrated circuits. - M .: Radio and communications, 1994, p.234-237. The second input of the AND element 1.12.1.2 is the clock input of the permission element 1.12.1. The input of the AND gate 1.12.1.1 is the control input of the permission element 1.12.1. The output of the AND gate 1.12.1.1 is connected to the first input of the AND gate 1.12.1.2, the output of which is the output of the permission element 1.12.1. The clock generator 1.12.2 provides synchronous operation of all elements of the pathogen control unit. The schemes of such generators are known and are given, for example, in the book: Reference on integrated circuits. / Ed. V.V. Tarabrina. - M .: Energy, 1980, p. 588 fig. 5.35, 5.36. The first one-shot 1.12.3 is designed to set the measurement interval t _meas (pulse formation of the required duration). Waiting multivibrators can be used as the first one-shot 1.12.3, which are described, for example, in the book: V.A. Batushev, V.N. Veniaminov, V.G. Kovaleva, etc. Microcircuits and their application. - M .: Energy, 1978, p.193 or V.L. Shilo. Linear integrated circuits in electronic equipment. - M .: Soviet Radio, 1979, p. 210-214. The input element 1.12.4 is designed to extract an information sequence from a long series of a sequence of signals of the same sign. In particular, it can be implemented on a three-input logic element And (Fig. 8). Such logical elements are known and described, for example, in the book: V.Yu. Lavrienko. Handbook of semiconductor devices. - Kiev: Technique, 1980, p.399, Fig. 173. The first, second and third inputs of the logical element And are the control, clock and information inputs of the input element 1.12.4, respectively, and the output of the logical element And is the output of the input element 1.12.4. The error analyzer 1.12.5, shown in Fig.9, is designed to calculate k _tech (counting incorrectly received bits of the information sequence). It can be implemented on binary counters built using digital integrated circuits, described, for example, in the reference book: Digital integrated circuits. - M.: Radio and Communications, 1994, p. 68. The connected inputs V ₁ and NOT-V _{2 of the} binary counter are the control input of the error analyzer 1.12.5. C synchronization input and installation input

binary counter correspond to the information and zeroing inputs of the error analyzer 1.12.5. The Q-outputs of the binary counter correspond to the output of the error analyzer 1.12.5, which is a four-bit bus. The synchronization block 1.12.6, shown in figure 10, is designed to write and read information into the memory block 1.12.8, as well as to control the switch 1.12.12. The synchronization block can be implemented on the logical elements AND, AND-NOT, described, for example, in the directory: Digital integrated circuits. - M .: Radio and communications, 1994, p.234-237. The first input of the logical element AND 1.12.6.1, connected to the input of the logical element AND-NOT 1.12.6.2, is the control input of the synchronization element 1.12.6. The second input of the logical element AND 1.12.6.1 is the clock input of the synchronization element 1.12.6. The outputs of the logical elements AND 1.12.6.1 and NAND 1.12.6.2 are respectively the first and second outputs of the synchronization element 1.12.6. The second one-shot 1.12.7 is designed to generate signals with a duration corresponding to the time of regulation of the transmission power. As the first and second single vibrators, standby multivibrators can be used, as described, for example, in the book: V.A. Batushev, V.N. Veniaminov, V.G. Kovaleva, etc. Microcircuits and their application. - M .: Energy, 1978, p.193 or V.L. Shilo. Linear integrated circuits in electronic equipment. - M .: Soviet Radio, 1979, p. 210-214. The memory element 1.12.8 is designed to store the results of the calculation of the error analyzer 1.12.5 at the time of regulation of the level of the output signal of the pathogen 1.4 of figure 2 on each measurement interval t _meas . In particular, it can be implemented on the shift register 1.12.8.1 and four logical elements AND 1.12.8.2-1.12.8.5 (Fig.11). The schemes of such registers are known and described, for example, in the reference book: Digital Integrated Circuits. - M.: Radio and Communications, 1994, p. 62, Fig. 2.49.a. Schemes of logical elements AND 1.12.8.2-1.12.8.5 are also known and described, for example, in the directory: Digital Integrated Circuits. - M .: Radio and communication. 1994, p. 234-237. The second inputs of the logical elements AND 1.12.8.2-1.12.8.5 are connected and are the enable input of the memory element 1.12.8. The synchronization input C and the information inputs D ₁ -D ₄ of the shift register 1.12.8.1 are respectively the clock and information inputs of the memory element 1.12.8. The setting input of the shift register 1.12.8.1 is the control input of the memory element 1.12.8. The outputs Q ₁ -Q ₄ of the shift register 1.12.8.1 are respectively connected to the first inputs of the logical elements AND 1.12.8.2-1.12.8.5, the outputs of which are the output of the memory element 1.12.8. The information input and output of the memory element 1.12.8 are a four-bit bus. The state assessment element 1.12.9 depicted in FIG. 12 is intended to compare k _tech with k _min and k _max . In particular, it can be implemented on comparators made on integrated circuits, described, for example, in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov and others. Integrated circuits: Reference. - 2nd ed., Spanish, - M: Energoatomizdat, 1985, p. 285. The inputs A ₀ -A _{3 of the} comparator 1.12.9.1, respectively connected to the inputs of the same name of the comparator 1.12.9.2, are the information input of the element for assessing the state 1.12.9. The inputs B ₀ -B _{3 of the} comparators 1.12.9.1 and 1.12.9.2 are the installation input of the state assessment element 1.12.9. The third and first outputs of the comparators 1.12.9.1 and 1.12.9.2 are the output of the state assessment unit 1.12.9, which is a two-bit bus. The quality assessment threshold generator 1.12.10 is intended for setting the values of k _min and k _max . In particular, resistive matrices on integrated circuits, described, for example, in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov, can be used as a driver of thresholds for assessing the quality of 1.12.10 (Fig. 13) and other integrated circuits. Directory. - 2nd ed., Spanish. - M .: Energoatomizdat, 1985, p. 190. The outputs of the resistive matrices make up the output of the threshold shaper, which is an eight-bit bus. The initial state setting element 1.12.11 shown in Fig. 14 is intended to bring the error analyzer 1.12.5, the memory element 1.12.8, the code generator 1.12.13 to the initial state and initial start-up of the first one-shot 1.12.3. In particular, it can be implemented using resistive elements described, for example, in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov, etc. Integrated circuits. Directory. - 2nd ed., Spanish. - M .: Energoatomizdat, 1985, p. 190. The switch 1.12.12, shown in Fig.15, is designed to supply information and switching signals to the shaper code 1.12. It can be implemented on the logical elements OR, AND, AND-NOT, described, for example, in the reference book: Digital integrated circuits. - M .: Radio and communications, 1994, p.234-237, and a single vibrator, which can be used as standby multivibrators described in the book: V.A. Batushev, V.I. Veniaminov, V.G. Kovaleva and Other microcircuits and their application. - M .: Energy, 1978, p. 193 or V.L.Shilo. Linear integrated circuits in electronic equipment. - M .: Soviet Radio, 1979, p. 210-214. The first and second inputs of the logical element OR 1.12.12.1 connected respectively to the input of the logical element AND-NOT 1.12.12.2 and the second input of the logical element 1.12.12.3 correspond to the information input of the switch 1.12.12. The output of the AND gate 1.12.12.2 is connected to the first input of the AND gate 1.12.12.3, the output of which is the first output of the switch 1.12.12. The output of the OR gate 1.12.12.1 is connected to the second input of the AND gate 1.12.12.4, the first input of which corresponds to the enable input of the switch 1.12.12. The output of the AND gate 1.12.12.4 is connected to the second input of the OR gate 1.12.12.5, the output of which is the information output of the switch 1.12.12. The first input of the OR gate 1.12.12.5 is connected to the output of the one-shot 1.12.12.6, the input of which is the control input of the switch 1.12.12. Shaper code 1.12.13, shown in Fig.16, is designed to generate a control signal to control the level of the output signal of the pathogen 1.4 of Fig.2. It can be implemented on binary counters built using integrated circuits, described, for example, in the reference book: Digital Integrated Circuits, - M .: Radio and Communication, 1994, p.143, Fig.3.78.a. The inputs D ₁ -D _{8 of the} binary counter are the installation input of the code generator 1.12.13. The addition / subtraction inputs ± 1 and synchronization C of the binary counter are respectively the information and switching inputs of the code generator 1.12.13. The installation R and enable E inputs are respectively the control and enable inputs of the code generator 1.12.13. The counter outputs are the output of the code generator 1.12.13. The installation input and output of the code driver 1.12.13 are a four-bit bus. Shaper initial code 1.12.14 (Fig.17) is designed to generate a signal corresponding to the code of the initial value of the output level of the signal of the pathogen 1.4 of figure 2 U ₀ . It can be implemented using resistive matrices, described, for example, in the book: B.V. Tarabrin, L.F. Lunin, Yu.N. Smirnov, etc. Integrated circuits. Directory. - 2nd ed., Spanish. - M .: Energoatomizdat, 1985, p. 190.

The receiving antenna 2.1 of the satellite repeater 2 of FIG. 2 is designed to receive signals emitted by earth stations in satellite communications 1 of FIG. 2. Low-noise power amplifier 2.2 is designed for pre-amplification of a signal received from earth stations in satellite communications 1 of Fig.2. The circuits of low-noise power amplifiers are known and described, for example, in the book: G. B. Askinazi, V. L. Bykov, G. V. Vodopyanov and others. Handbook of satellite communications and broadcasting. Ed. L.Ya. Kantora. - M .: Radio and communications, 1983, p. 147-152, 174-175, Fig. 8.2. Mixer 2.3 satellite relay 2 of figure 2 is designed to convert amplified in the input low-noise amplifier of the received microwave signal into an IF signal. Mixer circuits are known and described in the same book on p. 152-154, Fig. 8.8. The selective path 2.4 of the satellite repeater 2 of FIG. 2 as part of an intermediate frequency amplifier 2.4.1, a bandpass filter 2.4.2 and a demodulator 2.4.3 is intended to amplify the signal in the frequency band to a predetermined level and to extract a digital signal from the corresponding satellite earth station. Schemes of electoral paths are known and described, for example, in the books: A.D. Fortushenko, Yu.A. Afanasyev, M.V. Brodsky, and others. Fundamentals of the technical design of communications systems equipment using satellite. Ed. A.D. Fortushenko. - M .: Communication, 1972, p. 156-160, Fig. 2.28 and the Handbook of radio relay communication. Under. ed. S.V. Borodich. - M .: Radio and communications, 1981, p.115-152. The local oscillator 2.5 is designed to form the frequency used in the mixer 2.3 for linear transfer of the received signal to the intermediate frequency. Heterodyne circuits are known and described, for example, in the book: A.D. Fortushenko, Yu.A. Afanasyev, M.V. Brodsky, and others. Fundamentals of the technical design of communications equipment using satellite systems. Ed. A.D. Fortushenko. - M.: Communication, 1972. S. 160-170. Switch 2.6 is intended for switching the input digital signals of earth stations in satellite communications 1 _{1-N of} Fig.2 to the inputs of the switches of the test signal 2.7 in accordance with the established connection diagram. The switch is a typical device for switching digital streams, the structural diagram of its implementation is shown, for example, in the book: B.Ya. Sovetov, S.A.Yakovlev. Building Integrated Services Networks. - L .: Mechanical Engineering, 1990, p. 140.

The switch of the test signal 2.7, shown in figure 3, is designed to regulate the transmission of test signals of earth stations relative to certain time intervals allocated for the analysis of the quality of information channels, and consists of a shaper of the trigger signal timer 2.7.1, timer 2.7.2, even-cycle counter 2.7.3, odd loop counter 2.7.4, one-shot 2.7.5, first 2.7.6 and second 2.7.7 logic elements AND and the first 2.7.8 and second 2.7.8 logic elements OR. The output of the shaper of the start signal of the timer 2.7.1 is connected to the input of the timer 2.7.2, the first, second and third outputs of which are connected to the inputs of the even-cycle counter 2.7.3, one-shot 2.7.5, and the odd-cycle counter 2.7.4, respectively. The outputs of the even-cycle counter 2.7.3 and the odd-cycle counter 2.7.4 are connected to the first inputs of the logic elements AND 2.7.6 and 2.7.7, respectively, and the output of the single-shot 2.7.5 is connected to the second inputs of the logic elements AND 2.7.6 and 2.7.7 . The outputs of the logic elements AND 2.7.6 and 2.7.7 are connected to the second inputs of the logical elements OR 2.7.8 and 2.7.9, respectively, and the first inputs of the logic elements OR 2.7.8 and 2.7.9 are connected respectively to the first and second inputs of the driver timer 2.7.1 and are the first and second inputs of the test signal switch 2.7. The outputs of the logic elements OR 2.7.8 and 2.7.9 are respectively the information and signal outputs of the test signal switch 2.7.

The elements included in the general structure of the test signal switch 2.7 of FIG. 3 are typical and can be technically implemented at the present time using a modern element base. The driver signal start timer 2.7.1 figure 4 is intended to start the timer 2.7.2. It can be implemented on two decoders 2.7.1.1, 2.7.1.2 and the logical element OR. Decryptor schemes are known and are given, for example, in the book: I.P. Shelestov. Hams: useful circuits. Book 2. - M .: Solon, 1998, p.40, 41, fig. 1.48.c. The timer is designed to control at appropriate times relative to the structure of the signal frame by the counters of even cycles 2.7.3 and odd cycles 2.7.4. The schemes of such timers are known and are given, for example, in the book: A.A. Bokunyaev, N.M. Borisov, E. B. Gumel and others. A reference book of a radio amateur designer. Book 1. / Ed. N.I. Chistyakova. - M.: Radio and Communications, 1993, p. 314, Fig. 8.123. Counters of even cycles 2.7.3 and odd cycles 2.7.4 of figure 3 is intended to highlight the test signals of the first and second correspondents, respectively. The schemes of such counters are known and are given, for example, in the book: A. A. Bokunyaev, N. M. Borisov, E. B. Gumel and others. A reference book of a radio amateur designer. Book 1. / Ed. N.I. Chistyakova. - M.: Radio and Communications, 1993, p.309, Fig. 8.118. The one-shot 2.7.5 of FIG. 3 is intended for generating a single pulse of duration corresponding to the test signal in the structure of the information-test signal. As a single-vibrator 2.7.5, standby multivibrators can be used, which are described, for example, in the book: V.A. Batushev, V.N. Veniaminov, V.G. Kovaleva, etc. Microcircuits and their application. - M .: Energy, 1978, p.193 or V.L. Shilo. Linear integrated circuits in electronic equipment. - M .: Soviet Radio, 1979, p. 210-214. Schemes of logical elements OR, And are known and are given in the book: A.A. Bokunyaev, N.M. Borisov, E. B. Gumel and others. A reference book of a radio amateur designer. Book 1. / Ed. N.I. Chistyakova. - M.: Radio and Communications, 1993, p. 304, Fig. 8.92.a and 8.92.6, respectively. The adder modulo two 2.8 is designed to generate an information or test signal corresponding to a specific correspondent. As an adder modulo two, an adder described in the book can be used: V.A.Bushuev, V.N. Veniaminov, V.G. Kovalev, etc. Microcircuits and their application. - M .: Energy, 1978, p.178-180. The temporary association unit 2.9 is designed to generate a group signal of the corresponding earth stations of satellite communications and modulate the frequency of the transmitter of a satellite repeater. The schemes of such temporary association units are known and described, for example, in the book: V.A. Bukovsky, V.V. Ignatov, A.P. Rodimov and others. Military space communications systems. Ed. A.P. Rodimova. - L .: YOU, 1984, pp. 192-206, Fig. 9.7. The power amplifier 2.11 is designed to amplify the power of the microwave radio signal to the required level. Power amplifier circuits are known and described, for example, in the book: G.B. Askinazi, VL Bykov, GV Vodopyanov, and others. A Handbook of Satellite Communications and Broadcasting. Ed. L.Ya. Kantora. - M.: Radio and Communications, 1983, p. 166-173, Fig. 9.9. The transmitting antenna 2.12 of the satellite relay 2 of FIG. 2 is intended to transmit signals to the satellite earth station 1 of FIG. 2. The receiving and transmitting antennas of satellite repeaters are known and described in the same book on p.219-221, Fig. 11.13.

A satellite communication system with multiple access with frequency division, processing and switching of signals on board the satellite repeater of figure 1 works as follows.

In the satellite communication system under consideration, the main type of communication is communication in the information areas between interacting correspondents. In this case, the main and subordinate earth stations of satellite communications are distinguished, relative to which they form temporary positions in the digital stream, comparable with even or odd cycles of information and test signals.

The digital stream from the subscriber of the earth station of satellite communications 1 _{1 is} fed to the information input of the separation and combining unit 1.8 of FIG. 2, which provides its asynchronous input, as well as the ability to generate and enter additional service information. From the information output of the separation and combining unit 1.8 of FIG. 2, the total digital stream enters simultaneously the input of the delay line 1.10 of FIG. 2 and the information input of the unit for generating information-test signals 1.11 of FIG. 2.

In the unit for generating information-test signals 1.11 of FIG. 2, the formation of a generalized signal is provided, including the information and, at appropriate times, test components in accordance with the structure of the signal frame. This signal through the pathogen 1.4 of figure 2 is transferred to the operating frequency range of the satellite earth station 1 ₁ and is fed to the power amplifier 1.3 of figure 2, where it is amplified to the required level and through the duplexer 1.1 of figure 2, which provides frequency isolation of the transmission and reception paths , through the antenna-feeder path 1.2 of figure 2 is transmitted to the satellite repeater 2 of figure 2.

The signal of the satellite repeater 2 of FIG. 2, received by the antenna-feeder path 1.2 of FIG. 2 of the satellite earth station 1 ₁ through the duplexer 1.1 of FIG. 2 is fed to the input unit 1.5 of FIG. 2, where it is selected, the information signal is extracted from interference, preliminary processing and reinforcement. The selected information signal through the frequency separation unit 1.6 of FIG. 2, providing signal selectivity in the frequency of the receiving path, is fed to the receiver 1.7 of FIG. 2. In the receiver 1.7 of FIG. 2, amplification, filtering and demodulation of the received signals is carried out.

The demodulated signal is fed to the input of the separation and combining unit 1.8 of FIG. 2, where it is normalized in shape, voltage and current to the required level. Then it is fed from the signal output of the separation and combining unit 1.8 of FIG. 2 to the signal input of the adder modulo two 1.9 of FIG. 2, to the information input of which an information-test signal is delayed by the delay line 1.10 of FIG. 2 for a time comparable to the propagation time the signal on the line is a satellite communications earth station — a satellite repeater — satellite communications earth station. In the adder modulo two 1.9 of FIG. 2, by comparing the received and delayed signals, the correspondent signal is extracted.

A feature of the operation of satellite communication lines with frequency separation of signals on the satellite repeater 2 of FIG. 2 is that the required quality of information exchange on these lines is achieved by maintaining the same signal level in power at the input of the satellite repeater 2 of FIG. 2 from 1 ₁ - 1 _N satellite earth stations.

It is known (see Patent RU No. 2214682 C2 7, class N 04 B 7/005) that failure to satisfy the condition of equal signal power at the input of a satellite repeater leads to a change in the error coefficient in satellite communication channels. Therefore, the regulation of the signal level at the input of the satellite relay 2 of figure 2 in the inventive device is proposed to carry out relative to the quality estimates of the channels by changing the bit error. To this end, it is proposed to change the output signal level of satellite earth stations 1 ₁ -1 _{N of} FIG _. 2 with respect to a pre-established quality of the communication channel, estimated relative to the range of the error coefficient, which is determined relative to the test signals transmitted and received by each satellite earth station 1 ₁ -1 _N through the satellite relay 2 of FIG. 2, respectively. The regulation of the output signal power at satellite earth stations 1 ₁ -1 _{N of} FIG _. 2 in this case is carried out by introducing into the signal control circuit of its pathogen the information-test signal generation blocks 1.11 and the pathogen 1.12 of FIG. 2.

Switch test signal 2.7 of figure 3 works as follows. Upon receipt of the information and signal inputs from the switch 2.6 of Fig. 3 of the clock signals corresponding to the beginning of the cycles of the information-test sequence, the shaper of the start signal of the timer 2.7.1 generates a signal relative to which the timer 2.7.2 of Fig. 3 starts. The signals of the timer 2.7.2 of Fig.3. at the corresponding time points determined by the cycle of the signal frame structure, they arrive at the counters of even cycles 2.7.3, odd cycles 2.7.4 and one-shot 2.7.5 of FIG. 3. Cycle counters respectively distinguish the signals of even and odd cycles, which makes it possible in the future to ensure the passage of test signals of the first and second correspondent. Single vibrator 2.7.5 figure 3. generates a single impulse of duration corresponding to the test signal in the structure of the information-test signal. As a result of the operation of the counters 2.7.3, 2.7.4 and the one-shot 2.7.5 of FIG. 3, the outputs of the first and second logic elements 2.7.6 and 2.7.7 of FIG. 3 generate control signals for the first and second logical elements OR 2.7.8 and 2.7.9. respectively, determining the passage of the test signal from the first or second correspondent. At the same time, at the information and signal outputs of the test signal switch 2.7 of FIG. 3, there is a signal corresponding to a logical unit or test signal. The combination of these signals in the adder modulo two 2.8. figure 2 leads to the inversion of the transmitted test signal, which is taken into account when it is received at the satellite earth station 1 _{1 of} figure 2. by the element NOT 1.11.9 of FIG. 4. Separation in the generalized information and test signal of the time intervals of the passage of test signals relative to different correspondents is necessary to remove the uncertainty in the distribution of the error coefficient relative to the communication lines of the corresponding correspondents, as well as by the different contributions of different sections of the satellite communication lines (satellite earth station - satellite relay, satellite relay - satellite communications earth station) in the process of the occurrence of a bit error. Voltage plots, revealing the nature of the operation of the elements of the switch of the test signal of Fig.3, are presented in Fig.18.

The unit for generating information-test signals 1.11 of FIG. 5 works as follows. The signal from the information output of the separation and combining unit 1.8 of FIG. 2 is fed to the information input of the information-test signal generation unit and then through the first logical element NOT 1.11.1 of FIG. 5, the first logical element AND 1.11.2 of FIG. 5 and the OR logic element 1.11.3 figure 5 is fed to the 2 output of block 1.11. In this case, the first logical element AND 1.11.2 of FIG. 5 acts as a key, providing the information signal is turned off and the test signal is connected at time intervals determined by the operation of the one-shot 1.11.12 of FIG. 5, the operation of which is correlated with the structure of the signal frame. The OR element 1.11.3 of FIG. 5 forms a generalized information-test signal, which is further transmitted by the satellite earth station 1 _{1 of} FIG. 2.

Switching the generated test signal, relative to which the communication quality is evaluated, is carried out by means of the third element AND 1.11.4 of FIG. 5. The test signal generated in the test sequence generator 1.11.11 of FIG. 5, in parallel, through the third logical element AND 1.11.4 and the second logical element NOT 1.11.9 of FIG. 5, is fed to the corresponding time intervals determined by the structure of the signal frame for information and the signal inputs of the logical element OR 1.11.3 and the input of the fifth logical element AND 1.11.10, respectively.

The coordinated operation of all elements of the information-test signal generation block 1.11 of FIG. 2 regarding the signal frame structure is ensured by the operation of the timer 1.11.9 and the single-shot 1.11.12 of FIG. 5. Moreover, by means of a timer 1.11.8 of FIG. 5, the signal structure is monitored. The timer 1.11.8 of FIG. 5 is triggered by a clock included in the sequence of the information-test signal generated by the satellite earth station for transmission. The duration of the time intervals corresponding to the test signals is formed relative to the frame structure by means of a single-shot 1.11.12. figure 5.

The error signal is extracted from the received signal from the satellite repeater 2 of FIG. 2 based on a comparison in the adder modulo two 1.11.6 of FIG. 5 of the test signal generated by the test sequence generator 1.11.11 and the received test signal from the satellite repeater, which is fed to the signal the adder input modulo two 1.11.6 figure 5. As a result of summing these signals in an adder modulo two 1.11.6 of FIG. 5, an error signal is generated at its output relative to the test signal generated by the test sequence generator 1.11.11 and delayed by the second delay line 1.11.8, and the received signals. In this case, the first and second delay lines 1.11.7 and 1.11.8 and the fourth element And 1.11.5 of FIG. 5 provide synchronization of the processing of the information-test signal transmitted and received through the satellite relay by this satellite earth station and the test signal generated on this earth station when transmitting it. The extracted error signal from the output of the adder modulo two 1.11.6 of FIG. 5 is fed to the input of the exciter control unit 1.12 of FIG. 2 and is further used in the exciter control unit 1.12 of FIG. 2 to control the signal level at the output of the satellite earth station. Due to the fact that the information-test signal received from the satellite repeater 2 of FIG. 2 comes inverted with respect to the signal generated at the satellite earth station 1 _{1 of} FIG. 2, a second logical element NOT 1.11 is introduced to eliminate this discrepancy. 9 of Fig. 5. Voltage plots, revealing the nature of the operation of the elements of the unit for generating information-test signals 1.11 of Fig. 5, are presented in Fig. 19.

The operation of the pathogen control unit 1.12 of FIG. 6 can be divided into two stages: the first stage corresponds to the installation of the unit in its initial state, the second - direct operation.

Setting the block to its initial state involves the following actions: setting thresholds for evaluating the signal quality k _min and k _max preparing code shaper for operation 1.12.13, preparing for setting a code corresponding to the initial output signal of the pathogen U ₀ , zeroing the memory element 1.12.8.

The thresholds for assessing the quality of the signal k _min and k _max are set by connecting the installation input of the state assessment element 1.12.9 of FIG. 12 through the resistance R of the resistive matrices of the driver of the quality assessment thresholds 1.12.10 of FIG. 13 to the power source E.

In this case, a code is generated that is determined by connecting the installation inputs of the comparators 1.12.9.1 and 1.12.9.2 of FIG. 12, with respect to which the current signal quality is evaluated and, subsequently, the level of the output signal of the exciter 1.4 of FIG. 2 is adjusted. Preparation of the code shaper 1.12.13 to generate the initial output signal level code of the pathogen U _{0 is} carried out by connecting the setup inputs D ₁ -D _{8 of the} binary counter of the code shaper 1.12.13 of Fig.16 through the resistance R of the resistive matrix of the shaper of the initial code 1.12.14 of Fig.17 to power supply E, as well as applying to the permissive input E of code generator 1.12.13 a signal corresponding to logical “1” generated in the initial state setting element 1.12.11 of Fig. 14 by connecting the resistance R to the power source I am E.

The reset of the counter of the code generator 1.12.13 of Fig.16 is carried out by supplying to the resetting input R a logical "1" generated in the element of setting the initial state 1.12.11 of Fig.14 by connecting the resistance R to the power source E.

Reset of the previous states, corresponding to the zeroing of the register in the memory element 1.12.8 of FIG. 11, is carried out by applying a signal of the corresponding logical “1” by connecting the power supply E through the resistor R of the initial state setting element 1.12.11 of FIG. 14 to the control input R of the memory element 1.12 .8 Fig. 11.

The set of actions described above prepares the unit for immediate work.

The generated signal in the installation element of the initial state 1.12.11, corresponding to the logical "1", is output from the output (Fig. 14) to the control input of the switch 1.12.12 of Fig. 15. This signal triggers a one-shot 1.12.12.6 Fig.15, generating a pulse signal, which through the logical element OR 1.12.12.5 of the switch 1.12.12 Fig.15 through its first output is fed to the information input of the code generator 1.12.13 Fig.16. This signal provides a record in the binary counter (Fig.16) of the generated code in the generator of the initial code 12/12/14 Fig.17 at the stage of installation of the block in the initial state. As a result, at the output of the code generator 1.12.13, the initial level code of the pathogen output signal 1.4 of FIG. 2 U _{0 is set} , with respect to which further regulation of the pathogen output signal is performed. This determines a further algorithm for the operation of the pathogen control unit.

An assessment of the correspondence of the output signal of the pathogen 1.4 of Fig. 2 to the required quality of the generated signal is carried out at a time interval t _measurements sufficient for the collection of statistical data on the error coefficient corresponding to the current signal quality. The required time interval t is _measured by the first one-shot 1.12.3, which starts when there is no signal on the control and clock inputs of the resolution element 1.12.1 of FIG. 7, respectively, from the outputs of the second one-shot 1.12.7 and the clock 1.12.2.

The signal generated by the first one-shot 1.12.3, simultaneously fed to the control inputs of the input element 1.12.4 of Fig. 8, the error analyzer 1.12.5 of Fig. 9, the synchronization element 1.12.6 of Fig. 10, performs a number of functions: sets the counting time of single pulses, arriving at the information input of the input element 1.12.4 of Fig. 8, the logic of which is determined by a three-input logic element And Fig. 8. The signal at the output of input element 1.12.4 appears during the signal generated by the first one-shot 1.12.3 signal with the arrival of an information signal corresponding to a logical "1" with a frequency of a clock pulse generator 1.12.2 supplied to clock input 2 of input element 1.12.4 of Fig. 8 clock generator 1.12.2. Information signals from the output of the input element 1.12.4 go to the information input of the error analyzer 1.12.5, which is the synchronizing input of the binary counter (Fig.9). Since the write-enabled inputs of the binary counter of the error analyzer 1.12.5 of Fig. 9 are connected to the output of the first one-shot 1.12.3, this provides a count of incoming pulses to the information input of the error analyzer 1.12.5 only during the operation of the first one-shot 1.12.3. The binary counter (Fig. 9), having counted the number of information pulses, generates an information signal at its output in the form of a binary code, which, based on the signals generated in the synchronization element 1.12.6 of Fig. 10, is a logical element And 1.12.6.2, with a clock repetition rate pulses of the clock pulse generator 1.12.2, arriving at the first input of the logic element And 1.12.6.1, during the operation of the first single-shot 1.12.3, the signals of which are fed to the input of the logic element And 1.12.6.1, are recorded in the memory element 1.12.8. The recorded information in the memory element 1.12.8 is stored until the next receipt of information signals from the output of the error analyzer 1.12.5. During operation of the error analyzer 1.12.5, information is not read from the memory element 1.12.8. This is ensured due to the fact that during operation of the first one-shot 1.12.3 in the synchronization element 1.12.6 at the output of the logical element AND-NOT 1.12.6.2 of figure 10, a inhibitory signal of logical "0" is generated, which, when received at the enable input of the memory element 1.12.8 (Fig.11, the first inputs of logical elements AND 1.12.8.2-1.12.8.5), provides a state of logical "0" at the output of these logical elements and memory element 1.12.8 as a whole. The same inhibitory signal blocks the promotion of information from the output of the state assessment element 1.12.9 through the elements of the switch 1.12.12 to the input of the code generator 1.12.13. Blocking is carried out by supplying a logical "0" to the first input of the logical element AND 1.12.12.4 Fig.15, corresponding to the enable input of the switch 1.12.12.

Upon completion of the operation of the first one-shot 1.12.3, an output signal corresponding to the logical “1” is generated at the output of the AND-NOT 1.12.6.2 logical element of FIG. 10, which provides for reading information from memory element 1.12.8 and writing information through the switch 1.12.12 ( logical "1" at the first input of the logical element AND 1.12.12.4, Fig.15) to the shaper code 1.12.13, and also provides the launch of the second one-shot 1.12.7.

Information in the form of a code from the output of the memory element 1.12.8 is supplied to the inputs A0-A4 of the comparators 1.12.9.1 and 1.12.9.2 corresponding to the information input of the evaluation element 1.12.9 of Fig. 12. Since at the installation inputs of 2 comparators 1.12.9.1 and 1.12.9.2 of FIG. 12 a code is pre-set that corresponds to the required thresholds for evaluating the signal quality k _min and k _max , then comparators 1.12.9.1 and 1.12.9.2 compare the code of the information signal with threshold codes . The comparison results in the form of logical signals “1” or “0” from the outputs of the comparators 1.12.9.1 and 1.12.9.2 of FIG. 12 are fed to the information input of the switch 1.12.12 of FIG. 15, which, depending on what the information signal corresponds to relative to the selected threshold connects the first and second output of the switch 1.12.12 to the information and switching inputs of the code generator 1.12.13 or only to the information input of the code generator 1.12.13 Fig.16.

Consider the possible cases. If k _tech <k _max , then at the output of the comparator 1.12.9.1 of Fig.12 there will be a logic signal "0", and at the output of the comparator 1.12.9.2 - "1". These signals, arriving at the information input "switch 1.12.12 Fig.15, which corresponds to the supply of signals of logical" 0 "and logical" 1 "to the inputs of the logical element OR 1.12.12.1 Fig.15. As a result, the second output of the switch 1.12.12 a logical “1” signal will be generated, which, entering the switching input of the code shaper 1.12.13, transfers the binary counter of the code shaper 1.12.13 of Fig.15 to the account increase mode. Upon the arrival of the information signal from the first output of the switch 1.12.12 to the information input shaper code 1.12.13 binary with etchik increases at its output with respect to discharge a preset code, to a unit that corresponds to an increase in the output level of agent 1 1.4.

If k _tech <k _min at the output of the comparators 1.12.9.1 and 1.12.9.2 of FIG. 12 there will be signals of logical “1” and logical “0, respectively, then logical“ 1 ”and logical will be generated at the first and second outputs of the switch 1.12.12 "0" respectively. These signals include the binary counter of the code generator 1.12.13 of FIG. 15 for decreasing the counter output code (FIG. 16) with respect to the preset one. This corresponds to a decrease in the level of the output signal of the pathogen 1.4 of figure 1.

In the case k _min <k _tech <kma _x at the outputs of the comparators 1.12.9.1 and 1.12.9.2, logical 0 signals are generated. This corresponds to the fact that the logical "0" signals are generated at the first and second outputs of the switch 1.12.12, which do not change the state of the binary counter of the code generator 1.12.13 of Fig.16. This corresponds to the fact that the level of the output signal of the pathogen 1.4 of figure 2 remains unchanged.

At the time of regulation of the level of the output signal of the pathogen 1.4 of figure 2, in order to ensure stable operation of the unit and obtain unambiguous results, it is necessary to prohibit the passage of information pulses to the error analyzer 1.12.5, prohibit its operation, reset it and prepare it for work on the next t _measurement interval. This set of actions is provided by turning on the second one-shot 1.12.7 by the signal generated in the synchronization element 1.12.6 by the AND-NOT logical element 1.12.6.2 of FIG. 10 at the end of the first one-shot 1.12.3. The signal from the output of the second one-shot 1.12.7 goes to the resetting input 2.3 of the error analyzer 1.12.5 of FIG. 9, resets it, and also goes to the control input of the resolution element 1.12.1 of FIG. 7, preventing the start of the first one-shot 1.12.3. Upon completion of the second one-shot 1.12.7 at the output of the AND-NOT 1.12.1 logic element of FIG. 7, a signal is generated corresponding to the logical “1”, which will be enable to turn on the first one-shot 1.12.3 for the next operation cycle.

Claims (4)

1. Satellite communication system, including N≥2 satellite earth stations and a satellite repeater, which contains a receiving antenna, the output of which is connected to the input of a low-noise power amplifier, the output of which is connected to the signal input of the mixer, N selective paths, each of which consists in series included intermediate frequency amplifier, band-pass filter, demodulator, and the input of the intermediate frequency amplifier and the output of the demodulator are respectively the input and output of the selective path, the inputs of the selective paths are combined and connected to the signal output of the mixer, the heterodyne input of which is connected to the output of the local oscillator, the output of the i-th selective path, where i = 1, 2, ... N, is connected to the i-th input of the switch, N / 2 adders modulo two, the output of the jth, where j = 1, 2, ... N / 2, of the adder modulo two is connected to the jth input of the temporary combining unit, the output of which is connected to the signal input of the modulator, and the heterodyne input to the output local oscillator, the modulator output is connected to the input of the power amplifier, the output of which is connected to the front input antenna, and each satellite earth station includes a duplexer, the transceiver input-output of which is connected to the antenna-feeder path, the signal input is connected to the output of the power amplifier, the input of which is connected to the exciter output, the signal output of the duplexer is connected to the input of the input unit, the output of which connected to the input of the frequency separation unit, the output of which is connected to the input of the receiver, the output of which is connected to the signal input of the separation and combining unit, a delay line whose output is connected to and the formation input of the adder modulo two, the signal input of which is connected to the signal output of the separation and combining unit, and its information output is connected to the input of the delay line, and the information input of the separation and combining unit and the output of the adder modulo two are respectively the information input and output of the earth station satellite communication, characterized in that N / 2 test signal switches are added to the satellite repeater, the i-th and (i + 1) -th switch outputs, where i is odd, are connected respectively, to the information and signal inputs of the [j = (i + 1) / 2] -th switch of the test signal, and the information and signal outputs of the j-switch of the test signal are connected to the information and signal inputs of the j-th adder modulo two, and at each satellite earth station, a pathogen control unit and an information-test signal generation unit are additionally introduced, the control and information outputs of which are connected respectively to the control input of the pathogen control unit and data input of the exciter, and the information and inputs the signal forming unit of information and test signals are connected to inputs of the delay line respectively and an adder for modulo two, and the output control unit exciter is connected to the control input of the pathogen. 2. The device according to claim 1, characterized in that the test signal switch consists of a timer trigger, a timer, an even-cycle counter, an odd-cycle counter, a one-shot, the first and second logical elements AND, and the first and second logical elements OR, the output of the driver the timer start signal is connected to the timer input, the first, second and third outputs of which are connected to the inputs of the even-cycle counter, one-shot, odd-cycle counter, the outputs of the even-cycle counter and the odd counter x cycles are connected to the first inputs of the logical elements AND, respectively, and the output of the single-vibrator is connected to the second inputs of the logical elements AND, the outputs of the logical elements AND are connected to the second inputs, respectively, of the logical elements OR, and the first inputs of the logical elements OR are connected respectively to the first and second inputs of the signal conditioner timer start and are the first and second inputs of the test signal switch, and the outputs of the logic elements OR are respectively the first and second outputs of the comm Tatorey test signal. 3. The device according to claim 1, characterized in that the information-test signal generating unit consists of a first logical element NOT, the output of which is connected to the second input of the first logical element And, the first input of which is connected to the timer input and is the first input of the information generating unit -test signals, the output of the first logical element AND is connected to the first input of the logical element OR, the second input of which is connected to the output of the third logical element AND, and the output of the logical element OR is T With the output of the information-test signals generating unit, the input of the first logical element is NOT connected to the first input of the third logical element AND, the input of the test sequence generator, the output of the one-shot, the second input of the fifth logical element And and the input of the first delay line, the second input of the third logical element And is connected to the output of the test sequence generator and the input of the second logical element NOT, the output of which is connected to the first input of the fifth logical element AND, the output of which connected to the input of the second delay line, the output of which is connected to the second input of the adder modulo two, the first input of which is the second input of the information-test signal generation unit, the timer output is connected to the input of the one-shot, the output of the first delay line is connected to the first input of the fourth logical element And, the second input of which is connected to the output of the adder modulo two, and the output of the fourth logical element And is the first output of the unit for generating information-test signals. 4. The device according to claim 1, characterized in that the pathogen control unit consists of a permission element, the control input of which is connected to the output of the second one-shot, and synchronizing to the synchronizing input of the input element, the control input of which is connected to the output of the first one-shot, control input of the error analyzer and the control input of the synchronization element, the clock input of the synchronization element is connected to the output of the clock generator and the clock input of the input element, the output of the resolution element p It is connected to the input of the first one-shot, the output of the input element is connected to the information input of the error analyzer, the control input of which is connected to the output of the second one-shot, the output of the error analyzer is connected to the information input of the memory element, the clock and enable inputs of which are connected respectively to the clock and enable outputs of the synchronization element, the control input of the memory element is connected to the control output of the initial state setting element, the control input of the switch and controlling mu input of the code generator, the output of the memory element is connected to the information input of the state assessment element, the installation input of which is connected to the output of the quality assessment threshold generator, and the output of the state assessment element is connected to the information input of the switch, the permitting input of which is connected to the allowing input of the memory element and the input of the second one-shot, allowing the output of the initial state setting element is connected to the enable input of the code generator, the information and switching inputs of which are connected respectively to the information and switching outputs of the switch, and the installation input of the code generator is connected to the output of the initial generator, and the information input of the input element and the information output of the code generator are the input and output of the exciter control unit, respectively.

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