SU475741A1 - Device of discrete-weight addition of separated signals - Google Patents

Description

The invention relates to the field of receiving spaced signals in radio communication systems with the transmission of synchronization signals and use when receiving the zero zone.

Devices are known in which the separation of separated signals is carried out at reception with the introduction of weight coefficients into each reception channel, the magnitude of which is proportional to the expected signal amplitude and inversely proportional to the power of the noise acting in the channel.

In this case, the demodulation device must contain measuring circuits that generate data on the interference power and signal level, as well as a device for inputting weighting factors in the form of, for example, an amplifier with an adjustable gain factor. The circuit provides near-optimal reception of diversity signals, but is characterized by increased complexity.

More simple to build are devices that provide a choice by any criterion of one of the separated channels.

The known channel selection devices with a maximum transmission coefficient. The device generally has a channel gain measurement circuit and a channel selection circuit with a maximum gear ratio. Auto selection devices are different.

the simplicity of the circuit implementation and with a small number of channels provide reception noise immunity, close to the noise immunity of the optimal complexing schemes. However, in such

devices, when selecting one channel, the energy of signals applied through other channels is not taken into account, which leads to an energy primer compared to the optimal addition, and with the number of channels increasing

and energy loss.

If used to maintain simultaneous operation of the transmitting and receiving communications equipment in the transmission systems of discrete information of the synchronization signals, resampling devices can be simplified, and the necessary information about the state of the communication channel can be obtained from the synchronization signal extraction unit (synchronization unit) coefficients to enter discrete. When performing diversity reception, the signal of the reception of synchronization signals in such a device is used to connect to the adder those channels on which the signal is received.

sync.

A significant disadvantage of such a device is that in a number of cases (the case of reception with a zero zone, the spaced reception of signals of amplitude telegraphy)

does not provide the same thing

false positives with a change in the number of channels to be summed. An increase in the number of channels being added also increases the noise level at the output of the adder, which, with a constant response threshold of the resolver, can increase the likelihood of false alarms, i.e., the presence of the information signal is fixed, whereas in fact the input of the threshold device only noise stress.

The purpose of the invention is to provide a constant level of false alarm during the subsequent signal processing.

This is achieved by the fact that a controlled voltage divider is connected to the output of the adder, the control inputs of which are connected via the decoder of the number of connected channels to the control inputs of the keys of the weighting processing channels.

The drawing shows a block diagram of a device of discrete-weight addition of separated signals at reception with zero zone for three reception channels.

The device contains synchronization blocks 1, information signal reception blocks 2, controllable keys 3, triggers 4, key state control, channel signal adder 5, time delay devices 6, collecting circuit 7, decoder 8, channel decision circuit 9 reception without a zero zone, the erase signal generator 10, the descrambler AND the state of triggers and the controlled divider 22.

Blocks 1 and 2, keys 3, triggers 4 and time delay devices 6 form three channels 13–15 of receiving diversity signals.

The information signals allocated by the receiving units are fed to the inputs of the controllable keys 3. The state of the keys depends on the control potentials coming from the right shoulders of the flip-flops 4. In the case of the permissive potential at the output of the trigger, the key controlled by it is set to the resolution , and the information signal from the output of the reception unit 2 through the key 3 without change is fed to the corresponding input of the adder 5. The key does not affect the shape of the transmitted signal and works essentially as a controlled divider, the coefficient Transferring is either '1, in the case of the presence at the output of flip-flop 4 resolving capacity, or "O, if the potential for prohibiting the output of the flip-flop.

Thus, if the Prohibiting potential occurs at the output of the trigger, the output of the corresponding block of the reference signal of the information signal is disconnected from the adder using key 3.

The state of the triggers depends on the impulse signals arriving at their inputs from the devices 6, the time delay of the synchronization signals, or from the output of the collecting circuit 7, which implements the logical operation "OR.

Blocks 1 demodulate a code combination that represents a synchronization signal and generates a single pulse (a signal that a synchronization signal has been received) that coincides in time with the leading edge of the first elementary signal of the information signal. This pulse is used in single and diversity reception systems to trigger a clock.

generator decoding device and regenerator.

The pulses from the output of the synchronization units 1 are fed to the collecting circuit 7, from the output of which any of the pulses fed to the input of the circuit 7 sets all the triggers 4 to the state "O", at which the inhibitory potential is formed at their output. The same pulses from the output of the synchronization blocks through the time delay devices 6 arrive at the PA inputs of the right shoulders of the triggers, setting them to the state "1", at which the permitting potential flows to the control inputs of the keys 3. The time delay devices 6 delay the pulse signals generated at the output of the synchronization blocks by a time slightly longer than the maximum possible shift in the time of occurrence of the signals at the output of the synchronization blocks, which can

take place due to the non-identical channels and transmission and reception paths of the clock signals.

Iri the presence of such a time shift the first pulse signal generated on

the output of the synchronization blocks, through the collecting circuit 7, sets all the triggers 4 to a state in which the outputs of the information signal reception blocks of all three channels will be disconnected from the adder by keys 3.

Assume that only two channels 13 and 16 receive reception and a pulse signal that a synchronization signal is received is formed at the output of block 1 of channel 15 through a time equal to TI after generating a similar signal at the output of block 1 of channel 13. Then the pulse signal of channel 13 through the collective circuit 7, all triggers 4 will be set to the state “O, and the same signal

delayed in the time delay circuit at time T2 greater than TI, the trigger 4 of channel 13 will be set to state "1, thereby ensuring the passage of the information signal of channel 13 through the key to the adder.

Similarly, a pulse signal from the output of block 1 of channel 15 through a time delay device with the same delay time equal to T2 will set the trigger to the state "1, providing a connection to the output adder

the block of receiving information signals of channel 15. At the same time, the trigger of channel 14, according to which the synchronization signal was not received, remains in the state "O", and the output of the block of reception of information signals is disconnected from the sum of aggregate