GB2059224A - Data transmission; compensating for inter-symbol interference - Google Patents

Data transmission; compensating for inter-symbol interference Download PDF

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Publication number
GB2059224A
GB2059224A GB8023279A GB8023279A GB2059224A GB 2059224 A GB2059224 A GB 2059224A GB 8023279 A GB8023279 A GB 8023279A GB 8023279 A GB8023279 A GB 8023279A GB 2059224 A GB2059224 A GB 2059224A
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United Kingdom
Prior art keywords
threshold
data receiver
bit
output
data
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Granted
Application number
GB8023279A
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GB2059224B (en
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General Electric Co PLC
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General Electric Co PLC
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Priority to GB8023279A priority Critical patent/GB2059224B/en
Publication of GB2059224A publication Critical patent/GB2059224A/en
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Publication of GB2059224B publication Critical patent/GB2059224B/en
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/065—Binary decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/063—Setting decision thresholds using feedback techniques only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems

Abstract

Compensation for inter-symbol interference in a digital data transmission system includes a plurality of threshold detectors 10-13 each having a respective different threshold level to determine whether the received bit has a value of '0' or '1'. Circuit means 5 responsive to one or more previously received data bits stored in 14 and/or one or more cross talk interferers selects which one of the threshold detectors is used to determine the current bit. Each detector may be associated with a sampling circuit 9. <IMAGE>

Description

SPECIFICATION Data transmission systems This invention relates to data transmission systems and more particularly to such systems transmitting digital (e.g. binary) data.
In a known binary data transmission system interference between consecutive symbols or bits of the received data is counteracted by adding a predetermined voltage to or subtracting a predetermined voltage from an incoming signal in dependance on the previously received bit, before applying the incoming signal to a threshold detector which is used to determine whether the received bit has a value of '0' or '1'.
Inter-symbol interference may for example be due to filtering of the signal, with narrower band width filters tending to introduce greater inter-symbol interference. The maximum permissible intersymbol interference level therefore determines for any particular system the maximum bit rate, and/or narrowest band width filter which may be used. If improved inter-symbol interference compensation can be provided then higher bit rates and/or narrower band filters may be employed.
It is an object of the present invention to provide an improved system for compensating for intersymbol interference.
According to one aspect of the present invention a data receiver comprises a plurality of threshold detectors each having a respective different threshold level and each arranged to provide an output when the level of a received signal exceeds the respective threshold level and means to select which of said plurality of threshold detectors is to be used in deciding the value of a data bit in dependance upon the value of at least one previously received data bit, the selection by said means serving to reduce the effect of inter-symbol interference.
Preferably each of said threshold detectors has a respective associated sampling circuit arranged to sample the output of the threshold detector at intervals corresponding to the period of each bit and substantially at the mid point of each data bit. The sampling circuit may be arranged to provide an output corresponding to the output of its respective threshold detector at the time of sampling, and to maintain that output until a subsequent sample is taken.
If the number of previously received data bits to be compensated for is n then the number of threshold detectors required to be provided for complete compensation is given by 2".
Where n is greater than one then the output of the multiplexer may be connected to a store of the shift register type, outputs of which may then be fed back to respectively address inputs of the means to select a particular threshold detector.
If the incoming signal is affected by locally identifiable interference (e.g. cross talk from an adjacent data transmitter or cross talk from a distant transmitter identified by another local receiver) one or more of the address inputs of the selection means may be connected to an output of the apparatus causing or identifying the interference so that the selected threshold detector is the one set to make the required decision in the presence of such interference.
According to another aspect of the present invention a data receiver comprises a magnitude comparator and means responsive to a plurality of previously received data bits to provide a threshold with which an incoming signal is compared, the threshold level being selected by said means serving to reduce the effect of inter-symbol interference.
Preferably the incoming signal is converted to digital levels by an analogue to digital converter and a digital magnitude comparator is used.
The threshold provision means may also be responsive to one or more cross talk interferers (such as adjacent digital transmitters) in addition to or instead of any or all of the previously received data bits.
The plurality of previously received data bits may be held in a store of the shift register type the outputs of which may be converted to digital levels by the threshold provision means before being compared by the digital magnitude comparator.
Data receivers in accordance with the present invention will now be described by way of example with reference to the accompanying drawings of which Figure 1 is a block diagram of a known data receiver, Figure 2 is a block diagram of a data receiver arranged to compensate for interference from a single previous bit, Figure 3 is a block diagram of a data receiver arranged to compensate for interference from two previous bits; and Figure 4 is a block diagram of a data receiver arranged to compensate for interference from a plurality of previous bits and locally generated cross talk.
Referring first to Figure 1 a known data receiver comprises a threshold detector 1 which produces, say, a binary 'one' output when the signal at its input exceeds a predetermined level, a sample and hold circuit 2 arranged to sample the output of the threshold detector 1 at the mid-bit time of incoming data, a variable feedback circuit (shown in its simplest form as a resistor) 4, and an analogue adder 3.
A received input signal is fed by way of the adder 3 to the threshold detector 1. When the signal level exceeds the predetermined threshold, the threshold detector 1 presents, say, a binary 'one' at its output.
Otherwise a binary 'zero' will be present at the output. The sampling circuit 2 is arranged to sample the output of the threshold circuit at the bit rate of the incoming data and at the mid point of each bit.
The output of the sampling circuit 2 is then held at binary 'zero' or binary 'one' in accordance with the output of the threshold detector 1 at the time sampling was carried out. To compensate for interference on the input signal due to the previous bit, the feedback circuit 4 supplies a positive or negative signal, in dependance on the output of the sampling circuit 2, to be added to the incoming signal by the adder 3.
Referring now to Figure 2, the data receiver shown may be used as a direct replacement for the circuit of Figure 1. The incoming signal is fed to two threshold detectors 7 and 8 one of which, say, 7 is set to require a higher signal to detect, say, binary 'one' than the other. Respective sampling circuits 9 are arranged to sample and hold the outputs of the threshold detectors 7 and 8, the outputs of the sampling circuits 9 being connected to a multiplexer 5. The multiplexer 5 selects in dependence upon the previous bit the respective signal from one of the sampling circuits 9 to be passed to the circuit output.
The selected signal is fed back to an address input 6 of the multiplexer 5 which uses this signal to determine which of the sampling circuits 9 is to provide the subsequent data bit. If, for example, the last received bit was a binary 'one' the multiplexer 5 enables the signal from the threshold detector 7 to pass to the output. Similarly if the last received bit was a binary 'zero' the multiplexer 5 enables the signal from the threshold detector 8 to pass to the output.
Referring now to Figure 3 a data receiver which acts in a similar manner to the circuit of Figure 2 may compensate for interference from two previous data bits. Four threshold detectors 10 to 13 have respective signal level thresholds, the multiplexer 5 selecting the output from one of them in dependance upon the last two received bits. The last two received bits are held in a store 14, which may be a shift register, and are fed back to address inputs 15 and 16.
The circuit output may be taken directly from the output of the multiplexer 5 to reduce delay to the output. One of the address inputs, say, may be connected to other apparatus (for example an adjacent data transmitter) which is known to be causing cross talk interference, the other input 16 then being connected to react to the previous data bit. In this case the output of the respective one of the threshold detectors 10-13 which best compensates for the effect of the cross talk and the previous data bit may then be selected by the multiplexer 5.
It will be readily seen that interference from any number of previous bits or cross talk interferers may be compensated for by using the system described above simply by expanding the number of threshold detectors. If the number of previous bits to be compensated for is added to the number of cross talk interferers to be compensated for and gives a total of n then a receiver of this kind requires 2n threshold detectors for complete compensation to be achieved.
Referring now to Figure 4 the 2n threshold detectors of Figures 2 and 3 are replaced by a digital magnitude comparator 20. An incoming analogue signal at the input 22 is converted to digital levels by an analogue to digital converter 21 the outputs of which are connected to inputs 50 to 56 of a digital - magnitude comparator 20. As each bit is received it is stepped through a shift register type store 23 the outputs of which are connected to inputs 40 to 45 of a conversion circuit 24 which provides digital signals to inputs 30 to 36 of the digital magnitude comparator 20. Cross talk interferers (for example adjacent data transmitters (not shown)) may also be connected to respective inputs 46 to 48 of the conversion circuit 24.
The conversion circuit 24 is arranged to combine the previously received bits held by the store 24 and the bits from the cross talk interferers and to convert these inputs to a digital level which is then forwarded to the digital magnitude comparator 20. The analogue to digital converter 21 converts the analogue input signal to a digital level which is similarly forwarded to respective inputs 50 to 56 of the digital magnitude comparator 20. If the digital signal at inputs 50 to 56 is greater than the digital signal at inputs 30 to 36 the digital magnitude comparator 20 presents, say, a binary 'one' signal at its output.
Otherwise a binary 'zero' signal will be present.

Claims (13)

CLAIMS 1. A data receiver comprising a plurality of threshold detectors each having a respective different threshold level and each arranged to provide an output when the level of a received signal exceeds the respective threshold level and means to select which of said plurality of threshold detectors is to be used to determine the value of a data bit in dependance upon the value of at least one previously received data bit, the selection by said means serving to reduce the effect of inter-symbol interference. 2. A data receiver as claimed in Claim 1 in which each of said threshold detectors has a respective associated sampling circuit arranged to sample the output of the threshold detector at intervals corresponding to the period of each bit and substantially at the mid point of each bit. 3. A data receiver as claimed in Claim 2 in which each sampling circuit is arranged to provide an output corresponding to the output of its respective threshold detector at the time of sampling and to maintain that output until the time of the next sampling. 4. A data receiver as claimed in any of Claims 1 to 3 in which each selected output is stored sequentially in a shift register. 5. A data receiver as claimed in any of Claims 1 to 4 in which at least one address input of the means to select is connected to an output of apparatus known to be affecting the received signal such that the selected threshold detector is the one set to compensate for the interference present. 6. A data receiver comprising a magnitude comparator and means responsive to a plurality of previously received data bits to provide a threshold level with which an incoming signal is compared by the magnitude comparator the threshold level being selected by said means serving to reduce the effect of inter-symbol interference. 7. A data receiver as claimed in Claim 6 in which the magnitude comparator is a digital magnitude comparator, the incoming signal is converted to digital levels by an analogue to digital convertor and the threshold level is provided in digital form. 8. A data receiver as claimed in Claim 6 or Claim 7 in which the means responsive to a plurality of previously received data bits is also connected to at least one other apparatus which is known to interfere with the incoming signal and said means to provide a threshold level is also responsive to the signals provided by said at least one other apparatus. 9. A data receiver as claimed in Claim 7 or Claim 8 in which each data bit as determined by the output of the digital magnitude comparator is held in a store of the shift register type the outputs of which are converted to digital levels by the threshold provision means to provide the threshold level for the next incoming bit. 10. A data receiver as claimed in Claim 9 in which the threshold provision means determines the digital level from a plurality of preceding bits, each bit contributing a respective predetermined positive or negative effect on the threshold level in dependance upon its position in the data stream relative to the next data bit to be received. 11. A data receiver substantially as herein before described with reference to Figure 3 of the accompanying drawings. 12. A data receiver substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings, New claims or amendments to claims filed on 7th January 1981 Superseded claims 1 to 12 New or amended claims:
1. A data receiver comprising threshold detection means having a plurality of different threshold levels selectable by means to provide an output from the detection means when the level of a received signal exceeds the selected threshold level, and said selection means selects the threshold level to be used to determine the value of a data bit in dependance upon the value of at least one previously received data bit, the selection by said selection means serving to reduce the effect of inter-symbol interference.
2. A data receiver as claimed in Claim 1 in which said threshold detection means is a plurality of threshold detectors each having a respective different threshold level and each arranged to provide an output when the level of a received signal exceeds the respective threshold level, and the selection means selects which of said plurality of threshold detectors is to be used to determine the value of a bit in dependance upon the value of at least one previously received data bit.
3. A data receiver as claimed in Claim 2 in which each of said threshold detectors has a respective associated sampling circuit arranged to sample the output of the threshold detector at intervals corresponding to the period of each bit and substantially at the mid point of each bit.
4. A data receiver as claimed in Claim 3 in which each sampling circuit is arranged to provide an output corresponding to the output of its respective threshold detector at the time of sampling and to maintain that output until the time of the next sampling.
5. A data receiver as claimed in any one of Claims 1 to 4 in which each selected ouptut is stored sequentially in a shift register.
6. A data receiver as claimed in any of Claims 1 to 5 in which at least one address input of the means to select is connected to an output of apparatus known to be affecting the received signal such that the selected threshold detector is the one set to compensate for the interference present.
7. A data receiver as claimed in Claim 1 in which said threshold detection means is a magnitude comparator, and the selection means is arranged to provide a threshold level in dependance upon the value of at least one previously received data bit with which an incoming signal is compared by the magnitude comparator.
8. A data receiver as claimed in Claim 7 in which the magnitude comparator is a digital magnitude comparator, the incoming signal is converted to digital levels by and analogue to digital convertor and the threshold level is provided in digital form.
9. A data receiver as claimed in Claim 7 or Claim 8 in which the means responsive to at least one previously received data bit is also connected to at least one other apparatus which is known to interfere with the incoming signal and said means to provide a threshold level is also responsive to the signals provided by said at least one other apparatus.
10. A data receiver as claimed in Claim 8 or Claim 9 in which each data bit as determined by the output of the digital magnitude comparator is held in a store of the shift register type the outputs of which are converted to digital levels by the threshold provision means to provide the threshold level for the next incoming bit.
11. A data receiver as claimed in Claim 10 in which the threshold provision means determines the digital level from a plurality of preceding bits, each bit contributing a respective predetermined positive or negative effect on the threshold level in dependance upon its position in the data stream relative to the next data bit to be received.
12. A data receiver substantially as herein before described with reference to Figure 3 of the accompanying drawings.
13. A data receiver substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.
GB8023279A 1979-07-16 1980-07-16 Data transmission compensating for intersymbol interference Expired GB2059224B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8023279A GB2059224B (en) 1979-07-16 1980-07-16 Data transmission compensating for intersymbol interference

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB7924632 1979-07-16
GB8023279A GB2059224B (en) 1979-07-16 1980-07-16 Data transmission compensating for intersymbol interference

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GB2059224A true GB2059224A (en) 1981-04-15
GB2059224B GB2059224B (en) 1983-08-03

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113082A2 (en) * 1982-12-24 1984-07-11 Fuji Electric Co. Ltd. Optical signal receiving apparatus
US4514854A (en) * 1982-02-24 1985-04-30 Hitachi, Ltd. Discrimination circuit for received data
EP0455910A2 (en) * 1990-05-11 1991-11-13 AT&T Corp. Distortion compensation by adaptively setting a decision threshold, for fibre optic systems
US5410556A (en) * 1993-10-29 1995-04-25 Ampex Corporation Pipelined viterbi decoder

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514854A (en) * 1982-02-24 1985-04-30 Hitachi, Ltd. Discrimination circuit for received data
EP0113082A2 (en) * 1982-12-24 1984-07-11 Fuji Electric Co. Ltd. Optical signal receiving apparatus
EP0113082A3 (en) * 1982-12-24 1987-07-01 Fuji Electric Co. Ltd. Optical signal receiving apparatus
EP0455910A2 (en) * 1990-05-11 1991-11-13 AT&T Corp. Distortion compensation by adaptively setting a decision threshold, for fibre optic systems
EP0455910A3 (en) * 1990-05-11 1992-12-09 American Telephone And Telegraph Company Distortion compensation by adaptively setting a decision threshold, for fibre optic systems
US5410556A (en) * 1993-10-29 1995-04-25 Ampex Corporation Pipelined viterbi decoder
WO1995012249A1 (en) * 1993-10-29 1995-05-04 Ampex Corporation Pipelined viterbi recorder

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Publication number Publication date
GB2059224B (en) 1983-08-03

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19960716