RU2254679C1 - Coherent receiver of modulated signals with a shift of multi-channel communication system (oqpsk) with code separation of channels - Google Patents

Abstract

FIELD: transmission of information, applicable in cellular and satellite communication systems.

SUBSTANCE: the receiver has two frequency converters, two quadrature correlators, phase error filter, controlled oscillator, two control elements, error delay filter, controlled clock oscillator, reference signal generator, two multipliers, two analog-to-digital converter, delay line, demodulator, decoder, two matched filters, phase shifter.

EFFECT: enhanced power efficiency of the communication system.

2 cl, 3 dwg

Description

The invention relates to the field of information transmission by means of electromagnetic waves and can be used in cellular and satellite communications systems, telemetry, in radio control systems and fiber-optic information transmission systems.

Known cellular communication systems with time-division multiplexing, using the so-called preambles for channel synchronization (part of the time interval in the channel, used to transmit clock signals) [1]. However, these systems have the following disadvantages:

1. Low energy efficiency, since to ensure reliable synchronization, it is necessary to allocate up to 40% of the channel energy for transmitting clock signals.

2. Low temporal efficiency of using the channel, since up to 40% of the time interval allotted for the transmission of each transmission of information is used to transmit clock signals.

3. When using systems of this type, it is not always possible to meet environmental safety requirements, since significant energy costs, which are necessary to ensure reliable synchronization of the system, lead to high spectral power density in the coverage area of the communication system and, as a result, to violation of environmental requirements security.

Also known are code division multiple communication cellular communication systems that use pilot signal [2] and [3] to synchronize receivers.

Their distinctive feature is that the pilot signal, which is used to synchronize the receivers of the system, is transmitted simultaneously with the information. However, in these systems, the use of a pilot signal also requires additional energy costs, which, if necessary, to ensure reliable synchronization of the system, can account for up to 30% of the energy allocated for transmitting information, which also leads to a high spectral power density in the coverage area of the communication system and, as a result - to violation of environmental safety requirements.

Closest to the proposed invention is a pseudo-random signal receiver [3], comprising a series-connected first frequency converter (IF), the first input of which is a receiver input, a first intermediate-frequency filter (PLL), a second PLL, a first multiplier (P), a phase detector ( PD), phase error filter (PFD), the first control element (UE), a controlled generator (UG), the output of which is connected to the second input of the first GGH, the second P connected in series, the first input of which is connected to the output of the first th phase filter, third phase converter, first adder (C), second frequency converter, second C, delay error filter (FDF), second UE, controlled clock (UTG), reference signal generator (GOS), the first output of which is connected to the second input the first P connected in series to the third P, the first input of which is connected to the output of the first PLL, the fourth PLL, the output of which is connected to the second input of the first C, as well as a reference generator (OG), the first output of which is connected to the second input of the PD, and its second output through a phase shifter (PV) is connected to the second input second st IF FFO via an amplifier output (DC) connected to the second input of the second C, CRP second output connected to the second input of the second P and its third output connected to the second input of the third P.

The aim of the present invention is to provide a coherent receiver of quadrature modulated signals with an offset (OQPSK), which would ensure high energy efficiency of the communication system with code division multiplexing by using all the radiated power only for information transfer, and would also provide environmental safety requirements for the operation of the system communication by reducing the spectral power density of the emitted signals while ensuring high reliability of synchronization systems .

This goal is achieved by the fact that in the known receiver of pseudo-random signals, including a series-connected first IF, the first input of which is the input of the receiver, the first phase-converter, second phase-converter, the first П, ФД, ФФО, the first УЭ, УГ, the output of which is connected to the second input of the first IF, serially connected to the second P, the first input of which is connected to the output of the first PLL, the third PLL, the first C, the second IF, the second C, FOZ, the second UE, UTG, GOS, the first output of which is connected to the second input of the first P, the third are connected in series P, p the first input of which is connected to the output of the first PLL, the fourth PLL, the output of which is connected to the second input of the first C, as well as the exhaust gas, the first output of which is connected to the second input of the PD, and its second output through the PV is connected to the second input of the second GP, the output of the PFD through The DC is connected to the second input of the second C, the second GOS output is connected to the second input of the second P, and its third output is connected to the second input of the third P, the first, second, third and fourth phase-phase converters, the third multiplier, the phase detector, and the reference oscillator are excluded first and second with matrices, amplifier, and the connection between the GOS and the second P is broken and new elements and connections between the elements are additionally introduced, namely: a first matched filter (SF) connected in series, the input of which is connected to the output of the first frequency converter, the first analog-to-digital converter (ADC) , the first quadrature correlator (KK), a demodulator (DM) and a decoder (D), the output of which is the output of the receiver, the second output of the first KK is connected to the input of the FFD, the output of the UG is connected to the input of the PV, the second input of the second IF is connected to the input of the receiver and its output through a series-connected second SF, second ADC and delay line (LZ) is connected to the second input of the first KK, the GOS output is connected to the third input of the first KK, the output of the first ADC is connected to the first input of the second KK, the output of the LZ is connected to the second input the second KK, the output of the UTG is connected to the second input of the first P, the output of which is connected to the third input of the second KK, the output of the second KK is connected to the input of the second P, the output of which, in turn, is connected to the input of the PhD, the second input of the second P is connected to the first output first QC.

Distinctive features of the proposed device are additional elements introduced into the receiver circuit, namely: the first and second SF, the first and second ADCs, the first and second KK, LZ, DM, D and the corresponding connections between them, which helps to increase energy efficiency due to the use of all radiated power only for information transfer, as well as the fulfillment of environmental safety requirements during the operation of a communication system by reducing the spectral power density of radiated signals when while ensuring high reliability of system synchronization, which meets the criterion of "novelty."

Since the totality of the introduced elements and their relationship to the filing date of the application in the patent and scientific literature are not found, the proposed technical solution corresponds to the "inventive step".

The structural diagram of the device shown in figures 1 and 2. The numbers in figure 1 denote:

1 - phase shifter on π / 2 (PV);

2 - controlled generator (UG);

3, 18 - control element (UE);

4 - phase error filter (FFO);

5, 11- frequency converter (IF);

6, 12 - matched filter (SF);

7, 13 - analog-to-digital Converter (ADC);

8, 15 - quadrature correlator (QC);

9 - demodulator (DM);

10 - decoder (D);

14 - delay line (LZ);

16, 19 - multiplier (P);

17 - delay error filter (FDF);

20 - reference signal generator (GOS);

21 - controlled clock generator (UTG);

In the figure, 2 numbers indicate:

1, 3, 6 - multiplier (P);

2, 5 - digital adder (CA);

4 - inverter (I).

Receiver operation

The operation of the receiver will consider the structural diagram, which is shown in figure 1, and provided that the receiver is in a state of capture of the received signal. The capture was carried out by the initial synchronization device, which is not considered in the claimed device.

Suppose the receiver input at time t _k receives the signal type

where S _I (t _k ) is the in-phase component of the signal;

S _Q (t _k ) is the quadrature component of the signal.

In turn,

where A _m is the signal amplitude;

r _i is the i-th information symbol taking the value 1 or -1;

- j-й элемент кодовой последовательности, принимающий значение 1 или -1;

- the j-th element of the code sequence, taking the value 1 or -1;

ω _s is the circular frequency of the received signal;

φ is the initial phase of the carrier;

n _I (t _k ), n _Q (t _k ) - in-phase and quadrature components of normal white noise with a power spectral density of N _0/2 ;

T is the duration of the code sequence element.

At the same time, signals of the form are sent to the second input of the first GCC (5) directly and to the first input of the second inverter (11) through the PV to π / 2 (1) from the output of the UG (2):

where ω ₀ is the circular reference frequency of the controlled generator, and ω ₀ ≈ω _c .

Then the signals at the first inputs of the first and second KK (8) and (15) after conversion in the first IF (5), filtering in the first SF (6) and transformations in the first ADC (7) have the form

and the signals at their second inputs after conversion in the second GTP (11), filtering in the second SF (12), conversions in the second ADC (13) and delay by a half-cycle (T / 2) in LZ (14) have the form

Where

Δω is the frequency difference between the received and reference signals.

The third code input KC (8) from the output of the GOS (20) receives the reference code sequence of pseudo-random symbols d _j identical and coinciding in time (within the duration of the element of the code sequence T) with the code sequence d _j contained in the received signal S (t _k ), and the third code input KK (15) from the output P (19) receives the reference code sequence d _j . This sequence is formed in P (19) by adding the signals arriving at its inputs from the output of the GOS (20) and the output of the UTG (21) and coincides in phase with the sequence supplied to the third input of the QC (8).

After processing the received and reference signals in the CC (8), at its first output, a signal appears corresponding to the transmitted binary information sequence r _i , which is supplied to the demodulator (9), and after decoding in the decoder (10), in which error correction and correction takes place , information symbols arrive at the output of the receiver.

At the second output of the spacecraft (8), a signal appears that is proportional to the phase difference of the carrier frequency of the received signal ω _s and the frequency ω ₀ UG (2). This signal through FFO (4) enters the RE (3), which, acting on the UG (2), adjusts its reference frequency ω ₀ to the carrier frequency of the received signal ω _c .

At the first output of the spacecraft (15), a signal appears containing information about the size of the mismatch between the received and reference signals with respect to the time delay. In addition, this signal is modulated by information sequence symbols. In the multiplier (16), the information component is removed and a signal appears at its output, containing only the error in the delay of the received and reference signals and the noise component. The error signal for the delay after filtering in the FDF (17) acts on the control element (18), which changes the clock frequency of the UTG (21) in such a way as to compensate for the mismatch in the delay of the received code sequence and the reference formed by the GOS (20).

The work of the spacecraft (8) and (15) we will consider according to the scheme shown in figure 2, in two modes: in the mode of receiving information and tracking the phase of the received signal and in the mode of generating the signal error tracking the delay.

CC operation in the mode of receiving information and tracking the phase of the received signal (CC operates in this mode (8)). When the QC is in this mode, a signal of the form (4) is supplied to the first input P (1) (it is the first QC input), and a reference code sequence d _j , which is identical to the code sequence, is supplied to its second input (aka the third QC input) contained in the signal (4), and coincides with it in delay with accuracy determined by the operation of the delay tracking circuit, but not exceeding a value equal to half the duration of the code sequence element.

A signal of the form (5) is supplied to the first input P (3) (aka the second QC input), and a reference code sequence d _j that is identical to the code sequence contained in the signal (5) is supplied to its second input (aka the third QC input) ), and coincides with it in delay with accuracy determined by the operation of the delay tracking circuit, but not exceeding a value equal to half the duration of the code sequence element.

In multipliers (1) and (3), the convolution of input and reference signals is carried out. The result of the convolution from the output P (1) is fed to the first inputs of the DS (2) and the DS (5), and the result of the convolution from the output P (3) is sent to the second input of the DS (2) and through And (4) to the second input of the DS ( 5). Since the DS (2) performs the function of addition, a signal of the form

The first term in this expression (with fairly accurate synchronization [cos (x _k ) ≈1]) is an information symbol, and the subsequent terms are noise. The signal from the output of the CA (2) is fed to the first output of the QC and to the second input P (6).

At the output of the DS (5), which together with the inverter (4) implements the subtraction function, a signal of the form

whose value is mainly determined by the sine component in expressions (4) and (5), since the cosine component at the output of the CS (5) is compensated. This signal is fed to the first input P (6).

P (6) performs the function of an adder modulo two. This leads to the fact that at its output there is no information component r _i . Indeed, multiplying expressions (6) and (7) we obtain

For small detunings in phase of the carrier frequency of the received ω _s and the frequency of the reference signals ω _{0, the} value sin (2x _k ) ≈2φ, i.e. the signal at output P (6) (at the second output of the QC) is proportional to the phase synchronization error, which is further processed by the synchronization system.

The operation of the QC in the tracking mode of the delay (in this mode, the QC works (15) and acts as a discriminator of the signal delay).

A distinctive feature of the operation of the QC in this mode is that the second inputs P (1) and (3), which are simultaneously the input 3 of the QC, are supplied from the output P (19) with a reference code sequence identical to the code sequence contained in the signals supplied at the first inputs P (1) and P (3) and UTG modulated by pulses of the clock frequency (21). Subsequently, the signals from the outputs P (1) and (3) are subjected to the same processing as in the case described above. At the output of the digital signature (2), a signal appears that contains a delay error signal and an information component that is undesirable for this mode of operation of the QC, which is subsequently compensated in P (16).

If the received signal has a delay relative to the reference signal taken from the output P (19) by the value of τ, then expressions (4) and (5) can be represented as follows:

where d _j [t _k -τ] is the symbol of the jth element of the code sequence of the received signal, delayed in time by the value of τ.

The symbol of the jth element of the reference code sequence supplied to the third input of the QC (15) consists of two different-polarity gates of duration T / 2 each and at the k-th moment of time can be represented as

where δ [·] is a half-gate.

Figure 3 shows the relative position of jx elements of the received d _{j inf} and the reference d _{j reference} code sequences at the k-th point in time.

From Figure 3, that the overlap area S _per strobe δ _j 'with the element of the code sequence of the received signal d _j [t _k -τ] is equal to (T / 2-τ), and the overlapping area of the gate δ _j' 'with the same element the code sequence of the received signal is equal to (-T / 2), i.e. there is a complete overlap of this strobe with an informational message.

The resulting overlap of the element of the reference signal by the element of the code sequence of the received signal S _perΣ is equal to the sum of the areas of overlap of the gates δ ' _j and δ'' _j and is equal to (-τ).

The signal at the output of the DS (2) is proportional to the value of S _perΣ .

From the above it follows that when the QC is in the delay tracking mode, it really acts as a discriminator of the delay of the received signal, and its second output is not used.

Let us evaluate the performance of the claimed device by the value of the s / w ratio at the output of the information channel, as well as in the channels for tracking the phase of the carrier frequency and the delay of the received signal. Since the signals at the outputs of the above-mentioned channels are random and ergodic, the s / w ratio at the output of the information channel can be obtained by time averaging of expression (6).

The mathematical expectation of the signal level, its dispersion and the s / w ratio at the first output of the QC (8) (information channel) are of the form

where P _c is the signal power;

R _W - noise power.

From the obtained expressions it follows that in the information channel the potential value of the s / n ratio is achieved, corresponding to the coherent (optimal) signal reception.

The statistical characteristics of the signal at the input of the synchronization channel behind the carrier (second QC output (8)), as follows from expression (8), have the following meanings:

при x→0;the average error is

as x → 0;

;error variance -

;

signal-to-noise ratio - s / w = 2P _s / P _w

From the analysis of the expressions it is seen that the value of the s / n ratio in the synchronization channel behind the carrier corresponds to the coherent synchronization channel.

The efficiency of the delay tracking channel is determined by the value of the error signal for the delay at the output P (16). As follows from figure 3, the resulting value of the error signal for the delay at τ = 0 is zero.

The estimate of the s / w ratio at the input of the tracking channel for the delay unambiguously follows from the obtained estimate of the s / w in the information channel when the delay tuning is performed by the value τ = T / 2. In this case, the signal energy at the channel input will decrease by exactly half. Thus, the signal-to-noise ratio at the input of the delay tracking channel can be estimated by the following expression

c / w = E / N ₀ ,

where E is the signal energy. Obviously, E = P _with T.

It follows from the foregoing that, at a fixed (set) emitted transmitter power that meets environmental safety requirements (level of power spectral density), the proposed device has potential noise immunity without additional energy to ensure synchronization of the communication system, allows you to implement a large service area while ensuring reliable synchronization of the system communication.

Thus, the proposed device has clear advantages compared with the prototype.

Technical implementation of digital adders (option) can be performed on the chip 7483, a diagram of which is presented in [4].

Sources of information

1. New standards for broadband radio communication based on W-CDMA technology: M .: International Center for Scientific and Technical Information, 1999. (Fig. 4.25, p.89, p.90).

2. In the same place (Fig. 3.11, p. 56).

3. Aces G.I. Statistical theory of the reception of complex signals: M., Soviet Radio, 1977 (Fig. 4.20, p.213) (prototype).

4. Application of integrated circuits: a practical guide. In 2 kn. Prince 2. Trans. from English / Ed. A. Williams. - M .: Mir, 1987 (Fig. 8.33, p. 51).

Claims (2)

1. A coherent receiver of quadrature modulated signals with an offset multichannel communication system with code division multiplexing, which includes the first frequency converter, the input of which is the receiver input, a phase error filter connected in series, the first control element, a controlled generator, the output of which is connected to the second the input of the first frequency converter, a delay error filter connected in series, a second control element, a controlled clock generator, an oppo generator signals, the first multiplier, a series-connected phase shifter and a second frequency converter, as well as a second multiplier, characterized in that it additionally includes a first matched filter, the input of which is connected to the output of the first frequency converter, the first analog-to-digital converter, the first quadrature correlator, demodulator, decoder, the output of which is the output of the receiver, the second matched filter, the input of which is connected in series the output of the second frequency converter, the second analog-to-digital converter, a delay line whose output is connected to the second input of the first quadrature correlator, the second quadrature correlator, the first input of which is connected to the output of the first analog-to-digital converter, and its second input is connected to the output of the delay line, the output of the first multiplier is connected to the third input of the second quadrature correlator, and the output of the reference signal generator is connected to the third input of the first quadrature correlator, w output The fourth quadrature correlator is connected to the input of the second multiplier, the second input of the second multiplier is connected to the first output of the first quadrature correlator, the second output of the first quadrature correlator is connected to the phase error filter input, the output of the controlled clock is connected to the second input of the first multiplier, the second input of the second frequency converter is connected with the input of the receiver, the output of the controlled generator is connected to the input of the phase shifter, and the input of the error filter for the delay is connected to the output of second multiplier. 2. The coherent receiver according to claim 1, characterized in that each of said quadrature correlators includes a first multiplier connected in series, the first input of which is the first input of the quadrature correlator, the first digital adder, the output of which is the first output of the quadrature correlator, and also connected in series with the second a multiplier, the first input of which is the second input of the quadrature correlator, an inverter, a second digital adder, a third multiplier, the output of which is second by the quadrature correlator output, the second input of the third multiplier is connected to the output of the first digital adder, the output of the first multiplier is connected to the second input of the second digital adder, and the output of the second multiplier is connected to the second input of the first digital adder, while the second inputs of the first and second multipliers are simultaneously the third the input of the corresponding quadrature correlator.

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