SU1345361A1 - Transceiver of multiposition broad bandwidth signals - Google Patents

Abstract

Invention m. used in multipath lines of the tropospheric, ionospheric, and other communications in the transmission of discrete messages. In order to increase noise immunity, a serially connected absolute code converter into a relative and phase manipulator is introduced at the transmitting side, and a relative code into absolute converter at the receiving side. In subclauses 2 and 3, the f-crystals are respectively given the device of the reference signal generation unit and the decision block. 2 hp f-ly, 1 tab., 8 ill. SP OS O5

Description

The invention relates to multichannel radio communication systems and is intended for use in multipath lines of tropospheric, ionospheric, and other communications in the transmission of discrete messages.

The purpose of the invention is higher noise immunity.

Figure 1 shows the structural electrical circuit of the transmitting part of the device proposed for transmitting and receiving multi-position broadband signals; Fig. 2 shows the structural electrical circuit of the receiving part of the device for transmitting and receiving multi-position wideband signals; FIG. 3 shows a structural electrical circuit of a signal conversion unit; Fig. 4 is a structural electrical circuit of a decision block; Fig. 3 shows the structural electrical circuit of the block for determining the maximum signal; Fig.6-8 - diagrams of the device.

A device for transmitting and receiving multi-position wideband signals contains on the transmitting side a 1 clock frequency selector, a 2 clock frequency divider, a signal conversion unit 3, N formers 4 multi-position broadband signals, an output adder 5, a phase manipulator 6, a radio transmitter 7, a converter 8 absolute code in relative. On the receiving side, the device contains a broadband receiver 9, N matched filters 10, N multipliers 11, N integrators 12, a decision block. 13, a signal converter 14, a sign multiplier 15, a reference signal generating unit 16 that contains N gating block 17, an adder 18, a multiplier 19, a comb filter 20 and N delay lines 21, N gate voltage formers 22, a relative code converter 23 absolute, element 24, synchronization block 25. The signal converting unit 3 contains AND elements 26, a decoder 27, additional pulse formers 28, OR elements 29, a sign impulse generator 30, and a forward register 31. Decider unit 13 contains a maximum signal determination unit 32, N first driver

33 pulses, N threshold blocks 34, N elements AND 35, element OR 36, the second driver 37 pulses, N blocks 38 extraction of absolute values of voltages. Block. The 32 maximum signal definitions contain N elements AND 39, N (N - 1) / 2 elements HE 40 and N (N - 1) / 2 comparators 4 1.

The device works as follows.

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The binary sequence (Fig. 2b) is fed to the third input of the signal conversion unit 3 and to the input of the 1 clock frequency selector, which forms short pulses with the following frequency f t, the duration of the binary information symbol (Fig. Bb). Clock pulses from the clock frequency selector 1 are fed to the second input of the signal conversion unit 3 and to the clock frequency divider 2, the output of which clock pulses with the following frequency f f .. (fig.bv) are fed to the first input of the signal conversion unit 3. Binary and the sequence of symbols in the signal conversion unit 3 is fed to a push register 31, the input of which is the input of the device. Under the action of clock pulses coming from the 1 clock frequency selector, the binary pulses are sequentially recorded in k bits of the forward register 31 (for the considered example, the implementation is k 3). After filling all the bits of the push register 31 using AND-26 elements controlled by pulses from the 2 clock divider, the k-bit code combination written into the push register 31 is read. Thus, using the push register 31 and additional pulse generator 28 splits the input binary sequence into source k-bit code patterns. The use of elements AND 26 allows the reading of a code combination written in the k-bits of the advance register 31 in the parallel code. The resulting k-bit code sequence in the parallel code from the outputs

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elements And 26 enters the k inputs of the decoder 27. In accordance with the input to the decoder

A double pulse of positive polarity appears on the combination of a double combination on one of its M 2 (M 2 3) outputs. Additional shapers 28 pulses numbered 1, 2,.,., M under the action of clock pulses from the splitter 2 clock frequency, generate a pulse of positive polarity and capacitance t, 31 (Fig.bg). Outputs additional shapers

28 pulses numbered 1, 2, 3, 4, corresponding to the code combinations 000, 001, 010, 011, are connected to the first inputs

(N М / 2 4) elements OR 29. The outputs of the remaining additional drivers 28 pulses numbered 5, 6,7 8, corresponding to the code combinations 100, 101, 110, 1111, are connected to the second inputs of the same elements OR 29 in the reverse order The outputs of the OR elements 29 are the outputs of the signal conversion unit 3.

When one of the outputs of the conversion unit 3 of a pulse signal of positive polarity (Fig.6e) with a duration of t3 in one of the formers 4 appears, a complex wideband signal of a given structure is created to transmit information about the k-bit code combination assigned by the unit 3 conversion of signals from the binary sequence transmitted to it. The signal conversion unit 3, using the most significant digit of the k-bit code combination, also determines the sign (plus 1 or minus O) with which the multiposition wideband signal is to be transmitted. For this purpose, the output of the high-order element 26 of the spinning register 31 is connected to the input of a imaging unit of 30 sign pulses, the output of which, in accordance with the polarity of the higher-order output of a k-bit code combination, is the formation of a pulse of duration t 2 Signal pulses are controlled by pulses.

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arriving at its second input from the 2 clock frequency divider. The output of the symbol maker 30 is a symbolic output of the signal conversion unit 3. The timing diagram of the pulses at the output of the imaging puller 30 is shown in FIG.

10 The multiposition wideband signals formed in the former 4 are combined by the output adder 5 and fed to the second input of the phase manipulator 6. In the phase 15 manipulator 6, the manipulation and the initial phase of the multiposition wideband signal in accordance with the binary sequence coming from the output of the converter 8 absolute code encoder relative to the first input of the phase manipulator 6. The time diagram of the pulses at the output of the absolute code converter 8 relative to 25 dstavlena on fig.bzh. From the output of the phase manipulator 6, the multi-position wideband signals are fed to the input of the radio transmitter 7. Thus, the radio transmitter 7 30 transmits the wide-band multi-position signals with relative phase modulation. Information about the transmitted code combination is embedded in the structure of the multi-position wideband signal and in its initial phase. The value of the initial phase of the signal is determined by the sign of the higher bit of the transmitted code combination and is measured according to 40 relative laws.

The table shows the correspondence of the code combinations to the structures of the transmitted multi-position wideband signals.

g The sequence of transmitted multi-position wideband signals in this example is symbolically shown in the timing diagram of fig.bz. The sign of the signal (its initial phase) is determined by the polarity of the binary pulse sequence received at the output of the absolute code converter 8 in the relative ratio 8, shown in FIG. At the receiving side of the signal after the wideband receiver 9, it is assigned to matched filters 10 that are consistent with the structure of the multiposition wideband signals.

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At the same time, the number of matched Integration limits of the set filters 10 is equal to N М / 2 - Аи and covered by the synchronization unit 25 connected at the input to the comb filter 20, and at the output - with the control inputs of the integrators 12 and subsequent processing devices

Determines the number of structures used multiposition wideband signals. As a result, responses (short radio pulses) appear at the outputs of matched filters 10, the initial phase of which can take the values O and 180 depending on the transmitted signal. The change of the initial phase in the sequences of received signals is carried out according to a relative law. In the receiving part of the device, coherent optimal reception of signals is carried out, for which the reference coherence oscillation is separated by summing the responses of matched filters 10 in adder 18 and clearing this amount of noise using a comb filter 20. To increase the efficiency of the comb filter 20, apply reverse b by decision with the pickup manipulation using delay lines 21 for the signal duration (T k), and blocks 17, multiplier 19, associated with the significant output of the decision block TK,

At the output of the adder 18, oscillations with a variable phase appear, which makes it impossible to operate the comb filter 20, which performs coherent accumulation of signals over many transmission cycles. In order to eliminate phase manipulation, control pulses of positive or negative polarity are fed to the second input of the multiplier 19 from the sign output of the decisive bhiuk 13. Thus, the manipulation is removed.

The noise-free reference coherent oscillations from the output of the comb filter 20 are supplied to the second inputs of the multipliers 11, the first inputs of which are connected to the outputs of matched filters 10. This performs synchronous coherent detection of the received signals. To combat fading, which are manifested in the scattering of responses at the output of matched filters 10 (multipath picture), signals from the outputs of multipliers 11 are sent to integrators 12, in which coherent accumulation of rays occurs.

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signals. The synchronization unit 25 generates a sync signal, which is a sequence of short pulses with a 1 / Tg following frequency. The moments of occurrence of short pulses correspond to the temporal boundaries of the received multi-point wideband signal. The specific implementation of synchronization unit 25 is determined by the structure of the used multi-point complex wideband signal. 20 Since the received broadband signals are manipulated in phase (Q.O or (180 °), different-field pulses appear at the outputs of the integrator 12. Time diagrams of voltages at the outputs of the integrators are shown in Fig. 7a, b. C of the outputs of the integrators 12 Signals arrive at the N inputs of the decision block 13. The inputs of the decision block 13 are the inputs N 4 of the blocks 38, which can be made according to the scheme of two half-period exponents.The signals of the positive polarity, the amplitude of the pulses, appear at the output of the blocks 38 this does not change (figv) Signals from the outputs of block 38 are fed to the inputs of block 32 for determining the maximum signal, in which the maximum amplitude of the signal is determined based on a comparison of the amplitude of the signal in each processing branch with the amplitudes of the signals in all other processing branches. x processing is carried out using comparators 41. Signals of a positive polarity but of varying amplitude are fed to the inputs of the comparators 41 .. In this example, the signal from the output of the block 38 s Number m 1 (the first from the processing branch) is fed to the first inputs of the comparators 41, forming the xGervish group (group number j 1), with numbers i 1, 2, 3. Signals from blocks 38 of the other processing branches with numbers are sent to the second inputs of the comparators 41 m 2, 3.4. At the same time, in the comparator 41 of the first group

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signals. The synchronization unit 25 generates a sync signal, which is a sequence of short pulses with a 1 / Tg following frequency. The moments of occurrence of short pulses correspond to the temporal boundaries of the received multi-point wideband signal. The specific implementation of synchronization unit 25 is determined by the structure of the used multi-point complex wideband signal. 0 Since the received broadband signals are manipulated in phase (Q.O or (180 °), different-field pulses appear at the outputs of integrator 12. Time diagrams of voltages at the outputs of the integrators are shown in Fig. 7a, b. C of the outputs of the integrators 12 Signals arrive at the N inputs of the decision block 13. The inputs of the decision block 13 are the inputs N 4 of the blocks 38, which can be made according to the scheme of two half-period exponents.The signals of the positive polarity, the amplitude of the pulses, appear at the output of the blocks 38 this does not change (Fig. 7b). The signals from the outputs of block 38 are fed to the inputs of block 32 for determining the maximum signal, in which the maximum amplitude of the signal is determined based on a comparison of the amplitude of the signal in each processing branch with the amplitudes of the signals in all other processing branches. processing is carried out using comparators 41. Signals of a positive polarity, but of different amplitude, are fed to the inputs of comparators 41 .. In this example, the signal from the output of the block 38 s O m m 1 (the first from the processing branch) goes to the first inputs of the comparators 41, forming the xGerv group (group number j 1), with numbers i 1, 2, 3. Signals from the blocks 38 of the other processing branches with numbers arrive at the second inputs of the comparators 41 m 2, 3.4. At the same time, in the comparator 41 of the first group

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Number i 1 compares the amplitudes of the first and fourth processing branches, in comparator 41, with the number of the first and third branches, with the number of the first and second branches. To implement such a comparison of signal amplitudes on the first processing branch with signals in the rest of the processing, it is necessary to have three comparators, i.e. N - 1 - comparator 41. For comparing the amplitude of the signal of the second branch with the amplitudes of the signals of the remaining processing branches

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Comparators 41 are used, which form the second group with the number j 2. The signal from block 38 with the number m 2 is fed to the first inputs of the comparators 41 of the second group (j 2). The second inputs of the Comparators 41 receive signals from the remaining blocks 38 with numbers m 3, 4. However, the signals in the first and second processing branches x have already been compared in the comparator 41 of the first group with the number. Consequently, there is no need to compare the signals of these processing branches in the second group of comparators 41, therefore their number in this group is one less and equal to two. In the third group of comparators 41, the signals of the third processing branch are compared with the signals of the other branches in a similar way. The number of comparators is 41 in this group. one less than the second and, therefore, two less than the first, because the signals of the third branch were compared with the signals of the first and the second processing branches in the previous first and second groups, respectively. At the same time, the number of comparators 41 in each group used to compare this particular processing branch with the others is one less than in the previous one and is generally determined by the formula k N - j, where N is the number of processing branches; j is the group number that matches the number of the processing branch being analyzed. ,

In the code of the comparators 41, a standard pulse appears, corresponding to 1 if the amplitude of the signal received at its first input is greater than the amplitude of the signal arriving at its second pulse.

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input, otherwise the output of the comparator 41 is O.

The signals from the outputs of the comparators 41 of each j-th group are fed to the inputs of the AND 39 elements with the numbers 1 j. Each of the elements And 39 has N 4 inputs and one output. The first inputs of all elements And 39 are connected to the output Q of the clock of the synchronization unit 25. Therefore, the elements And 39 receive resolution short pulses at times that are multiples of Tj. Consider the principle of operation of block 32 in relation to four special cases m.

The readout of the signal at (t 1) the first input of block 32 is maximum (i.e.

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output of comparators 41 first (j 1)

the groups are set to logical signals 1, and at the output of AND 39 with the number 1 1 (at the moment of arrival of the sync pulse at its first input) appears 1. At the same time, on all the other AND 39 elements with the numbers 1 2, 3, 4, 0 .

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of them, the outputs of the comparators of j 1 group are connected through the elements NOT 40.

The readout of the signal at (t 2) the second input of block 32 is maximum (i.e.

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 Vj, v v). On you

The comparators 41 of the SECOND group (j 2) are set to 1. At the output of the comparator 41 with the number of the first group (j 1) with O (since Vj v). Due to the fact that the output of this comparator is connected to the element AND 39. (1 2) through the element 40, the output of the element 39 (at the moment of arrival of the sync pulse at its first input) appears 1. At the same time, all the other elements 39 and 39 with .numbers 1 1,3 and 4) are closed.

The readout of the signal at (t 3) the third input of block 32 is maximum (ie, Vj V, Vj Vj, Vj7 V,). Comparator 41, which compares the third and fourth processing branches (tons 3 and 4), is connected directly to the inputs of the element 39 with the number 41, and the comparators 41, made a comparison of the processing branches of the first (square 1) with the third (III) and second (t 2) from the third (t 3), - through the elements NOT 40. Therefore, at the moment of the appearance of the sync pulse at the first input I 39 (m 3), 1 appears at its output. At the same time, all the other elements And 39 are closed .

+ 4 4 4 outlets. All comparators 41 with block 32 numbers are present

ABOUT . All these comparators (with numbers) are connected via the NOT 40 elements to the inputs of the AND 39 element. Therefore, at the time the sync block 32 arrives at the synchronization input, only the output of the AND 39 element from the JMepoM m 4 appears 1.

Thus, a short pulse appears at one of the inputs of block 32. The number of this output corresponds to the number of that branch, to the input of which a signal of maximum amplitude arrives. The synchronization of the elements AND 39 is ensured by the supply of short sync signals to their first inputs. Timing diagrams of signals at the outputs of block 32 for determining the maximum signal are shown in fig.7g.

From the outputs of the block 32, short pulses arrive at the inputs N 4 of the first shaper 33 pulses, which with the help of synchronization pulses (from synchronization unit 25) carry out the formation of pulses of positive polarity with 11d 3t. The first pulse shaper 33 can be implemented on RS-flip-flops. The outputs of the pulse shapers 33 are the outputs of the decision block 13, which determines which branch of the processing signal has the maximum amplitude. Timing diagrams of the signals at the outputs of the decision block 13 is shown in fig.7d. In addition, decision block 13 makes a decision about the sign of the reference signal with a maximum amplitude.

The signals arriving at the inputs of the decision block 13 are also fed to the inputs of the threshold blocks 34, for example, Schmitt triggers can be used. Depending on the signs of the voltages acting on the inputs of the threshold blocks 34, positive or negative voltages of the standard amplitude are set at its outputs. The signals from the outputs of the threshold blocks go to the first inputs of the And 35 elements, the second inputs of which receive signals from the corresponding outputs of the block 32. In this case, signals appear at the output of only that element 35, which belongs to the processing branch with the maximum amplitude of the signal and the polarity of the signal in which is positive. If the polarity of the signal received from the output of the threshold unit 34 is negative, the signal at the output of the element 35 is absent. The outputs of the AND 35 elements are combined with the OR element 36. The presence of a signal on the upper part of the OR element 36

5 indicate a positive.

the sign of the made decision by the block 13, and the absence - about the negative sign of the made decision. The second pulse shaper 37 is formed by generating positive and negative polarity pulses corresponding to a 1x signal at the sign output of the decision block 13. The synchronization of the second pulse shaper 37 is provided by synchronization pulses received by the synchronization input of the block

13 and the driver 37. The signal timing diagrams on. The sign output of the decision block 13 is shown in Fig. 8a.

From the N outputs of the decision block 13, the signals carrying information about which of the N branches of processing the maximum signal go to the inputs of the converter 14 of signals. At the output of the signal converter 14, in accordance with the number of its input, to which the signal from the clipping unit 13 arrives, a corresponding code pattern is formed. In this case, the output of the converter

By the signals, one of the first four code combinations listed in the table is generated. The kind of code combination is determined by the structure of the received multiband wideband signal. The n6 signal converter 14 takes into account the sign or the initial phase ((/ 180 °) with which the multi-position signal was transmitted and does not ensure the formation of the remaining four code 1H combinations, which are inverted with respect to the first four code combinations (see tab. The timing diagram of the signals at the output of the signal converter is shown in Fig. 86.

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, combinations from the output of the signal converter 14 are fed to the first input of the sign multiplier 15. The second input of the sign multiplier 15 is connected via a serially connected converter 23 of the relative code to the absolute and the first element HE 24 with the sign input of the decision unit 13.

Due to the fact that, in the proposed device, relative phase manipulation is used, information about the sign of the emitted signal at the output of the decision block 13 is presented in relative code. Therefore, in order to finally receive at the output of the receiver a sequence of binary information symbols transmitted using multi-position wideband signals with relative phase shift, it is necessary to present the binary sequence coming from the sign output of the decision block 13 in absolute code, and then with the opposite sign multiply with the sequence pulses received at the output of the converter 14 signals. A relative-to-absolute converter 23 compares the polarities of two adjacent binary symbols, if the polarities of the compared pulses are the same, then a pulse with a positive polarity is generated at the output. If the compared pulses have different polarities, a negative pulse is generated at the output of the converter 23. The timing diagram of the pulse sequence at the output of the converter 23 relative code in absolute is shown in Fig.8B. At the output of the first element HE 24, this sequence of pulses is inverted (Fig. 3g). The sign multiplier 15 compares the polarities of the pulses arriving at its two inputs. If these polarities coincide, then a positive impulse is formed at the output, if the compared polarities do not coincide, then a negative polarity impulse is formed at the output of block 15. As a result of a comparison of the polarities of the pulsed sequences received from the output of the signal converter 14. (Fig. 86) and

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the output of the first element NOT (Fig. 8d), the output information pulse sequence is formed at the output of the sign multiplier 15 (Fig. 8e).

Claims (3)

1. A device for transmitting and receiving multi-position wideband signals, containing on the transmitting side serially connected clock extractor, whose input is the device input, and sharing Clock clock gel, the output of which is connected to the Nerve input of the signal converting unit, N drivers of multi-position wideband signals, where N is any integer whose outputs are connected to the corresponding inputs of the output adder, as well as a radio transmitter, and on the receiving side - a wide-band n The receiver, whose input is connected to the combined inputs of parallel-connected signal processing branches, each of which contains a consistently connected matched filter, a multiplier and an integrator, while the integrator outputs of the N signal processing branches are connected to the corresponding inputs of the decision unit, each of the N outputs of which are connected to the corresponding the input of the signal converter and the input of the corresponding gate driver of the gating, the block, the formation of the reference signal, the element NOT and the block with The synchronization, the input of which is connected to the output of the reference signal generation unit and the second inputs of the multipliers N signal processing branches, and the output is connected to the synchronization input of the decision unit and the control inputs of the integrator N signal processing branches, the outputs of matched filters are connected to the corresponding first inputs of the forming unit the reference signal, which, in order to increase the noise immunity on the transmitting side, are introduced serially connected absolute code converter in tnositelny and phase manipulator, the input and output of which is connected with soootvetst- venno output of the output adder and the input of the transmitter, wherein 0 five 0 five 0 6 the input and output of the clock frequency selector are connected to the second and third inputs of the signal conversion unit, respectively, the outputs of which are connected to the inputs of the corresponding shapers of multiposition wideband signals, and the sign output of the signal conversion unit is connected to the input of the absolute code to relative converter, and at the receiving end A relative-to-absolute converter is entered in the absolute, the output of which is NOT connected to the first input of the signed sign multiplier, the output of which is the device output, and the second input is connected to the output of the signal converter, the auxiliary input of the reference signal generation unit the decision block and the input of the converter of the relative code to the absolute one, and the outputs of the voltage builders are connected to the second inputs of the block forming the reference signal. 2. Device POP.1, characterized in that the reference signal generating unit comprises serially connected delay lines whose inputs are the first inputs of the reference signal generating unit. A, gating units,: adder, multiplier, the output of which is the second output of the generating unit the reference signal, and a combed filter, the output of which is the first output of the reference signal generating unit, while the second inputs of the gating units are the second inputs of the reference signal generating unit. 3. Device POP.1, characterized in that the decision block contains N blocks for absolute voltage values, a block for determining the maximum signal, N first pulse formers, N threshold blocks, N And elements, OR element and a second pulse shaper, while the inputs blocks five ten 15 20  - - - 25 3453611 the absolute values of the voltages are connected to the inputs of the corresponding threshold blocks and are the inputs of the decision block, the outputs of the threshold blocks through the corresponding elements AND are connected to the corresponding inputs of the OR element, the output of which is connected to the input of the second pulse shaper, the output of which is the sign output of the decisive block , wherein the outputs of the absolute voltage value selection units are connected to the inputs of the corresponding first impreser through the maximum signal determination unit pulses whose outputs are the outputs of the decision block, the synchronization inputs of the second pulse former, the first pulse conditioners and the maximum signal determination unit are connected and are the synchronization input of the decision block, the second; the inputs of the elements And are connected to the corresponding; the outputs of the block for determining the maximum signal. FIG. 2 fig.Z „Known fyzl Blue II  . m I l i. . (yl “A I  j- / ttftF I and and g + / 44 -HD Type of “A I HD -XJ - / "g- Ai + / G4 TT Type 11 II KM P I /  I H-IZ I -b xtf I- Xf I + I II Fieb 1 1 1 11 J J 1 a MI O gptigti Editor S. Lisin Compiled by N. Lebed nska Tehred I. Popovich Corrector S. Cherni Order 4932/55 Circulation 635 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 I I