SU1653171A1 - Device for amplitude/phase modulated signal analysis - Google Patents

Abstract

The invention relates to telecommunications and can be used in data transmission systems. The purpose of the invention is to increase the speed of analysis. To achieve the goal, an error signal generation unit 7 is entered into the device, and the corrector 1 is made in the form of a properly connected delay block 8, block 9 adders, first and second adders 10 and 11, and block 12 controllable coefficients. The control of the moment of reading information is carried out with the help of signals taken directly from corrector 1 and proportional to the derivative of the criterion for tact, m. There is no additional delay in determining the control signal. 1 item f-ly, 1 ill.

Description

The invention relates to telecommunications and can be used in data transmission systems.

The purpose of the invention is to increase the speed of analysis.

The drawing shows a structural electrical circuit of a device for analyzing signals with amplitude-phase modulation.

The device for analyzing signals with amplitude-phase modulation contains a corrector 1, an analog-digital converter 2, a multiplier 3, a controlled oscillator 4, a demodulator 5 and a low-pass filter 6, as well as an error signal generating unit 7. The corrector 1, which is part of the device, contains a delay block 8, a block 9 of adders, a first and a second adders 10 and 11, and a block 12 of controlled coefficients,

The device for analyzing signals with amplitude-phase modulation operates as follows.

The input signal from the communication channel is fed to the demodulator 5, then to the low-pass filter 6 (LPF) and then to the analog-to-digital converter 2 (ADC) where it is read at discrete times in 1/2,

skel

G3

Here t

one

2f,

2Ј „- sledo frequency

information symbols) or - the main clock frequency), and fc is the passband of the low-pass filter 6. From ADC 2, the discrete signal is fed to the equalizer 1, and from its first output - to the error signal generation unit 7 and then to the device output. The signal from the first output of the error signal generation unit 7 is fed to the second (control) input of the equalizer 1 and

the second input of the multiplier 3. The control signal for the moment of reading information from the output of the multiplier 3 is fed to the controlled oscillator A and then to the clock input of the ADC 2.

From the outputs of block 8 of delay, block 9 of adders, block 12 of controllable coefficients, first and second adders 10 and 11, multiplier 3, and error signal generator 7, signals arrive at a time interval T, i.e. through the main clock interval.

A control signal for determining the read time is generated based on the rms quality criterion of the received signal at the receiver:

Q M (Xt) e, (1) where M is the expectation symbol;

7.1 - signal at the input of block 7 at the moment of time t;

Xi is the estimate of the transmitted signal in

time t0 Derivative of criterion (1) on

tact

Ё0 d € will be written in the form: on with- dZ

1 2Јt Z. - t error,

where t, t

Signal Z, received on Speaker 1, is equal to:

CJT

K1T-K

(3)

Ъ ЦшЛЛ | L

where С k are the controlled coefficients of the corrector whose values are stored in the block 12 of the controlled coefficients;

Y. - the value of the signals at the main outputs of the delay block 8, i.e. at the input of the first and the outputs of all the even taps of the block 8 delay; K - number of the main output.

to 0.1, ... n-i; 2p - the number of taps in the block

8 delays about

The signals at the outputs of two adjacent taps in block 8 delay shears by T / 2. Derivative value

-7v is roughly calculated as

the value is proportional to the difference of the values of Z., taken with a shift in time relative to the current point in time by + T / 2

dZ-t 1/7

dT T (

- Z

t-t / 2

). (A)

dO 2 g dZt Then -.--- -

(five)

and the read time is defined as:

- -fEt- -VfEtf: ,,.

t ,,

x (Y + - T / 2 - K - Y.

+ T / 2 - K),

five

0

five

0

five

0 5

0-

five

where y is the setting factor. (6) The signals YЈ - T / 2 - K are removed after the clock interval from the additional outputs of the block 8 delay, m0. from the outputs of all odd, taps, except the first, and arrive at the non-inverting inputs of block 9 adders. Signals Y Ј + T / 2 - K are also removed after the clock interval T from the descent of all even taps, except the last, and arrive at the inverting inputs of the adders 9 ". Therefore, all the inverting inputs of the block 9 adders, except the first, receive the same signals as and to the inverting inputs of previous adders „

The group of signals (Y - Т / 2 - К - - Y. + Т / 2 - К), (К 1,2 „.. п-1) from the outputs of block 9 of adders comes through clock intervals T to the first inputs of block 12 controls coefficients. Signals T / 2 - K - Y + + T / 2 - K) l are removed from the second outputs of the block 12 of controlled coefficients at clock intervals T "These signals are sent to the second adder 11, the output of which is the signal x (Yt - Т / 2 - К - Yt + Т / 2 - К 5 „

This signal in multiplier 3 is multiplied by the error signal from the output of the error signal generating unit 7. Thus, at the output of the reset switch "-1 l 3, a signal is formed.

x (Y4 - T / 2 - K - Y + T / 2). The controlled oscillator A, using the control signal, regulates the moment of reading, Ј petm, acting on the control input of the ADC 3 "

The control of the moment of reading 6 is carried out on the basis of the signals taken directly from the corrector 1 and proportional to the derivative of the criterion for the clock, i.e. There is no additional delay in the determination of the control signal. Therefore, the read time tuning time is reduced, which improves the quality of information reception, i.e. increases the noise immunity of the proposed system.

invention formula

Claims (2)

1 "A device for analyzing signals with amplitude-phase modulation, containing an equalizer, an analog-to-digital converter, sequentially, connected multiplier and controlled oscillator and a serially connected demodulator and low-pass filter, the output of which is connected to the first analog input a digital converter, the second input and the output of which are connected respectively to the output of the controlled oscillator and to the first input of the equalizer, and the input of the demodulator is an input of the device, characterized in that increase the speed of analysis; an error signal generation unit is inputted; the first input and output of which are connected respectively to the first output and the second input of the corrector, Q, j 5 20 25 31716 The second output of which is connected to the first input of the multiplier, the second input of which is connected to the first output of the error signal generation unit, the second output of which is the output of the device. 2. The device pop. adders, the corresponding outputs of the delay unit, and the inputs of the first and second adders, the outputs of which are respectively the first and second outputs of the equalizer, the first and second inputs of which are the input of the delay unit and the third input of the block of controlled coefficients, th input of the adder block connected to respective outputs of delay block.