SU1415445A1 - Device for synchronizing broad-band pseudo-random signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to expand the capture bandwidth without reducing the accuracy of synchronization. The device contains mixer 1, intermediate frequency amplifiers 2, A, 16, and 17, phase detectors 3 and 5, low pass filters 6, 12, and 21, controllable gasers 7 and 13, phase shifters 8 and 9, threshold unit 10, frequency detector 11, multipliers 14 and 15, amplitude detectors 18 and 19, adders 20 and 24, controlled clock r.r 22, rr 23 codes, demodulator 25, amplifier 26 and pulse counter 27. With large phase and frequency mismatches of the received and reference pseudo-random sequences in the frequency detector 11, an error voltage is formed, which is proportional to the output frequency of the V5 signal from the specified value. This signal is filtered by filter 12 and adjusts the frequency of Mr. 13. Phaser 8 to If / 2 provides for the formation of a discriminating x-ki phase-locked loop (in phase detector 5) phase difference. As a result, Mr. 7 adjusts in frequency so that the phase difference of the signals from the output of Mr. 7 and amplifier 4 reduces to zero. The phase shifter 9 compensates for the change in phase by passing the signal through the corresponding elements. The goal is achieved by introducing phase shifters 8 and 9, as well as those included in the circuit of the frequency auto-tuning of the frequency detector 11, filter 12 and r-13. 1 sludge. - t (L el 4 4 O1

Description

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The invention does not have e.h.t.-communication and can be used in information transmission systems that use broadband pseudo-random signals.

The purpose of the invention is to expand the capture bandwidth without reducing the accuracy of synchronization.

The drawing shows the structure of a jQ circuit electrical device for synchronizing broadband pseudo-random signals.

The synchronization device for broadband pseudo-random signals (PSS) 15 is proportional to the frequency drift of input mixer 1, first U11CH 2, first phase demodulator 3, second UTHC 4, frequency detector 11, additional low-pass filter 12, additional controlled reference oscillator 13). In this case, the signal from the output of the first phase detector 3, arriving at the input of the second IF amplifier 4 (narrowband IF amplifier), is filtered out from the combinational components occurring at large phase mismatches of the received and reference SRPs. Next, an error voltage is generated in frequency detector 11.

frequency-proportional input mixer 1, first U11CH 2, first phase demodulator 3, second UTHC 4, frequency detector 11, additional low pass filter 12, additional controlled reference oscillator 13). In this case, the signal from the output of the first phase detector 3, arriving at the input of the second IF amplifier 4 (narrowband IF amplifier), is filtered out from the combinational components occurring at large phase mismatches of the received and reference SRPs. Next, an error voltage is generated in frequency detector 11.

contains mixer 1, first intermediate frequency amplifier 2 (IF amplifier), first phase detector 3, second intermediate frequency amplifier 4 (IF amplifier), second phase detector 5, first low-pass filter 6 (LPF), controlled reference oscillator 7, first and second phase shifters 8 and 9, threshold unit 10, frequency detector 11, additional low-pass filter 12 (LPF), additional controlled reference oscillator 13, first and second multipliers 14 and 15, third and fourth amplifiers 16 and 17 intermediate frequency, first and second am-30 is a control signal scrap (through plate detectors 18 and 19, the first first low-pass filter 6) for the controlled support-adder 20, the second filter 21 of the lower generator 7. Phase shifter 8 frequencies (low-pass filter), controlled by the clock generator at the very best forming a generator of the generator 22, the generator 23 code, the second crime rate characteristic is the swarm adder 24, demodulator 25, auto-tuning usi-es (in the second phase clock 26 and the counter 27 pulses.

The synchronization device for broadband pseudorandom signals operates in the following manner.

The input signal is fed to the information before the progress of the last and second IFC 4, the free input of the mixer 1, which is (tends) to zero, which serves to transfer the signal to the specified intermediate frequency. The reference input of the mixer 1 receives a signal from the output of the additional jj-controlled reference oscillator 13. From the output of the mixer 1, the signal arrives at the input of the first IFCH 2 (wideband amplifier), which filters the combinational components of the frequency spectrum and passes the useful signal in the detector to the 5) phase difference. As a result, the controlled reference oscillator 7 adjusts in frequency so that the phase difference of the signals is taken out.

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In the first and second multipliers 14 and 15, the signal from the output of the first OFC 2 is multiplied by two simulation functions shifted by T, (Td is the duration of one discrete sequence of the PSS sequence). If one of the sequences in the FSS phase coincides to a greater degree, then at the output of the corresponding first or second multiplier 14 or 15, a harmonic signal will be generated at an intermediate frequency with a larger amplitude; In the third and fourth IFA 16 and 17, the signals from the outputs of the first and second multipliers 14 and 15 are filtered out of the high-frequency combinations determined by the width of the FSS spectrum. From the output of the first IFA .2, the signal enters the first phase detector 3, which serves to remove the memory bandwidth, to the reference input of which the memory bandwidth signal is output from the generator 23. If the frequency mismatch is large, then auto-tuning works (CHAP circuit:

signal from the specified value. The 3toT signal is filtered in an additional FR1H 12 and adjusts the frequency of the additional controlled reference oscillator 13.

When the frequency at the output of the second OFC 4 coincides with the nominal frequency within the capture band of the phase-locked loop at the output of the second phase detector 5, an error voltage is generated by the phase (frequency) of the harmonic signal from the output of the second IFCH 4. The voltage from the output of the second phase detector 5

is a control signal (via the first low-pass filter 6) for the controlled reference generator 7. Phaser 8 does not allow the formation of the discriminatory characteristic of the phase-locked loop (in the second phase

detector 5) phase difference. As a result, the controlled reference generator 7 adjusts in frequency so that the phase difference of the signals from the output is

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the course of the last and the second OAC 4 is reduced (tends) to zero

In the first and second multipliers 14 and 15, the signal from the output of the first OFC 2 is multiplied by two simulation functions shifted by T, (Td is the duration of one discrete sequence of the PSS sequence). If one of the sequences in the FSS phase coincides to a greater degree, then at the output of the corresponding first or second multiplier 14 or 15, a harmonic signal will be generated at an intermediate frequency with a larger amplitude; In the third and fourth IFA 16 and 17, the signals from the outputs of the first and second multipliers 14 and 15 are filtered out of the high-frequency combinational components obtained by multiplying the PSS sequences (supporting from the first and second outputs of the code generator 23 and from the output of the first U1FC 2) , arrive at the first and second amplitude detectors 18 and 1.9, which separate the voltage envelopes of the harmonic signals.

Voltages from the outputs of the first and second Q clock generator and code generator.

Amplitude detectors 18 and 19 are fed to the adder 20, where they are summed (added) in antiphase, which determines the magnitude of the error error voltage supplied through the second low-pass filter 21 to the input of the controlled clock generator 22, which synchronizes the code generator 23. From the first and second outputs, the first output of which is connected to the first input of the first multiplier, a second multiplier connected in series, a fourth intermediate frequency amplifier 15, a second amplitude detector whose output is connected to the second input of the first adder, a second adder connected in series, a demodulator and a amplifier 14 and 15 in the second totalizer 20, the output of which is connected to re 24, is coherent addition (since the same signal with

the third input of the first adder, serially connected threshold unit and a pulse counter, the output of which is connected to the control input of the amplifier, the output of the first intermediate frequency amplifier is connected to the second input of the first multiplier and the first input of the second multiplier, the second input of which is connected to the second output of the code generator, the third output of the code generator is connected to the reference input of the first phase detector, the outputs of the first and in the multiplier are connected responsibly to the first and second in the second summat pa, and the output of second-phase detector connected to the input of the threshold unit, the input mixer and the formational exhibits a

the output of the first IFA 2 is multiplied with different phases of the same code sequence). From the output of the second adder 24, the amplitude-modulated signal is fed to the input of demodulator 25, where the amplitude envelope is coherently extracted and the intermediate frequency is removed. The demodulator demodulator 25 receives the intermediate frequency signal from the output of the controlled reference oscillator 7 through the phase shifter 9, which compensates for the change in phase by passing the signal through the corresponding elements.

The fault voltage from the output of the demodulator 25 through the amplifier 26 is fed to the third input of the first adder 20, thereby contributing to the estimate of the total error of the error. The gain of amplifier 26 depends on the value of the number recorded in counter 27 switched on by threshold unit 10 with a corresponding value of the signal at the output of the second phase detector 5.

Claims (1)

Invention Formula 45 tor, additional low-pass filter and additional controlled reference oscillator, the output of which is connected to the reference input of the mixer, while the output of the second intermediate frequency amplifier is connected to the input of the frequency detector, the output of the controlled reference oscillator is connected via the inputted first and second phasers corresponding to the wideband synchronization device pseudo-random signals containing sequentially connected gg to the reference inputs of the second phase mixer, the first amplifier of the detector and the demodulator and the intermediate frequency, the first phase detector, the second amplifier is directly to the clock input, the pulse counter. Accurate frequency, second phase detector, first low pass filter and controlled reference oscillator, first multiplier connected in series, third intermediate frequency amplifier, first amplitude detector, first adder, second low pass filter, controlled the first output of which is connected to the input of the first multiplier, the second multiplier connected in series, the fourth intermediate frequency amplifier, the second amplitude detector, the output of which is connected to the second input of the first adder, the second adder connected in series, the demodulator and the amplifier connected to the third input of the first adder, a series-connected threshold unit and a pulse counter whose output is connected to the control input of the amplifier, the output of the first intermediate frequency amplifier is connected to the second input of the first multiplier and the first input of the second multiplier, the second input of which is connected to the second output of the code generator, the third the output of the code generator is connected to the reference input of the first phase detector, the outputs of the first and second multipliers are connected respectively to the first and second in Odam second adder, and the output of the second phase detector is connected to the input of the threshold unit, and the information input of the mixer is the input of the device, characterized in that, in order to expand the capture band without reducing the synchronization accuracy, a serially connected frequency detector, an additional low-pass filter and an additional controlled reference oscillator, the output of which is connected to the mixer reference input, are output, while the output of the second intermediate frequency amplifier connected to the input of the frequency detector, the output of the controlled reference oscillator is connected through the entered first and second phase shifters, respectively to the reference inputs of the second phase detector and demodulator and to the reference inputs of the second phase detector and demodulator and directly to the clock input pulse counter.