SU1215188A1 - Device for reception of phase-shift keyed signals - Google Patents

Abstract

The invention can be used in discrete information transfer systems by offset phase manipulation methods. Improved noise immunity is provided. The input signal is fed to phase detectors (PD) 2 quadrature channels 1. Each quadrature channel 1 contains a series-connected PD 2, a matched filter 3 and a decision block 4, from which the signal goes to the output of the device. On the PD 2 of the controlled generator (UG) 10, the reference voltage is applied through the phase splitter 11 with the shift f / 2. Optimally processed video signals from matched filters 3 are fed to multiplier 5, as a result of which the manipulation with the non-in-phase component is removed. With multiplier 5, the voltage is applied to the sample and hold blocks (BBX) 6,12. From these blocks, alternately in clock pulses shifted by the interval T, information about the phase mismatch of the UG 10 arrives at the adder 8. From the BVH 12 information to the adder 8 passes through the inverter, the torus 7, the voltage, the magnitude and sign of which are determined by the phase error voltage UG 10 relative to the input signal, through. the low-pass filter 9 arrives at UG 10. The goal is achieved by introducing an adder 8, two BVH, and an inverter. 1 il. с С f К «У1 00 CX

Description

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The invention relates to radio electronics and can be used in systems for the transmission of discrete information by offset phase manipulation methods (offset phase manipulation, manipulation with a minimum frequency shift and its modification).

The aim of the invention is to improve noise immunity.

Fig. 1 shows a structural electrical circuit of the proposed device.

The device for receiving phase-manipulated signals contains quadrature channels 1, phase detectors 2, matched filters 3, decision blocks 4, multiplier 5, first block 6 of sampling and storage, inverter 7, adder 8, low pass filter 9, controlled by generator 10, phase splitter 11, second sampling and storage unit 12

The device works as follows.

The input signal is in-phase with the phase detectors 2 quadratures of channel 1, and the second inputs of phase detectors 2 with a CTG | 2 shift provide the reference voltage from the controlled generator 10 through the phase splitter 1 1. The output signals from the phase detectors 2 are each processed optimally. matched filters 3 and arrive at decision blocks 4, where a decision is made about the sign of the received signal at the times determined by the clock pulses and corresponding to the maximum signal-to-noise ratio in the channel. In addition, the optimally processed video signals from the outputs of matched filters of the 3 quadrature channels 1 are fed to the inputs of the multiplier 5 where their analog multiplication occurs. As a result of multiplying the video signals of the quadrature cabals 1, the manipulation with the non-phase component of each of the quadrature channels 1 is removed. The voltage from the output of the multiplier 5 is simultaneously applied to the blocks 6 and 12 of the sample and storage, in which the input voltage is sampled at the moment of arrival of the control pulse and storage (memorization) of the selected sample. On the second

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the inputs of blocks 6 and 12 of the sample and the storage are fed by narrow clock pulses with an interval of 2 T and shifted between each other by T, which is done 5 taking into account the principle of forming signals during offset manipulation methods. Thus, the clock pulses arriving at blocks 6 and 12 of the sample and storage correspond to 10 points in time when there is a maximum voltage from the code of the matched filter 3 in one quadrature channel and at least another. Junction at the outputs of the matched 5 filters 3 in clocks with

The accuracy of the sign (due to the presence of manipulation) is proportional to the phase detuning of the controlled oscillator 10. Using the multiplier 5 to remove the manipulation allows obtaining control voltages for the controlled oscillator 10 and ensuring the normal operation of the phase auto-amplified ring. 25 royki frequency (AFC). In accordance with the time points determined by the clock pulses, block 6 and 12 of sampling and storage once for a time interval of 2 T performs 30 sampling and storing of the voltage level coming from the output of multiplier 5, and stores this value for a time T, after that, the same time interval T goes to 35 initial state before the arrival of a new team to take a sample. Since the clock pulses arriving at blocks 6 and 12 of the sample and storage are shifted between themselves by the interval T, 40 information about the phase detuning of the controlled generator 10 during the time T appears alternately at the outputs of blocks 6 and 12 of the sample and

storage. If the command on the sample and. 45 storing information about the phase detuning of the controlled oscillator 10 into blocks 6 and 12 of sampling and storage is given by the clock pulses of the corresponding in-phase channel, then the command to go to the initial state can be performed by the clock pulses of the quadrature channel, as shown in Fig. 1 dotted lines.

55 Such an algorithm of operation of blocks 6 and 12 of sampling and storage is not the only one; information about the phase detuning of the controlled generator

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10 may xpatiHTbCH for a time of 2 T, but this leads to some equivalent increase in the delay in the F-11CH control loop, which is not always acceptable. The magnitude of the voltage - 5 at the output of each unit 6 and 12 of the sample and storage is determined by the value of the phase error of the reference voltage from the output of the controlled generator 10 relative to the input signal, measured at the moments of arrival of the pulses to the corresponding block 6 and 12 of the sample and storage and the sign of the voltage at the outputs of blocks 6 and 12 of the sample and storage is determined by the sign of the phase error of the reference voltage relative to the input signal. It should be noted that the voltage values at the outputs of blocks 6 and 12 of the sampling and storage are identical in modulus, but opposite in sign, therefore before applying these voltages to the inputs of the adder 8 between the second input of the adder 8 and the output of the sampling and storage unit I2, the inverter is turned on 7. Thus, the magnitude of the useful voltage at the output of the adder 8, updated each time interval T, is completely determined by the magnitude and sign of the phase error of the reference voltage from the output of the controlled oscillator 10 relative to the input signal.

The resulting discriminatory characteristic of the proposed device, i.e. The dependence of the voltage at the output of the phytra 9 of the lower frequencies on the phase error of the reference voltage relative to the input signal when the device is fed to the device signals using offset manipulation methods has the form .11 / 2, where is the phase detuning of the controlled generator 10 relative to the nominal value. Such discriminatory characteristics

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Compiled by V. Chibisov Editor M. Kelemesh Tehred M. Nadi Corrector A. Obruchar

Order 912/60 Circulation 624 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PPP Patent, Uzhgorod, st. Project, 4

88

This device ensures the normal operation of the PLL of the controlled oscillator 10 by the input signal with offset manipulation methods .1

Claims (1)

Invention Formula A device for receiving phase-manipulated signals containing a multiplier, a low-pass filter whose output is connected to the phase splitter through a controlled oscillator, and in each of the quadrature channels - a serially connected phase detector, matched filter and a decisive block, with the first inputs phase detectors are combined, the second inputs of phase detectors are connected to the corresponding outputs of the phase splitter, the outputs of matched filters are connected to the corresponding inputs of the multiplier, the first inputs of the phase detectors are the signal inputs of the device, the clock inputs of which are the clock inputs of the decisive blocks, characterized in that, in order to increase the noise immunity, an adder, an inverter and two sampling and storage units are entered, the first inputs of which connected to the multiplier output, the output of the first sampling and storage unit is connected to the first input of the adder, the second input of which is connected to the output of the inverter, the input of which is connected to the output of the second block ki and storage, and the output of the adder is connected to the input of the low-pass filter, and the second inputs of the first and second blocks of sampling and storage are connected to the clock inputs of the decisive blocks of the corresponding quadrature channels.