SU1113894A1 - Clock synchronizing device - Google Patents

Abstract

A COLLATED SYNCHRONIZATION DEVICE containing a series-connected bandpass filter, an amplifier-limiter and a differentiating unit, series-connected gate driver and a delay line, the input of the band-pass filter and the output of the delay line being, respectively, the input and output of the device synchronization accuracy; a sequentially connected controlled integrating unit and a controlled delay line are introduced, with information and control The inputs of the controlled integrating unit are connected respectively to the outputs of the limiting amplifier and the gating pulse shaper, and the information input and output of the controlled delay line 5 are connected respectively to the output of the differentiating unit and the gating pulse shaper input.

Description

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Phie. The invention relates to telecommunications engineering and can be used for clock synchronization in communication systems with pulse code modulation and delta modulation. A clock synchronization device is known that contains a series-connected sync signal extraction unit, a bandpass filter, a sync pulse generator and a switching unit, a signal envelope detector and a threshold unit connected in series, as well as a delay unit whose input and output are connected respectively to the output and the second input of the unit switching, and the input of the detector envelope signal and the output of the threshold unit are connected respectively to the output of the band-pass filter and the third input of the switching unit of the CPU. A disadvantage of the known clock synchronization device is the low synchronization accuracy. The closest technical solution to this invention is a clock synchronization device containing a serially connected bandpass filter, an amplifier-limiter and a differentiating unit, serially connected gating pulse generator and a delay line, with the input of the bandpass filter and the output of the delay line being the input and output of the device, and the output of the differentiating unit is connected to the input of the gating pulse former 2. The disadvantage of the known device is tovoy synchronization is the low accuracy of synchronization. The purpose of the invention is to improve the synchronization accuracy. To achieve this goal, a clock synchronization device containing a series-connected bandpass filter, an amplifier-limiter and a differentiating unit, serially connected gate generator and a delay line, the input of the band-pass filter and the output of the delay line being the input and output of the device, respectively. connected in series a controllable integrable ifi block and a controllable delay line, with the information and control inputs of the controllable integrating The first block is connected respectively to the outputs of the amplifier-limiter AND the gating pulse shaper, and the information input and output of the controlled delay line are connected respectively to the output of the differentiating unit and the input of the gating pulse shaper. FIG. 1. a structured electrical circuit of the clock synchronization device; in fig. 2 time diagrams. Demonstrating the operation of the clock synchronization device. The clock synchronization device contains a band-pass filter 1, a limiting amplifier 2, a differentiated block 3, a controlled delay line 4, a gate clock 5, a delay line 6, and a controlled integrated block 7. The pulses of the digital signal are fed to the input of the bandpass filter 1 (Fig. 1). In this case, a quasi-harmonic oscillation occurs at the output of the bandpass filter 1, one of the possible implementations of which is shown in FIG. 201 The signal from the output of the bandpass filter 1 is fed to the input of the amplifier-limiter 2, which has a certain deadband (dotted line on 1FIG 2. The limiting amplifier 2 responds only to the positive half-wave of the input signal and generates rectangular pulses normalized in height and varying in width depending on the amplitude of the quasi-harmonic oscillation, (Fig. 2S) j, which is a consequence of the presence of a dead zone in it. These pulses are symmetrical with respect to the maximum (amplitude) values of q a harmonic oscillation is fed to the information input of the controlled integrating unit 7 and to the input of the differentiating unit 3. The controlled integrating unit 7 produces a voltage proportional to the width of the input pulse, which after the end of the input of the rectangular pulse is kept unchanged at its output until the moment of suppression. at the control input of the controlled integrating unit 7 short pulses from the output of the gate generator 5 ,. which bring it to its initial state (Fig 2fe and 2e, 31 A constant voltage proportional to the pulse duration at the input of the controlled integrated unit 7, from the output of the latter is fed to the control input of the controlled delay line 4, to the information input which, short negative pulses (Fig. 2d) formed by differentiation by block 3 are simultaneously delivered.The delay time of the controlled delay line 4 is inversely proportional to the magnitude of the control voltage, Yrie, its parameters are chosen so that when from the side of the control input from zero to the maximum value (which corresponds to the pulse width at the information input of the controlled integrating unit 7 from zero to the half-period value of the quasi-harmonic oscillation) a delay of the input 1x pulses respectively from a quarter of the quasi-harmonic oscillation period to zero. the remaining cases, the pulses are delayed within a specified interval

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1 44 at a time inversely proportional to the control voltage. With this choice of operating mode, short pulses (Fig. 2d), fluctuating in phase at the output of the controlled delay line 4, appear at times coinciding with the moments of transition of the quasi-harmonic oscillation through zero, which leads to a sharp decrease in their phase fluctuations ( Fig. 2o, 2e). The short rectangular pulses (Fig. 2e) formed by the gating pulse shaper 5, passing through the delay line 6, acquire the necessary temporary positions. Thus, in the pre-set clock synchronization device, the temporary position of the individual gating pulses is continuously corrected. This is achieved by appropriate processing of the quasi-harmonic signal, which leads to a decrease in the phase jitter of the strobe pulses and, therefore, to an increase in the synchronization accuracy.

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Claims (1)

A TACT SYNCHRONIZATION DEVICE comprising a serially connected bandpass filter, an amplifier-limiter and a differentiating unit, serially connected to a gate pulse generator and a delay line, the input of the bandpass filter and the output of the delay line being the input and output of the device, characterized in that, for the purpose of _z synchronization accuracy, introduced in series connected controlled integrating unit and controlled delay line, while information and control in the strokes of the controlled integrating block are connected respectively to the outputs of the amplifier-limiter and the gate pulse shaper, and the information input and the output of the controlled delay line are connected respectively to the output of the differentiating block and the input of the gate pulse shaper. Fig 1 1 '11138