JPS5451411A - Monitor system of error rate - Google Patents

Monitor system of error rate

Info

Publication number
JPS5451411A
JPS5451411A JP11742377A JP11742377A JPS5451411A JP S5451411 A JPS5451411 A JP S5451411A JP 11742377 A JP11742377 A JP 11742377A JP 11742377 A JP11742377 A JP 11742377A JP S5451411 A JPS5451411 A JP S5451411A
Authority
JP
Japan
Prior art keywords
signal
gate
demodulator
binary
error rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11742377A
Other languages
Japanese (ja)
Inventor
Shunroku Sasaki
Tadashi Sekizawa
Yoshitoshi Tsuji
Tadayoshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11742377A priority Critical patent/JPS5451411A/en
Publication of JPS5451411A publication Critical patent/JPS5451411A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/206—Arrangements for detecting or preventing errors in the information received using signal quality detector for modulated signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To perform the monitoring of the symbol error rate at the three phase PSK modulation signal and to simplify the unit, by obtaining the probability of vector generaton not used. CONSTITUTION:The input hree phase PSK modulation signal is outputted as a binary signal via the hree phase demodulator 2 and the ternary to binary converter 3. In this case, signal conversion at the modulator 3 is made with the word synchronous signal S1 separated with the demodulator 2 and the symbol clock S2. On the other hand, the binary signal output a3 of the demodulator is inputted to the AND gate 7 and FF5, and the signal S3 delayed by one clock is outputted from FF5 with the singal S2 and it is fed to the gate 7. Further, the signal S1 is fed to the gate 7 after inversion 6. Accordingly, the gate 7 outputs the signal S4 when the signal a3 is 1 in continuity with two periods of the signal S2, the gate 7 outputs the signal 4 and the probability of vector generation can be obtained by counting 8 the signal S4 for a given time.
JP11742377A 1977-09-30 1977-09-30 Monitor system of error rate Pending JPS5451411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11742377A JPS5451411A (en) 1977-09-30 1977-09-30 Monitor system of error rate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11742377A JPS5451411A (en) 1977-09-30 1977-09-30 Monitor system of error rate

Publications (1)

Publication Number Publication Date
JPS5451411A true JPS5451411A (en) 1979-04-23

Family

ID=14711268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11742377A Pending JPS5451411A (en) 1977-09-30 1977-09-30 Monitor system of error rate

Country Status (1)

Country Link
JP (1) JPS5451411A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008208519A (en) * 2007-02-23 2008-09-11 Megatekku:Kk Soundproof structure
JP2009074273A (en) * 2007-09-19 2009-04-09 Nippon Sheet Glass Environment Amenity Co Ltd Panel device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008208519A (en) * 2007-02-23 2008-09-11 Megatekku:Kk Soundproof structure
JP2009074273A (en) * 2007-09-19 2009-04-09 Nippon Sheet Glass Environment Amenity Co Ltd Panel device

Similar Documents

Publication Publication Date Title
ES464023A1 (en) Digital phase lock loop circuit and method
JPS5451411A (en) Monitor system of error rate
JPS558166A (en) Data transmission system
JPS5260515A (en) Intermediate frequency phase compounding device
JPS5637755A (en) Multiphase modulating device
JPS52109811A (en) Amplitude phase modulation communication system
SU570026A1 (en) Device for measuring time intervals
JPS5572248A (en) Function discrimination system for lsi
JPS5366110A (en) Waveform transmitting system
JPS5530232A (en) Demodulator on n-phase phase shift keying system
JPS5361375A (en) Counting circuit apparatus
JPS5263655A (en) Data converting device
JPS5378743A (en) Multiplier
JPS5354935A (en) Information converting device
JPS5558649A (en) Error rate monitor unit
JPS53139968A (en) A-d convertor
JPS52149110A (en) Anologue-digital conversion
FR2339291A1 (en) Digital data transmission method - uses phase modulation of carrier wave and removes ambiguity arising from phase reference of carrier
JPS55149554A (en) Carrier reproducing circuit
SU627597A1 (en) Apparatus for receiving synchronizing recurrent train
JPS5293206A (en) Data transmission system
JPS5466062A (en) Clock synchronous circuit
JPS53115145A (en) Automatic shift code insertion circuit
JPS52107724A (en) Segment signal generator
JPS5412617A (en) Frame synchronizing circuit