SU627597A1 - Apparatus for receiving synchronizing recurrent train - Google Patents

Description

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The invention relates to communication technology and can be used in data transmission systems whose information signal is formed by recurrent sequences.

A device for receiving a synchronizing recurrent sequence is known, comprising a series-connected multiplication unit for a generator polynomial, a division unit for a generating polynomial and a major processing unit {l. However, this device has a long time for receiving a synchronizing recurrent sequence.

The purpose of the invention is to reduce the reception time of the synchronous recurrent sequence in the presence of single and double errors and with the alternation of the polarity of the pulses of the input sequence.

For this purpose, in the device for receiving a synchronizing recurrent sequence, containing a sequence | but connected multiplication unit for a generator polynomial, a division unit for a generator polynomial and a majority processing unit, a shift register, two error detection units, two OR elements, an inverter

and a zero-sequence decoder, wherein the output unit multiplied by a polynomial is connected to the input of the shift register and to one of the inputs of the first error detection unit directly and through an inverter to one of the inputs of the second error detection unit, the outputs of which through the first OR element are connected to the single input dividing unit by generator polynomial, to the zero input, which the outputs of the first error detection block are connected through the second OR element, to the corresponding input of which are connected flax unit outputs the multiplication by the generator polynomial by the decoder zero sequence, wherein the other inputs of the first and second error detection units are connected respectively; The straight: and inverted outputs of the shift register.

The drawing shows a structural electrical circuit of the proposed device.

A device for receiving a synchronous recurrent sequence containing a series-connected multiplication unit 1 for a generator polynomial, a division unit 2 for a generator, its polynomial and a unit 3 for majority processing / as well as a register

4 shifts, two error detection 5.6 blocks, two elements OR 7.8, an inverter 9 and a zero-sequence decoder 10, with the output of the block

1 multiplied by the generator polynomial is connected to the input of the shift register 4 and to one of the inputs of the first block

5 error detection directly and through the inverter 9 to one of the inputs of the second error detection unit 6, the outputs of which through the first element OR 7 are connected to the single input of the division unit 2 into a generator polynomial, to the zero input of which the outputs of the first error detection unit 5 are connected through the second element OR 8, to the corresponding input of which the additional outputs of block 1 are multiplied

to the generating polynomial through the zero-sequence decoder 10, the direct and inverse outputs of the shift register 4 being connected to the other inputs of the first and second error detection blocks 5.6.

 The device works as follows.

The input binary signal, formed by a recurrent sequence with alternating polarity, goes to multiplication unit 1, which multiplies the sequence by the generator polynomial. From the output of block 1, the signal is fed to the input of block 2, dividing by the generating polynomial.

The detection units 5.6 operate based on the analysis of the output signals of the multiplication unit 1, setting zero or single initial conditions in division unit 2 whenever the input signal does not contain an error for a number of ticks equal to the order of the generating polynomial, or the same number of cycles contains a single or paired error, which sometimes appear in communication systems using relative phase modulation.

From the output of dividing unit 2, the signal arrives at majoritarian processing unit 3, which produces a selection of the law of polarity recurrent signal. Detection unit 5 records the absence of errors, the presence of a single error and the presence of paired} errors when there is no SIV inversion of the input sequence, and detection unit 6 registers the absence of errors, the presence of a single error and the presence of a paired error in the inversion of the input sequence.

The output signal of the detection unit 5 sets the triggers of the shift register 11 to the zero state, and the detection unit 6 sets the triggers of the shift register 12, the output of which is connected to the adder 13, to the state. If there are no errors in the input signal during 2 AND clock cycles, where n is the length of the 11 (12) shift (i.e.

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the degree of the generating polynomial) is either single or paired

an error during the same number of clock cycles, then block 5 (6) of detection through the element OR 7 (8), depending on the law of polarity reversal of the input sequence, establishes initial conditions in shift register 11. block 2 division.

If there is no signal at the device input, the decoder 10 through the element OR 8 sets the initial conditions in the register 11 of the division unit 2. From the output of dividing unit 2, the signal is fed to the input of unit 3, which performs majority processing.

Claims (1)

1. USSR author's certificate No. 262942, cl. H 04 L 7/00, 1968. to P L 13 No.-t P f f f f ( L I I t. I hrfMf