SU555553A2 - Digital delay tracking device - Google Patents

Description

(54; DIGITAL MONITORING DEVICE FOR DELAYS

one

The invention relates to communication technology, namely to digital devices for tracking delay in data transmission and telegraphy systems.

According to the main author's certificate №467489, a smart delay-tracking device is known, containing a reference generator of pseudo-random video sequences, the output of which is connected to one input of two multipliers, the other inputs of which are connected to the input bus, and the outputs to control inputs of a reversible counter and modulator two the output of which is connected to one input of the element I, the other input of which is connected to the output of the quartz oscillator, and the output of the element AND is connected to the counting input of the reversible counter ka, outputs of addition and subtraction of NIN which are connected to two inputs of the control element, the third input of which is connected to the output of the crystal oscillator, and the output of the control element through a divider is connected to the advancement bus of the reference generator of pseudorandom video sequences l.

Such a device has a significant time to synchronize due to the need to establish word synchronization (by the function of modulating the input signal.

The circuit of the invention is shortening the search for synchronism for arbitrary waveforms.

To do this, a digital delay tracking device contains a reference generator of pseudo-random video sequences, the output of which is connected to one input of two multipliers, the other inputs of which are connected to the input strip, and the outputs to the control inputs of a reversible counter and modulo adder two, the output of which is connected to one input of the element And, the other input of which is connected to the output of the crystal oscillator, and the output of the element And is connected to the counting input of the reversible counter, the outputs of which are added and subtracted from unified with two inputs of the control member, the third input of which is connected to the output of the crystal oscillator, and an output control element cherez Delhi Tel is connected to the bus of advance of the reference oscillator pseudo video sequences introduced delay line. In this case, the device input is connected to the information input of one of the multipliers through the delay line, and directly to the additional input of the reference generator. FIG. Figure 1 shows the electrical structure of a digital delay tracking device; in fig. 2 and 3 are embodiments of this device. The device contains a reference generator 1 of pseudo-random video sequences, the output of which is connected to one of the inputs of multipliers 2, 3, an additional input of the reference generator 1 and another input of multiplier 2 are connected to the input bus directly, and the information input of multiplier 3 through the newly entered delay line 4, outputs multipliers 2, 3 are connected to the control inputs of the reversible counter 5 and the adder 6 modulo two, the output of which is connected to one input of the element AND 7, the other input of which is connected to the output to generator generator 8. The output of the element 7 is connected to the counting input of the reversible counter 5, the addition and subtraction outputs of which are connected to two inputs of the control element 9, the third input of which is connected to the output of the crystal oscillator 8, and the output of the control element 9 through the divider 10 is connected to the reference Generator 1. A feature of the design of the device shown in FIG. 2 is that the information input of multiplier 2 and the input of delay line 4 are connected to its input, the output of which is connected to the second input of multiplier 2 and the information input of multiplier 3 directly, and to another input of multipliers 3 via the reference generator, 1, working in regenerator mode. The feature of the device shown in FIG. 3 is that the reference generator 1 and the delay line 4 are made in the form of a two-bit register 11. The input of the two-bit register 11 is combined with the information input of the multiplier 2 and with the input of the device. The output of the first bit of register 11 is connected to the second input of multiplier 2 and the information input of multiplier 3, and the output of the second bit of register 11 is connected to S5 with the second input of multiplier 3, the half-touch output of divider 1O is connected to the forward bus of the first bit of register 11, and the clock output - to the promotion tire of the second category.

60 of the regular register 11 and multiplier 2, the device operates as follows. The input signal is fed to the inputs of two multipliers 2, 3. The signal enters the multiplier 3, it passes the delay line 4. The multiplier x 2, 3 multiplies the input signal with the reference signal. The latter is formed by the reference generator 1 from the input signal. The reference signal has a delay of t / g relative to the input signal in a steady state, where G is the duration of the element of the input signal. The signals from the outputs of the multipliers 2, 3 control the operation mode of the reversible counter 5, to the counting input of which, through the element 7, receives a sequence of pulses from the output of the crystal oscillator 8. The resolution to the element 7 is fed from the adder 6 modulo two only at that moment at the outputs of multipliers 2, 3 there are signals of different Signs. This operation is identical to the subtraction operation and ensures the operability of the reversible counter 5, which integrates the difference, thus ensuring the formation of a discriminative characteristic. In control element 9, depending on the error sign, pulses are added to the input sequence from the crystal oscillator 8 or subtraction. Clock pulses are generated by divider 10. The input signal in the device, izbrbrazhen- ny in Fig, 2, is fed to the inputs of the delay line 4 and the perimeter 2, which form an autocorrelator torus. The signal from the output of the multiplier 2 constantly affects one of the control buses for the operation of the reversible counter 5 (for example, addition, the signal from the output of the delay line 4 goes to one of the inputs of the multiplier 3 directly, and the regenerated signal from the output Oscillator 1. Delay line 4, multiplier 3, reference generator 1 form a second autocorrelator torus with a controlled delay. Depending on the desaturation sign of the input and regenerated usb at the output of the multiplier 3, it forms The device operates similarly to the device shown in Fig. 1. The input signal in the device, shown in Fig. 3, is post-input to the inputs two times the signal from the output of the first register bit 11. the two signals received at the output of the multiplier 2 depends on the phase difference between the multiplied signals.The multiplier 3 multiplies the signals from the outputs of both bits of register 11, the phase difference of which is always constant and equal to T /, where tr is q itelnost input element. Clock and half-pulse pulses are formed by a divider 9. Next, the device operates similarly to the device shown in FIG. one.

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Claims (1)

The invention claims Digital delay tracking device according to author's certificate No. 4667489, characterized in that, in order to shorten the search for synchronism for arbitrary signals, a delay line is inserted, and the device input is connected to the information input of one of the multipliers via the delay line , and with an additional input of the reference generator - directly. Sources of information taken into account in the examination: 1. USSR Copyright Certificate №467489, M. KI N, 1973. ten