SU651447A1 - Zero beat discriminator - Google Patents

Description

- (54) DISCRIMINATOR OF ZERO BEATS

through the additional phase inverter CF the corresponding inputs of the second additional switch, wherein the control inputs of the additional switches are connected to the output of the reference element, and the outputs are in the discriminator zero zero biases.

The drawing shows a structural electrical diagram of the proposed device.

The zero beat discriminator contains two quadrature channels 1,2, each of which includes in series phase detector 3, low pass filter 4, key 5, to another input of which clock pulses, memory block b, differentiating circuit 7 and switch 8, another whose input through the phase inverter 9 is connected to the output of the differentiating circuit 7, and the control input to the output of the block for determining the sign of the signal 10, in each of the quadrature channels 1 and 2 the differentiating circuit7 is made in the form of serially connected delay lines 11 and deduction The tester 12, the second input of which is connected to the input of the delay line 11, the input of the sign determining unit of the signal 10 is connected to the output of the subtractor 12, the summation sign determining unit 13 is connected to each of the quadrature channels 1 and 2, the inputs of which are connected to the input and output of the delay line 11, and the equivalence element 14, the first input of which is connected to the output of the signal determining unit of the signal 10, and the output of the second input of the measuring unit for determining the sign of the sum 13 of another quadrature channel, are connected to the outputs of the switches 8 connected in parallel to the turns common for both quadrature channels 1 and 2, the comparison element 15 and the additional switch 16, equivalent to the outputs of the elements 14, are connected directly and the other through the additional phase inverter 17, the corresponding inputs of the second additional switch 18, while the control inputs of the additional switches 16, 18 are connected to the output of the reference element 15, and the outputs are the outputs of the zero beat discriminator, the inputs 19,20,21,22, the outputs 23,24.

The device works as follows.

When the phase detectors 3 are supplied to the inputs of a coherent-pulse signal UQ with a carrier frequency f and opon oscillations with a frequency fQf, shifted relative to each other by 90 °, the output of the memory blocks 6 are formed in series of square pulses with a duration and period of duration equal to the duration and the period following the selection of them

pulses. These sequences are modulated by oscillations with a frequency FQ, defined as Pd - f,

shifted relative to each other by 90. Delay lines 11 delay these sequences for the period following the selection pulses. The sums of the sign of the sum of the sign of 13 determines the signs of the sum of the signals in the input and output lines of the delay lines 11. The subtractors 12 determine the difference of the same signals, and the blocks of the sign of the sign of the signal 10 determine the signs of the differences. The elements of equivalence 14 produce a logical unit if the same logical signals (a pair of logical zeros or a pair of logical ones) are received at their inputs. The logic signals at their output depend only on the sign of the frequency,

F sign change,

and at

these signals are reversed. In this case, the signal at the output of the memory block 6 has the form

Hm (.

The signal at the output of the memory block 6 has the form

UioCna - U 6in (L5PTCHch o

The difference of signals Ugfn 1 of the same signal delayed for a period is

AUqCn -2U cos (ftjnT -. V5in- The sum of the signals of the same signal delayed for a period is

and, “Cn (5g., PT- .4i, xo5. We multiply iUqCnaMaTlu QLnl and. get

UjCnl (ftjnT- - 4 o) 5inftjT. Similarly, you can get

Ujji: n Au cm.sugCn: i -2u bin (ftjnT- wSi J

where nj is the signal difference, EUqCnl is the sum of the signals UgCnl and u jLn-ll.

The sign of the quantities Uj InJ and Ujj n depends only on the sign of the factor SinSljT (T.e. On the sign of Si), since other factors are always positive. However, for some values of and n, the signals Uj n or Ujj In are zero, and the sign, therefore, cannot be reliably determined.

But if you choose from the signals Uj. Gp1i and UjjCn signal with the highest amplitude and determine the sign of and. This result of determining the sign will not depend on tfo and n, TI, k.

 n and uj ,. n) equal

signals

zero at different times. In the proposed device, in order to simplify it, the values of Uj n and Uj. n is not calculated, only the sign of these quantities is determined by the signs of the factors. The elements of equivalence are used for this. Switches 8 are controlled by signals from the outputs of the signal determining unit 10, and they switch signals taken from the input and output of the phase inverter 9, so that the output of the switches 8 always produces positive polarity . Comparison element 15 compares the values of the signals at the outputs of the switches 8 and controls the additional switches 16,18. As a result, the second additional switch 18 connects the output 24 to the equivalent element 14 of the quadrature channel, where the signal is greatest. The additional phase inverter 17 is turned on due to the fact that the fif sign on the element output, the equivalence of the 14 quadrature channel 2 n) is reversed (the signal U The additional switch 16 switches the signals available on the outputs of the switches 8, so that the output 23 Thus, at output 24, a signal (logical O or) is dependent on the sign of Pj / and output 23 is a signal depending on the value of / sinfJjT /, and the polarity of these signals does not depend on the initial phase of the signal at input 19 and from the current time and sufficient There are only two pulses at the input of the device to determine the sign of the beat frequency Fj. Thus, the proposed device has a significantly increased speed. For mula of the invention Zero beat discriminator containing two quadrature channels, each of which has a phase filter connected in series key, the other input of which is supplied with clock pulses, a memory block, a differentiating circuit and a switch, the other input of which is connected through the phase inverter to the output of the differentiating circuit, and the control input - to the output of the signal determining unit of the signal, that is, in order to increase the speed, in each quadrature channels the differentiating circuit is made in the form of serially connected delay lines and subtractors, the second input which is connected to the input of the delay line, the input of the sign determining block of the signal is connected to the output of the subtractor, the sum of the sign of the sum sign, the inputs of which are connected to the input and output of the delay line, and the element equivalence, the input of which is connected to the output of the signal sign determining unit, and the output of the summation sign of the sum of the other quadrature channel is connected to the second input, the parallel and common inputs for the quadrature channels and the additional switch are connected to the switch outputs, and the other through the additional phase inverter, the corresponding inputs of the second additional switch, and the control inputs of the additional commutators The tators are connected to the output of the reference element, and the outputs are the outputs of the zero beat discriminator. Sources of information taken into account during the examination 1. USSR author's certificate No. 490263, cl. H 03 K 5/18, 1974.